We consider the optimal average cost of variable length source code averaged with a given probability distribution over source messages. The problem was argued in Csiszar and Korner's book. In a special case of binary alphabet, we find an upper bound to the optimal cost minus an ideal cost, where the ideal cost is the entropy of the source divided by a unique scalar that makes negative costs logarithmic probabilities. Our bound is better than the one given in the book.

A distributed congestion avoidance scheme, the End-to-End Rate Control Algorithm (EERCA), has been proposed for Available Bit Rate (ABR) service. In this work, we enhance EERCA by replacing the Queue Occupancy Reduction with the queuing delay control (QDC), which manipulates the queue occupancy more efficiently with less functional complexity. Furthermore, it alleviates per-VC accounting requirement and thus reduces the complexity of a switch. From both the analysis and the simulation, it shows that the proposed virtual queue occupancy precisely reflects the variation of the actual queue occupancy. This enhanced EERCA features higher efficiency and more stable queue occupancy than the original algorithm.

In 1995, 8 kb/s CS-ACELP coder of G.729 is standardized by ITU-T SG15 and it has been reported that the speech quality of G.729 is better than or equal to that of 32 kb/s ADPCM (G.726). However G.729 is the fixed rate speech coder, and it does not consider the property of voice activity in mutual conversation. If we use the voice activity, we can reduce the average bit rate in half without any degradations of the speech quality. In this paper, we propose an efficient variable rate algorithm for G.729. The variable rate algorithm consists of two main subjects, the rate determination algorithm and the design of sub rate coders. For the robust VAD algorithm, we combine the energy-thresholding method, the phonetic segmentation method by integration of various feature parameters obtained through the analysis procedure, and the variable hangover period method. Through the analysis of noise features, the 1 kb/s sub rate coder is designed for coding the background noise signal. Also, we design the 4 kb/s sub rate coder for the unvoiced parts. The performance of the variable rate algorithm is evaluated by the comparison of speech quality and average bit rate with G.729. Subjective quality test is also done by MOS test. Conclusively, it is verified that the proposed variable rate CS-ACELP coder produces the same speech quality as G.729, at the average bit rate of 4.4 kb/s.

In this paper, we propose a preemptive priority handoff scheme for integrated voice/data cellular mobile systems. In our scheme, calls are divided into three different classes: handoff voice calls, originating voice calls, and data calls. In each cell of the system there is a queue only for data calls. Priority is given to handoff voice calls over the other two kinds of calls. That is, the right to preempt the service of data is given to a handoff voice call if on arrival it finds no idle channels. The interrupted data call returns to the queue. The system is modeled by a two-dimensional Markov chain. We apply the Successive Over-Relaxation (SOR) method to obtain the equilibrium state probabilities. Blocking and forced termination probabilities for voice calls are obtained. Moreover, average queue length and average transmission delay of data calls are evaluated. The results are compared with another handoff scheme for integrated voice/data cellular mobile systems where some numbers of channels are reserved for voice handoff calls. It is shown that, when the data traffic is not very light, the new scheme can provide lower blocking probability for originating voice calls, lower forced termination probability for ongoing voice calls, and shorter average queue length and less average transmission delay for data calls.

We propose a hysteresis neural network system solving NP-Hard optimization problems, the N-Queens Problem. The continuous system with binary outputs searches a solution of the problem without energy function. The output vector corresponds to a complete solution when the output vector becomes stable. That is, this system does never become stable without satisfying the constraints of the problem. Though it is very hard to remove limit cycle completely from this system, we can propose a new method to reduce the possibility of limit cycle by controlling time constants.

In literature, many methods have been presented for enumerating binary trees (full binary trees) and regular k-ary trees, while no one for enumerating arbitrary trees or arbitrary k-ary trees. It is proposed in 1997 using a context-free grammar GBT (GFBT) to code binary trees (full binary trees) for enumerating them. In this paper, we use another grammar GT (GTk) to code arbitrary trees (arbitrary k-ary trees) for enumerating them. The properties of words of Ln(GT) (Ln(GTk)) are discussed in depth, including necessary and sufficient conditions for a word, prefix and suffix of Ln(GT) (Ln(GTk)), and efficient algorithms are given and analyzed for the enumeration of words of Ln(GT) (Ln(GTk)).

This paper presents the several bifurcation phenomena generated in nonlinear three-phase circuit with symmetry. The circuit consists of delta-connected nonlinear inductors, capacitors and three-phase symmetrical voltage sources. Particular attention is paid to the subharmonic oscillations of order 1/2. We analyze the bifurcations of the oscillations from both theoretical and experimental points. As a tool of analysis, we use the homotopy method. Additionally, by comparing with single-phase and single-phase-like circuits, the special feature of the three-phase circuit is revealed.

We report relations between invariant manifolds of saddle orbits (Lyapunov family) around a saddle-center equilibrium point and lowest periodic orbits on the two degree of freedom swing equation system. The system consists of two generators operating onto an infinite bus. In this system, a stable equilibrium point represents the normal operation state, and to understand its basin structure is important in connection with practical situations. The Lyapunov families appear under conservative conditions and their invariant manifolds constitute separatrices between trapped and divergent motions. These separatrices continuously deform and become basin boundaries, if changing the system to dissipative one, so that to investigate those manifolds is meaningful. While, in the field of two degree of freedom motions, systems with saddle loops to a saddle-center are well studied, and existence of transverse homoclinic structure of separatrix manifolds is reported. However our investigating system has no such loops. It is interesting what separatrix structure exists without trivial saddle loops. In this report, we focus on above invariant manifolds and lowest periodic orbits which are foliated for the Hamiltonian level.

A compact residue arithmetic multiplier based on the radix-4 signed-digit arithmetic is presented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, two radix-4 signed-digit (SD) number representations, {-2,-1,0,1,2} and {-3,-2,-1,0,1,2,3}, are introduced. The former is used for the input and output, and the later for the inner arithmetic circuit of the presented multiplier. Integers 4p and 4p 1 are used as moduli of residue number system (RNS), where p is a positive integer and both circuits for partial product generation and sum of the partial products can be efficiently constructed by using the multiple-valued current-mode circuits. The modulo m addition, m=4p or m=4p 1, can be performed by an SD adder or an end-around-carry SD adder with the multiple-valued circuits and the addition time is independent of the word length of operands. The modulo m multiplier can be compactly constructed using a binary tree of the multiple-valued modulo m SD adders, and consequently the modulo m multiplication is performed in O(log p) time. The number of MOS transistors required in the presented residue arithmetic multiplier is about 86p2 + 66p.

A resonant-tunneling-diode (RTD) based sense amplifier circuit design has been proposed for the first time to envision a very high-speed and low-power memory system that also includes refresh-free, compact RTD-based memory cells. By combining RTDs with n-type transistors of conventional complementary metal oxide semiconductor (CMOS) devices, a new quantum MOS (Q-MOS) family of logic circuits, having very low power-delay product and good noise immunity, has recently been developed. This paper introduces the design and analysis of a new QMOS sense amplifier circuit, consisting of a pair of RTDs as pull-up loads in conjunction with n-type pull-down transistors. The proposed QMOS sensing circuit exhibits nearly 20% faster sensing time in comparison to the conventional design of a CMOS sense amplifier. The stability analysis done using phase-plot diagram reveals that the pair of back-to-back connected static QMOS inverters, which forms the core of the sense amplifier, has meta-stable and unstable states which are closely related to the I-V characteristics of the RTDs. The paper also analyzes in details the refresh-free memory cell design, known as tunneling static random access memory (TSRAM). The innovative cell design adds a stack of two RTDs to the conventional one-transistor dynamic RAM (DRAM) cell and thereby the cell can indefinitely hold its charge level without any further periodic refreshing. The analysis indicates that the TSRAM cell can achieve about two orders of magnitude lower stand-by power than a conventional DRAM cell. The paper demonstrates that RTD-based circuits hold high promises and are likely to be the key candidates for the future high-density, high-performance and low-power memory systems.

Using Hopfield-type neural network model, we present an algorithm for reconstructing 3D mesh processor arrays using single-track switches where spare processors are laid on the six surfaces of a 3D array and show its effectiveness in terms of reconstruction rate and computing time by computer simulation. Next, we show how the algorithm can be realized by a digital neural circuit. It consists of subcircuits for finding candidate compensation paths, deciding whether the neural system reaches a stable state and at the time the system energy is minimum, and subcircuits for neurons. The subcircuit for each neuron including the other subcircuits can only be made with 16 gates and two flip-flops. Since the state transitions are done in parallel, the circuit will be able to find a set of compensation paths for a fault pattern very quickly within a time less than 1 µs. Furthermore, the hardware implementation of the algorithm leads to making a self-reconfigurable system without the aid of a host computer.

A new logic-in-memory VLSI architecture based on multiple-valued floating-gate-MOS pass-transistor logic is proposed to solve the communication bottleneck between memory and logic modules. Multiple-valued stored data are represented by the threshold voltage of a floating-gate MOS transistor, so that a single floating-gate MOS transistor is effectively employed to merge multiple-valued threshold-literal and pass-switch functions. As an application, a four-valued logic-in-memory VLSI for high-speed pattern recognition is also presented. The proposed VLSI detects a stored reference word with the minimum Manhattan distance between a 16-bit input word and 16-bit stored reference words. The effective chip area, the switching delay and the power dissipation of a new four-valued full adder, which is a key component of the proposed logic-in-memory VLSI, are reduced to about 33 percent, 67 percent and 24 percent, respectively, in comparison with those of the corresponding binary CMOS implementation under a 0.5-µm flash EEPROM technology.

A novel combinatorial optimization algorithm called 2-stage discrete optimization method (2DOM) is proposed for the largest common subgraph problem (LCSP) in this paper. Given two graphs G=(V1, E1) and H=(V2, E2), the goal of LCSP is to find a subgraph G'=(V1', E1') of G and a subgraph H'=(V2', E2') of H such that G' and H' are not only isomorphic to each other but also their number of edges is maximized. The two graphs G' and H' are isomorphic when |V1'|=|V2'| and |E1'|=|E2'|, and there exists one-to-one vertex correspondence f: V1' V2' such that {u, v} E1' if and only if{f(u), f(v)} E2'. LCSP is known to be NP-complete in general. The 2DOM consists of a construction stage and a refinement stage to achieve the high solution quality and the short computation time for large size difficult combinatorial optimization problems. The construction stage creates a feasible initial solution with considerable quality, based on a greedy heuristic method. The refinement stage improves it keeping the feasibility, based on a random discrete descent method. The performance is evaluated by solving two types of randomly generated 1200 LCSP instances with a maximum of 500 vertices for G and 1000 vertices for H. The simulation result shows the superiority of 2DOM to the simulated annealing in terms of the solution quality and the computation time.

We have developed an InP-based monolithic optical frequency discriminator consisting of a temperature-insensitive optical filter and dual photodiodes. This integrated device detects the optical frequency deviation of the input light as differential photocurrent from the dual photodiodes, and the photocurrent is fedback to the light source for frequency stabilization through a differential amplifier. The FSR and extinction ratio of the filter are 50 GHz and 20 dB. The total opto-electronic conversion efficiency is 40%. In a frequency stabilization experiment using the developed discriminator, the frequency fluctuation of a DFB laser was reduced to less than 10 MHz.

We successfully fabricated plastic ferrules and split alignment sleeves for single-mode fiber-optic connectors by the injection molding process. Liquid crystalline polymer (LCP) was used as the molding material for the ferrule. We introduced an eccentricity control mechanism into the ferrule mold and realized an eccentricity of less than 1 µm. As the molding material for the sleeve, thermosetting epoxy resin was used. Suitable mechanical properties were realized by employing appropriate dimensional design and the molding process. The optical characteristics of a system combining these plastic components are compatible with single-mode SC-type connectors and are also stable under hot and humid conditions.

This paper presents a new technique for the synthesis of sets of low-peak sequences exhibiting low peak cross correlation. The sequences also have flat power spectra and are suitable for many applications requiring such sets of uncorrelated pseudo-white-noise sources. This is a new application of the ta-sequence (trigonometric function aliasing sequence), which itself is a very new technique that uses the well-known "Reed-Solomon code" or "One coincident code" to generate these sets of low-peak-factor pseudo-white-noise exhibiting low peak cross correlation. The ta sequence method presented here provides the means for generating various sequences at the lengths required for such applications as system measurement (needing uncorrelated test signals), pseudo-noise synthesis (for spread spectrum communication), and audio signal processing for sound production (for enhancing spatial imagery in stereo signals synthesized from mono sources) and sound reproduction (for controlling unwanted interference effects in multiple-loudspeaker arrays).

We have developed an InP-based monolithic optical frequency discriminator consisting of a temperature-insensitive optical filter and dual photodiodes. This integrated device detects the optical frequency deviation of the input light as differential photocurrent from the dual photodiodes, and the photocurrent is fedback to the light source for frequency stabilization through a differential amplifier. The FSR and extinction ratio of the filter are 50 GHz and 20 dB. The total opto-electronic conversion efficiency is 40%. In a frequency stabilization experiment using the developed discriminator, the frequency fluctuation of a DFB laser was reduced to less than 10 MHz.

Recently, Kundur and Hatzinakos showed that a linear restoration filter designed by using the almost obvious a priori knowledge on the original image, such as (i) nonnegativity of the true image and (ii) the smallest rectangle encompassing the original object, can realize a remarkable performance for a blind image deconvolution problem. In this paper, we propose a new set-theoretic blind image deconvolution scheme based on a recently developed convex projection technique called Hybrid Steepest Descent Method (HSDM), where some partial information can be utilized set-theoretically by parallel projections onto convex sets while the others are incorporated in a cost function to be minimized by a steepest descent method. Numerical comparisons with the standard set-theoretic scheme based on POCS illustrate the effectiveness of the proposed scheme.

This paper describes a spatial spectral subtraction method by using the complementary beamforming microphone array to enhance noisy speech signals for speech recognition. The complementary beamforming is based on two types of beamformers designed to obtain complementary directivity patterns with respect to each other. In this paper, it is shown that the nonlinear subtraction processing with complementary beamforming can result in a kind of the spectral subtraction without the need for speech pause detection. In addition, the optimization algorithm for the directivity pattern is also described. To evaluate the effectiveness, speech enhancement experiments and speech recognition experiments are performed based on computer simulations under both stationary and nonstationary noise conditions. In comparison with the optimized conventional delay-and-sum (DS) array, it is shown that: (1) the proposed array improves the signal-to-noise ratio (SNR) of degraded speech by about 2 dB and performs more than 20% better in word recognition rates under the conditions that the white Gaussian noise with the input SNR of -5 or -10 dB is used, (2) the proposed array performs more than 5% better in word recognition rates under the nonstationary noise conditions. Also, it is shown that these improvements of the proposed array are same as or superior to those of the conventional spectral subtraction method cascaded with the DS array.

This paper presents a new general distance measure that not only can be used in a vector quantization (VQ) of line spectrum frequency (LSF) parameters but also performs well in a LSF transformed domain. The new distance is based on the spectral sensitivity of LSFs and their transformed coefficients. In addition, a fix scaling vector is used to decrease the sensitivity of spectral error at higher frequencies. Experimental results have shown that the proposed distance measure leads to as good as or better performance of VQ compared to other methods in the field of LSF coding. The use of this distance as the weighting function of the LSF transformed parameters is also suggested.