This paper proposes a high-speed input and output buffering ATM switch, named Tandem-Crosspoint (TDXP) switch. The TDXP switch consists of multiple crossbar switch planes. These switch planes are connected in tandem at every crosspoint. Even if a cell can not be transmitted to an output port on the first plane, it has a chance to be transmitted on the next plane. Cell transmission is executed on each switch plane in a pipeline manner. Therefore, more than one cell can be transmitted to the same output port within one cell time slot, although the internal line speed of each switch is equal to the input /output line speed. The TDXP switch architecture has several advantages in implementation. First, the TDXP switch does not increase the internal line speed in eliminating Head-Of-Line (HOL) blocking. Second, since the TDXP switch employs a simple cell reading algorithm at the input buffer in order to retain the cell sequence, the TDXP switch does not require to rebuild the cell sequences at output buffers using time stamps, as is required by a parallel switch. These merits make implementing the high-speed ATM switch easy. Numerical results show that the TDXP switch can eliminate the HOL blocking effectively and achieve high throughput both for unicasting and multicasting traffic. This switch architecture is expected to enable the development of high-speed ATM switching systems that can realize over 1 Tb/s throughput in a cost-effective way.

A technique for realization of low-voltage OTAs is presented in this letter. A very low-voltage differential-output OTA is realized by employing a new common-mode amplifier in the common-mode feedback circuit. The results of PSpice simulations are shown. The proposed OTA can operate at a 0. 9 V supply voltage.

While active researches have been continuously made on the ATM switch architectures and the QoS service guarantees, most of them have been treated independently in the past. In this paper, we first explain the architectural requirement on the ATM switches to implement the mechanism of QoS guarantees in the context of ATM congestion control. Then we discuss how a vital link between two should be built, and remaining problems are pointed out.

In this papers, we will discuss the different percentages of embedding certain subsystems successfully into a n-cube according to the fault model used. We will discuss two fault models: the first one assumes that, in a faulty node, the computational function of the node is lost while the communication function of the faulty node remains intact, and, in the second, the communication function is also lost. In this paper, 2 types of fault tolerable subsystem embedding schemes will be introduced. The first one embeds a complete binary tree into a n-cube with faulty nodes, and the second embeds two (n-1)-subcubes whose total number of faulty nodes is less than half the number of nodes. These schemes are divided into 4 types based on the above two models. First, we will discuss how different the successful percentages of embedding are for 2 of the different types of embedded binary trees that are based on the above two models. Then, we will analyze the possibility that the component nodes of an embedded binary tree can communicate via the faulty nodes that are located in the embedded binary tree. In the embedding process, each faulty node was replaced with a nonfaulty node that was located on another (n-1)-subcube and at a Hamming distance of 1 from the faulty node. The number of faults that led to the successful percentage of embedding will be presented as an upper bound. Next, we will discuss how different the successful embedding percentages are for the 2 types of irregular (n-1)-subcubes based on the two models; that is, if 2n-2+1 or more of the nonfaulty nodes in both of the (n-1)-subcubes can communicate or not via faulty nodes. Here also, the number of faults that led to a successful embedding percentage will be presented as a critical value.

In this paper, we propose an extension of finite state tree automaton, called tree automaton with tree memory (TTA), and also define structure composing TTA (SC-TTA) and backward deterministic TTA (BD-TTA) as subclasses of TTA. We show that the classes of yield languages accepted by TTAs, SC-TTAs and BD-TTAs are equal to the class of recursively enumerable languages, the class of languages generated by tree-to-string finite state translation systems (TSFSTSs) and the class of languages generated by deterministic TSFSTSs, respectively. As a corollary, it is shown that the yield language accepted by an SC-TTA (resp. a BD-TTA) is linear space (resp. polynomial time) recognizable.

In this paper we newly define a generalized edge-ranking of a graph G as follows: for a positive integer c, a c-edge-ranking of G is a labeling (ranking) of the edges of G with integers such that, for any label i, deletion of all edges with labels >i leaves connected components, each having at most c edges with label i. The problem of finding an optimal c-edge-ranking of G, that is, a c-edge-ranking using the minimum number of ranks, has applications in scheduling the manufacture of complex multi-part products; it is equivalent to finding a c-edge-separator tree of G having the minimum height. We present an algorithm to find an optimal c-edge-ranking of a given tree T for any positive integer c in time O(n2log Δ), where n is the number of vertices in T and Δ is the maximum vertex-degree of T. Our algorithm is faster than the best algorithm known for the case c=1.

Considering the pattern classification/recognition tasks, the influence of the activation function on fault tolerance property of feedforward neural networks is empirically investigated. The simulation results show that the activation function largely influences the fault tolerance and the generalization property of neural networks. It is found that, neural networks with symmetric sigmoid activation function are largely fault tolerant than the networks with asymmetric sigmoid function. However the close relation between the fault tolerance and the generalization property was not observed and the networks with asymmetric activation function slightly generalize better than the networks with the symmetric activation function. First, the influence of the activation function on fault tolerance property of neural networks is investigated on the XOR problem, then the results are generalized by evaluating the fault tolerance property of different NNs implementing different benchmark problems.

In this paper, a dynamic constructive algorithm for fault tolerant feedforward neural network, called DCFTA, is proposed. The algorithm starts with a network with single hidden neuron, and a new hidden unit is added dynamically to the network whenever it fails to converge. Before inserting the new hidden neuron into the network, only the weights connecting the new hidden neuron to the other neurons are trained (i. e. , updated) until there is no significant reduction of the output error. To generate a fault tolerant network, the relevance of each synaptic weight is estimated in each cycle, and only the weights which have their relevance less than a specified threshold are updated in that cycle. The loss of a connections between neurons (which are equivalent to stuck-at-0 faults) are assumed. The simulation results indicate that the network constructed by DCFTA has a significant fault tolerance ability.

A new broadband space diversity (B-SD) combining method, which is a key technique in the growth of digital microwave radio system, is proposed. In this B-SD combining method, two received signals, whose bandwidths are 280 MHz, are combined. To develop this combining method, an optimum control algorithm is developed that monitors power levels of all primary carriers and controls the endless phase shifter so that the higher level signal is decreased and the lower level signal is increased. This paper describes the proposed B-SD combining method which effectively operates over a wide bandwidth. Performance evaluations based on simulations and theoretical estimations are given. It is proven that this combining method offers the same performance obtained by the conventional narrowband SD combining method and can be applied to over 50% cases of the propagation paths observed in Japan. The suitability of the proposed combining method and the calculation methods adopted is demonstrated experimentally.

This paper proposes practical escrow cash schemes with particular emphasis on countermeasures against social crimes such as money laundering and extortion. The proposed cash schemes restrict "unconditional" privacy in order to prevent these social crimes while preserving off-line-ness, divisibility and transferability, properties listed in [25] as criteria for ideal cash schemes.

This paper describes the design and architecture for a newly developed microprocessor suitable for consumer applications, which we call SuperH. To achieve both low-power and high-speed, the SuperH architecture includes 16-bit fixed length instruction code and several power saving features. The 16-bit fixed length instruction code makes the SuperH possible to achieve excellent code efficiency for the SPECint benchmarks when compared with conventional microcontrollers and RISC's for workstations and PC's. As a result, the SuperH provides almost the same code efficiency as that of 8-bit microcontrollers, and also achieves similar performance as that of RISC's with 32-bit fixed length instruction code. The SuperH also incorporates several power reduction techniques through the control of clock frequency and clock distribution. Thus, the 16-bit code format, power saving features, and other architectural innovations make the SuperH particularly proficient for portable multi-media applications.

This paper describes the 10-bit 50 MS/s pipelined CMOS A/D Converter using a "reference feed-forward architecture." In this architecture, reference voltage generated in a reference generator block and residual voltage from a DA/subtractor block are fed to the next stage. The reference generator block and DA/subtractor block are constructed using resistive-load, low-gain differential amplifiers. The high-gain, high-speed amplifiers consuming much power are not used. Therefore, the power consumption of this ADC is reduced. The gain matching of the reference voltage with the internal signal range is achieved through the introduction of the reference generator block having the same characteristics as a DA/subtractor block. Each offset voltage of the differential amplifier in the reference generator block and the DA/subtractor block is canceled by the offset cancellation technique, individually. In addition, the front-end sample/hold circuit is eliminated to reduce power consumption. Because of the introduction of high-speed comparators based on the source follower and latch circuit into the first stage A/D subconverter, analog bandwidth is not degraded. This ADC has been fabricated in double-polysilicon, double-metal, 0.5µm CMOS technology, and it operates at 50 MS/s with a 300-mW (Vdd=3.0 V) power consumption. The differential linearity error of less than +/-1 LSB is obtained.

We present a method for learning classification functions from pre-classified training examples and hypotheses written roughly by experts. The goal is to produce a classification function that has higher accuracy than either the expert's hypotheses or the classification function inductively learned from the training examples alone. The key idea in our proposed approach is to let the expert's hypotheses influence the process of learning inductively from the training examples. Experimental results are presented demonstrating the power of our approach in a variety of domains.

We have developed an efficient recursive algorithm based on the interacting multiple model (IMM) for enhancing speech degraded by additive white noise. The clean speech is modeled by the hidden filter model (HFM). The simulation results shows that the proposed method offers performance gains relative to the previous one with slightly increased complexity.

From the standpoint of reducing the electromagnetic (EM) absorption in the human head for portable telephones, a ferrite sheet is proposed to use as a protection attachment between the antenna and the head. By using an anatomically based head model and a realistic portable telephone model, the effects of the ferrite sheet on both the reduction of EM absorption and antenna radiation pattern are numerically analyzed by the finite-difference time-domain (FDTD) method. The results show that a ferrite sheet can result in a reduction over 13% for the spatial peak SAR averaged over one gram of tissue relative to a degradation below 0.6 dB for the antenna radiation pattern.

A 100MIPS high speed and low power fixed point Digital Signal Processor (DSP) has been developed applying 0.45µm CMOS TLM technology. The DSP contains a 16-bit32K full CMOS static RAM with a hierarchical low power architecture. The device is a RAM based DSP with a total of 4.2 million transistors and a new low power design and process which enabled an approximate 50% reduction in power as compared to conventional DSPs at 40 MHz. In order to cover very wide application requirements, this DSP is capable of operating at 1.0 V for DSP core and 3.3 V for I/O. This was achieved by new level shifter circuitry to interface with cost effective 3 V external commodity products and confirmed 80% of power reduction at Core VDD=2.0 V, I/O VDD=3.3 V at 40MHz. This paper describes the new features of the high speed and low power DSP.

This paper surveys low-power design techniques for Si bipolar Gbit/s LSIs. First, a total strategy for power reduction in bipolar LSIs is described. The power dissipation of Si bipolar LSIs can be minimized by reducing the supply voltage, switching and driving currents, the power of input and output circuits, and the equivalent "on" ratio. Widely spread activities from device to architecture levels are indispensable and each of the low-power techniques reduces power by a factor of about 0.5 to 0.7. The integration of these techniques is very important, and as a certain example of their effectiveness, an SOH signal processing LSI is demonstrated with a reduction factor of 1/10. Comparisons with other device technologies for low power characteristics reveal the low-power potential of bipolar LSIs in the Gbit/s region.

This paper proposes a new speech codec based on CELP for PHS multimedia communication. PHS portable terminals should consume as little power as possible, and the codec used in them has to be robust against channel errors. Therefore, the proposed codec operates with low computational complexity while reducing the deterioration in speech quality due to channel errors. This codec uses two new schemes to reduce computational complexity. One is moving average scalar quantization for the filter coefficients of the synthesis filter. This scheme requires 90% less complexity to quantize synthesis filter coefficients compared to the widely used vector quantization. The other is pre-selection for selecting an algebraic codebook used as random excitation source. An orthogonalization scheme is used for stable pre-selection. Deterioration of speech quality is suppressed by using CRC and parameter estimation for error protection. Two types of codec are proposed: a 10-ms frame type that transmits 160 bits every 10-ms and a 15-ms frame type that transmits 160 bits every 15 ms. The computational complexity of these codecs is less than 5 MOPS. In a nochannel error environment, the speech quality is equal to that of ITU-TG.726 at 32.0 kbit/s. With 0.3% channel error, both codecs offer more comfortable conversation than G.726. Moreover, at 1.0% channel error, the 10-ms frame type still provides comfortable conversation.

This paper describes a vision system with dual viewing angles, i. e., wide and narrow viewing angles, and a scheme of user-friendly speech dialogue environment based on the vision system. The wide viewing angle provides a wide viewing field for wide range motion tracking, and the narrow viewing angle is capable of following a target in wide viewing field to take the image of the target with sufficient resolution. For a fast and robust motion tracking, modified motion energy (MME) and existence energy (EE) are defined to detect the motion of the target and extract the motion region at the same time. Instead of using a physical device such as a foot switch commonly used in speech dialogue systems, the begin/end of an utterance is detected from the movement of user's mouth in our system. Without recognizing the movement of lips directly, the shape variation of the region between lips is tracked for more stable recognition of the span of a dialogue. The tracking speed is about 10 frames/sec when no recognition is performed and about 5 frames/sec when both tracking and recognition are performed without using any special hardware.

Bit-interleaving can enhance performance of a trellis coded modulation system over a fading channel. A combined system with decision feedback equalization is proposed. In the system, TCM decoded symbols are fed back for equalization. To avoid a bad effect of decoding delay, a deinterleaver is utilized effectively. Information sequence is divided into three subsequences and encoded by three encoders. Among the 3 code vectors from the encoders, bits are interleaved and decoding proceeds in parallel. Simulation results show that the proposed system realizes 0.6 dB more coding gain than a symbol interleaved system. A calculation method of a branch metric for decoding is proposed. Performance with the branch metric is shown to be nearly independent from the desired/undesired power ratio of a intersymbol interference channel. An approximate upper bound is analyzed for the proposed system, and the optimum code is searched.