This paper presents a new fuzzy dynamic output feedback controller design technique for the Takagi Sugeno (T-S) fuzzy model with unknown-but-bounded time-varying modeling error. It is shown that the quadratic stabilization problem of the T-S fuzzy modeled system can be converted into an H control problem of the scaled polytopic Linear Parameter Varying (LPV) system. Then, a controller satisfying a prescribed H performance is designed for the stabilization of the T-S fuzzy modeled system.

In this paper, we present a new approach which is spanning tree-based genetic algorithm for solving a multi-objective transportation problem. The transportation problem as a special type of the network optimization problems has the special data structure in solution characterized as a transportation graph. In encoding transportation problem, we introduce one of node encodings based on a spanning tree which is adopted as it is capable of equally and uniquely representing all possible basic solutions. The crossover and mutation were designed based on this encoding. Also we designed the criterion that chromosome has always feasibility converted to a transportation tree. In the evolutionary process, the mixed strategy with (µ+λ)-selection and roulette wheel selection is used. Numerical experiments show the effectiveness and efficiency of the proposed algorithm.

In this paper, the Linear Exponential Quadratic Gaussian with Loop Transfer Recovery (LEQG/LTR) methodology is employed for the design of high performance induction motor servo systems. In addition, we design a speed sensorless induction motor vector controlled driver with both the extended Kalman filter and the LEQG/LTR algorithm. The experimental realization of an induction servo system is given. Compared with the traditional PI and LQG/LTR methods, it can be seen that the system output sensitivity for parameter variations and the rising time for larger command input of the proposed method can be significantly reduced.

Three basic ideas for enhancing the performance of extended EPRML (EEPRML) are described in detail. The first is the modification of the EEPRML impulse response in order to minimize the bit error rate of read signals from magnetic recording channels. This modification can improve the signal to noise ratio (S/N) of conventional extended partial response maximum likelihood (EPRML) by approximately 1 dB. The second is the introduction of 16/17 (3;11) maximum transition run code (MTR). This code can completely eliminate error events of more than four consecutive bits from modified EEPRML error events, and reduce the probability of minimum distance error events occurring by one eighth. Finally, dominant error events such as {0e0}, {0ee0}, {0eee0}, and {0e00e0} before 16/17 (3,11) MTR decoding can be corrected by employing cyclic redundancy check code (CRCC) with soft decision decoding. The symbol "e" represents one bit error, namely, "1" to "0" or vice versa and "0" represents a correct bit. Total performance has been evaluated by computer simulations using an isolated waveform similar to actual read signals and additive white Gaussian noise. Consequently, it has been confirmed that modified EEPRML with 16/17 (3;11) MTR code and CRCC can improve the S/N of conventional EPRML by approximately 4 dB at a bit error rate of 10-6.

Generating conditions of the optical feedback noise in self-pulsing lasers were experimentally examined. The noise charcteristics were determined by changing the operating power, the feedback distance and the feedback ratio for several types of self-pulsing lasers. The idea of the effective modulation index was introduced to evaluate the generating conditions in an uniform manner based on the mode competition theory. Validity of the idea was experimentally confirmed for generation of noise.

This paper focuses on flow control in high-speed and large-scale networks. Each node in the network handles its local traffic flow only on the basis of the information it knows. It is preferable, however, that the decision making of each node leads to high performance of the whole network. To this end, the relationship between local decision making and global performance of flow control is the essential object. We propose phenomenological models of flow control of high-speed and large-scale networks, and investigate the stability of these models.

High speed home networks may lead high speed non-public networks (consumer communication networks) in this ten years. We find many high speed audio and visual machines in the home which should be connected each other and to personal computers by a home network. On the other hand, people's work is rapidly changing to work including teleworking. Home is becomming a part of office which needs a high speed network to access to the Internet, broadcasting, home database and so on. IEEE 1394 is a standard for high speed wired network in the home and should be extended to a wireless standard. Wireless 1394 discussed recently is shown in this paper.

We propose a model for fault tolerant 3D processor arrays using one-and-half track switches. Spare processors are laid on the two opposite surfaces of the 3D array. The fault compensation process is performed by shifting processors on a continuous straight line (called compensation path) from a faulty processor to a spare on the surfaces. It is not allowed that compensantion paths are in the near-miss relation each other. Then, switches with only 4 states are needed to preserve the 3D mesh topology after compensating for faults. We give an algorithm in a convenient form for reconfiguring by hardware the 3D mesh arrays with faults. The algorithm can reconfigure the 3D mesh arrays in polynomial time. By computer simulation, we show the survival rates and the reliabilities of arrays which express the efficiencies of reconfiguration according to the algorithm. The reliabilities are compared with those of the model using double tracks for which the near-miss relation among compensation paths is allowed, but whose hardware overhead is almost double of that of the proposed model using one-and-half track. Finally, we design a logical circuit for hardware realization of the algorithm. Using the circuit, we can construct such a built-in self-reconfigurable 3D mesh array that the reconfiguration is done very quickly without an aid of a host computer.

It is known that the clock-period can be shorter than the maximum of signal-delays between registers if the clock arrival time to each register is properly scheduled. The algorithm to design an optimal clock-schedule was given. In this paper, we propose a clock-tree routing algorithm that realizes a given clock-schedule using the Elmore-delay model. Following the deferred-merge-embedding (DME) framework, the algorithm generates a topology of the clock-tree and simultaneously determines the locations and sizes of intermediate buffers. The experimental results showed that this method constructs a clock-tree with moderate wire length for a random layout of scheduled registers. Notably, the required wire length for a gentle layout of scheduled registers was shown to be almost equal to that of zero-skew clock-trees.

In this paper, we introduce a high-speed and low-power Phase-Frequency Detector (PFD) that is designed using a modified TSPC (True Single-Phase Clock) positive edge triggered D flip-flop . The proposed PFD has a simple structure with using only 19 transistors. The operation range of this PFD is over 1.4 GHz without using additional prescaler circuits. Furthermore, the PFD has a dead zone less than 0.01ns in the phase characteristics and has low phase sensitivity errors. The phase and frequency error detection range is not limited as in the case of the pt-type and nc-type PFDs. Also, the PFD is independent of the duty cycle of input signals. Also, a new charge-pump circuit is presented that is based on a charge-amplifier. A stand-by current of the proposed charge-pump circuit enhances the speed of charge-pump and removes the charge sharing which causes a phase noise in the charge pump PLL. Furthermore, the effect of clock feedthrough is reduced by separating the output stage from up and down signal. The simulation results base on a third order PLL are presented to verify the lock in process with the proposed PFD and charge pump circuits. The proposed PFD and charge-pump circuits are designed using 0.8 µm CMOS technology with 5 V supply voltage.

In this study, wave propagation phenomena of phase states are observed at van der Pol oscillators coupled by inductors as a ladder. For the case of 17 oscillators, interesting wave propagation phenomena of phase states are found. By using the relationship between phase states and oscillation frequencies, the mechanisms of the propagation and the reflection of wave are explained. Circuit experimental results agree well with computer calculated results qualitatively.

A new data-I/O scheme with a hidden writing-recovery architecture has been developed for the megabit-class high operating frequency SRAMs. Read-out nodes in the memory cell are separated from bitline-connected writing nodes so as not to delay sensing initiation due to uncompleted bitline recovery. The data stored in a memory cell are read-out by sensing the differential current signal on a double-rail virtual-GND line along bitlines. Each pair of virtual-GND lines is imaginarily short-circuited by a sense amplifier, so that the read-out circuitry would have large immunity against virtual-GND-line noises. The critical noise level associated with data destruction is analyzed at various supply voltages. The virtual-GND-line-sensed memory cell with the squashed topology, the swing-suppression-type low-power writing circuitry, and the current-sense amplifier with extra negative feedback loops, --which are used in the data-I/O scheme are also mentioned. Assuming a sub array in megabit-class SRAMs, 4 K-words 6 -bits test chip was fabricated with a 0.5-µm CMOS process. The SRAM achieved 180-MHz operation at a typical 3.3-V, 25 condition. The power dissipation at the practical operating frequency of 133-MHz was 50-mW.

In several design methods for Pass-transistor Logic (PTL) circuits, Boolean functions are expressed as OBDDs in decomposed form and then the component OBDDs are directly mapped to PTL cells. The total size of OBDDs (number of nodes) corresponds to the circuit size. In this paper, we investigate a method for PTL synthesis based on exact minimization of Free BDDs (FBDDs). FBDDs are well-studied extension of OBDDs with free variable ordering on each path. We present statistics showing that more than 56% of 616126 NPN-equivalence classes of 5-variable Boolean functions have minimum FBDDs with less size than their OBDDs. This result can be used for PTL synthesis as libraries. We also applied the exact minimization algorithm of FBDDs to the minimization of subcircuits in the synthesis for MCNC benchmarks and found up to 5% size reduction.

This paper proposes an implementation of the Telecommunications Information Networking Architecture (TINA) connection management system, based on our involvement of The TINA Trial (TTT). The system is used for managing ATM networks, which consist of network elements with SNMP interfaces. It provides setup, configuration, and release of ATM connection with a GUI-based network design tool that generates network resource data used for deploying TINA software components. This paper reports on a method of implementing TINA components over a Distributed Processing Environment (DPE) and an effective way to manage computational objects with multiple interfaces by using the Trading Service.

A description for high-speed communication networks for the 21st century is roughly sketched, and the technical development trends in high-frequency and high-speed devices are briefly forecasted. Four examples of devices under development are reported: 76-GHz flip-chip MMIC's for car-radar systems, a cost-effective RF module for millimeter-wave wireless systems, a 10-Gbps demultiplexer for optical fiber communication systems, and a GaAs microwave signal processor for active phased-array systems. Considering as technological trends evolve further, this paper also introduces the software radio concept and the fusion of wireless and optical technologies for cost-effective wireless communication equipment and end-user services.

A procedure for quickly developing highly integrated multifunctional MMICs by using the three-dimensional masterslice MMIC technology has been developed. The structures and advanced features of this technology, such as miniature transmission lines, a broadside coupler, and miniature function block circuits, enable multifunctional MMICs to be quickly and easily developed. These unique features and basic concept of the masterslice technology are discussed and reviewed to examine the advantages of this technology. As an example of quick MMIC development, an amplifier, a mixer, and a down-converter are fabricated on a newly designed master array.

In this paper, the use of optimal Karhunen-Loeve (KL) transform for quantization of speech line spectrum frequency (LSF) coefficients is studied. Both scalar quantizer (SQ) and vector quantizer (VQ) schemes are developed to encode efficiently the transform parameters after operating one or two-dimensional KL transform. Furthermore, the SQ schemes are also combined with entropy coding by using Huffman variable length coding (VLC). The basic idea in developing these schemes is utilizing the strong correlation of LSF parameters to reduce the bit rate for a given level of fidelity. Since the use of global statistics for generating the coding scheme may not be appropriate, we propose several adaptive KL transform systems (AKL) to encode the LSF parameters. The performance of all systems for different bit rates is investigated and adequate comparisons are made. It is shown that the proposed KL transform coding systems introduce as good as or better performance for both SQ and VQ in the examined bit rates compared to other methods in the field of LSF coding.

In pattern recognition using neural networks, it is very difficult for researchers or users to design optimal neural network architecture for a specific task. It is possible for any kinds of neural network architectures to obtain a certain measure of recognition ratio. It is, however, difficult to get an optimal neural network architecture for a specific task analytically in the recognition ratio and effectiveness of training. In this paper, an evolutional method of training and designing feedforward neural networks is proposed. In the proposed method, a neural network is defined as one individual and neural networks whose architectures are same as one species. These networks are evaluated by normalized M. S. E. (Mean Square Error) which presents a performance of a network for training patterns. Then, their architectures evolve according to an evolution rule proposed here. Architectures of neural networks, in other words, species, are evaluated by another measurement of criteria compared with the criteria of individuals. The criteria assess the most superior individual in the species and the speed of evolution of the species. The species are increased or decreased in population size according to the criteria. The evolution rule generates a little bit different architectures of neural network from superior species. The proposed method, therefore, can generate variety of architectures of neural networks. The designing and training neural networks which performs simple 3 3 and 4 4 pixels which include vertical, horizontal and oblique lines classifications and Handwritten KATAKANA recognitions are presented. The efficiency of proposed method is also discussed.

For the correctness of the minimum cut algorithm proposed in [H. Nagamochi and T. Ibaraki, Computing edge-connectivity of multigraphs and capacitated graphs, SIAM J. Discrete Mathematics, 5, 1992, pp. 54-66], several simple proofs have been presented so far. This paper gives yet another simple proof. As a byproduct, it can provide an O(m log n) time algorithm that outputs a maximum flow between the pair of vertices s and t selected by the algorithm, where n and m are the numbers of vertices and edges, respectively. This algorithm can be used to speed up the algorithm to compute DAGs,t that represents all minimum cuts separating vertices s and t in a graph G, and the algorithm to compute the cactus Γ(G) that represents all minimum cuts in G.

We study some sufficient conditions of codeword lengths for the existence of a fix-free code. Ahlswede et al. proposed the 3/4 conjecture that Σi=1n a-li 3/4 implies the existence of a fix-free code with lengths li when a=2 i. e. the alphabet is binary. We propose a more general conjecture, and prove that the upper bound of our conjecture is not greater than 3/4 for any finite alphabet. Moreover, we show that for any a2 our conjecture is true if codeword lengths l1,l2,. . . consist of only two kinds of lengths.