In this paper an ATM call level model, where service classes with QoS guarantees (CBR/VBR) as well as elastic (best effort) services (ABR/UBR) coexist, is proposed and a number of simulations have been carried out on three different network topologies. Elastic traffic gives on the network level rise to new challenging problems since for a given elastic connection the bottleneck link determines the available bandwidth and thereby put constraints on bandwidth at other links. Thereby bandwidth allocation at call arrivals but also bandwidth reallocation at call departure becomes, together with routing, an important issue for investigation. Two series of simulations have been carried out where three different routing schemes have been evaluated together with two bandwidth allocation algorithms. The results indicate that the choice of routing algorithm is load dependent and in a large range the shortest path algorithm properly adopted to the mixed CBR/ABR environment performs very well.

Rapid system prototyping is one of the main applications for field-programmable gate arrays (FPGAs). At the stage of rapid system prototyping, design specifications can often be changed since they cannot be determined completely. In this paper, layout design change is focused on and a layout reconfiguration algorithm is proposed for FPGAs. The target FPGA architecture is developed for transport processing. In order to implement more various circuits flexibly, it has three-input lookup tables (LUTs) as minimum logic cells. Since its logic granularity is finer than that of conventional FPGAs, it requires more routing resources to connect them and minimization of routing congestion is indispensable. In layout reconfiguration, the main problem is to add LUTs to initial layouts. Our algorithm consists of two steps: For given placement and global routing of LUTs, in Step 1 an added LUT is placed with allowing that the position of the added LUT may overlap that of a preplaced LUT; Then in Step 2 preplaced LUTs are moved to their adjacent positions so that the overlap of the LUT positions can be resolved. Global routes are updated corresponding to reconfiguration of placement. The algorithm keeps routing congestion small by evaluating global routes directly both in Steps 1 and 2. Especially in Step 2, if the minimum number of preplaced LUTs are moved to their adjacent positions, our algorithm minimizes routing congestion. Experimental results demonstrate that, if the number of added LUTs is at most 20% of the number of initial LUTs, our algorithm generates the reconfigured layouts whose routing congestion is as small as that obtained by executing a conventional placement and global routing algorithm. Run time of our algorithm is within approximately one second.

An approximation algorithm composed of a digital neural network (DNN) and a modified greedy algorithm (MGA) is presented for the board-level routing problem (BLRP) in a logic emulation system based on field-programmable gate arrays (FPGA's) in this paper. For a rapid prototyping of large scale digital systems, multiple FPGA's provide an efficient logic emulation system, where signals or nets between design partitions embedded on different FPGA's are connected through crossbars. The goal of BLRP, known to be NP-complete in general, is to find a net assignment to crossbars subject to the constraint that all the terminals of any net must be connected through a single crossbar while the number of I/O pins designated for each crossbar m is limited in an FPGA. In the proposed combination algorithm, DNN is applied for m = 1 and MGA is for m 2 in order to achieve the high solution quality. The DNN for the N-net-M-crossbar BLRP consists of N M digital neurons of binary outputs and range-limited non-negative integer inputs with integer parameters. The MGA is modified from the algorithm by Lin et al. The performance is verified through massive simulations, where our algorithm drastically improves the routing capability over the latest greedy algorithms.

Originally intended for application to B-ISDN, which is carrier oriented, ATM technology has been actively studied for application to LAN based environments since the beginning of the 1990s. One of the most notable things in LAN area is development of a rich set of application services. A number of technical specifications for major application services have been developed, which include LAN Emulation, IP over ATM, Multi-protocol over ATM, Voice and Telephony over ATM, as well as Native ATM services such as MPEG2 over ATM. Development of these new services raises new challenges related to traffic management. Keeping pace with the development, a number of traffic control mechanisms have also been developed to maximize the performance of these services. Traffic control and management techniques, however, are still in the early stage of their learning curve. Network engineers are facing challenging problems related to traffic management. This paper reviews major service-related technologies and discusses traffic management issues associated with these services. Especially, it describes the real world traffic management as practiced by average network engineers with state-of-the-art products. Although the thechnology developments have advanced through many research works, there seems to be a considerable gaps between the practice and principles. This paper discusses the traffic issues of ATM LAN from this perspective and points out some challenges for the future. Most of the difficulties in handling traffic issues stems from the differences in implementation details. To alleviate this difficulty, the introduction of a unified node model which describes the traffic handling capability of ATM nodes in sufficient detail is suggested.

The switch LSI described here takes advantage of the special characteristics of fully-depleted CMOS/SIMOX devicesthat is, source/drain capacitances and threshold voltages that are lower than those of conventional bulk CMOS devicesto boost the I/O bit rate. The double-edge triggered MUX/DEMUX which uses a frame synchronization logic, and the active-pull-up I/O provide a 144-pin, 2. 5-Gbps/pin interface on the chip. The 220-kgate rerouting banyan switching network with 110-kbit RAM operates at an internal clock frequency of 312 MHz. The CMOS/SIMOX LSI consumes 8. 4 W when operating with a 2-V power supply, and has four times the throughput of conventional one-chip ATM switch LSIs.

Silva et al. has suggested a criterion based on incidence matrix to verify if a given extended free choice net has a live and bounded marking. This paper shows that this criterion is a necessary and sufficient condition that a given net is a state machine allocatable (SMA) net. This result gives a polynomial algorithm to verify SMA net.

A new type of fiber Fabry-Perot interferometer buried in a fiber connector housing was proposed. The transmission spectra revealed double peaks due to birefringence in the fiber and the peak separation showed a temperature dependence as large as -7. 7 MHz/deg, which was 2 orders of magnitude larger than that estimated from the thermal characteristics of its component materials.

Segmenting the images obtained from magnetic resonance imaging (MRI) is an important process for visualization of the human soft tissues. For the application of MR, we often have to introduce a reasonable segmentation technique. Neural networks may provide us with superior solutions for the pattern classification of medical images than the conventional methods. For image segmentation with the aid of neural networks of a reasonable size, it is important to select the most effective combination of secondary indices to be used for the classification. In this paper, we introduce a vector quantized class entropy (VQCCE) criterion to evaluate which indices are effective for pattern classification, without testing on the actual classifiers. We have exploited a newly developed neural tree classifier for accomplishing the segmentation task. This network effectively partitions the feature space into subregions and each final subregion is assigned a class label according to the data routed to it. As the tree grows on, the number of training data for each node decreases, which results in less weight update epochs and decreases the time consumption. The partitioning of the feature space at each node is done by a simple neural network; the appropriateness of which is measured by newly proposed estimation criterion, i. e. the measure for assessment of neuron (MAN). It facilitates the obtaining of a neuron with maximum correlation between a unit's value and the residual error at a given output. The application of this criterion guarantees adopting the best-fit neuron to split the feature space. The proposed neural classifier has achieved 95% correct classification rate on average for the white/gray matter segmentation problem. The performance of the proposed method is compared to that of a multilayered perceptron (MLP), the latter being widely exploited network in the field of image processing and pattern recognition. The experiments show the superiority of the introduced method in terms of less iterations and weight up dates necessary to train the neural network, i. e. lower computational complexity; as well as higher correct classification rate.

Ferroelectric non-volatile memory (FeRAM) has been inspiring interests since bismuth layer perovskite material family was found to provide "Fatigue Free" endurance, superior retention and imprint characteristics. In this paper, we will provide new circuits technology for FeRAM developed to implement high speed operation, low voltage operation and low power consumption. Performance of LSI embedded with FeRAM for contactless IC card is also provided to demonstrate the feasibility of the circuit technology.

This paper investigates some Z4 codes formed as the Z4-analog (Hensel lifting) of the binary BCH construction. Such codes with length 105 and dimension 13 have been constructed. They are described with their parameters. Some examples of their generator polynomials are given when Hamming weight and Lee weight are different.

The location of stations on the buses can not be ignored in the analysis of the DQDB protocol, especially when traffic load is heavy. In this paper, we propose a new method to model the DQDB (Distributed Queue Dual Bus) protocol by assuming that the request arrival process depends on both the value of the request counter and the location of a station on the buses. By taking these dependences, we can catch the real behavior of the DQDB stations, which is locationally dependent and unfair under heavy load traffic. Based on this model, we analyze the DQDB system with finite buffer by considering the request counter states and buffer states separately and obtain the throughput, mean packet delay and packet reject probability of individual stations. The throughput in individual stations matches that of simulation very well within the range of traffic up to the channel capacity. Also the delay and packet reject rate performance is good up to moderate traffic load. These numerical results reveal the properties of the location dependence and the unfairness of DQDB system under heavy load condition. The analytic results under heavy load traffic for a general DQDB system has not been reported till now. Therefore we conclude that our model and analysis are valid and effective.

Given a binary picture represented by a region quadtree, it is desirable to identify the amount of (rightward and downward) shifts of the foreground components such that it gives the minimum number of nodes of its quadtree. This problem is called "quadtree normalization. " For this problem, it is unknown whether there exists a linear time algorithm with respect to the size of given images (i. e. , the number of pixels). In this study, we investigate the "one-dimensional version" of the quadtree normalization problem, i. e. , given a binary string represented by a regional binary tree, the task is to identify the amount of (rightward) shift of the foreground components such that it gives the minimum number of nodes of its binary tree. We show that there exists a linear time algorithm for this version.

We introduce a subclass of context-free languages, called pure context-free (PCF) languages, which is generated by context-free grammars with only one type of symbol (i. e. , terminals and nonterminals are not distinguished), and consider the problem of identifying paralleled even monogenic pure context-free (pem-PCF) languages, PCF languages with restricted and enhanced features, from positive data only. In this paper we show that the ploblem of identifying the class of pem-PCF languages is reduced to the ploblem of identifying the class of monogenic PCF (mono-PCF), by decomposing each string of pem-PCF languages. Then, with its result, we show that the class of pem-PCF languages is polynomial time identifiable in the limit from positive data. Further, we refer to properties of its identification algorithm.

We describe the design of ECL write circuits and a CMOS memory cell in an ECL-CMOS SRAM to achieve ultra-fast cycle time. Factors determining the write cycle are reduced by several novel circuit techniques and by optimizing the design of the write circuits and CMOS memory cell, thereby, enabling ultra-fast cycle time. Key techniques are a bit line overdriving, the use of an overshoot suppressing emitter follower and a WPG with a replica memory cell delayer. The 72-kb ECL-CMOS SRAM macro through which these techniques were implemented was fabricated using 0. 3-µm BiCMOS technology. The RAM macro achieves a short cycle time of 2 ns without sacrificing stable memory cell operation. These techniques thus provide SRAMs with a shorter cycle time in the cache memories of high performance computer systems.

While active researches have been continuously made on the ATM switch architectures and the QoS service guarantees, most of them have been treated independently in the past. In this paper, we first explain the architectural requirement on the ATM switches to implement the mechanism of QoS guarantees in the context of ATM congestion control. Then we discuss how a vital link between two should be built, and remaining problems are pointed out.

In this paper, we propose an extension of finite state tree automaton, called tree automaton with tree memory (TTA), and also define structure composing TTA (SC-TTA) and backward deterministic TTA (BD-TTA) as subclasses of TTA. We show that the classes of yield languages accepted by TTAs, SC-TTAs and BD-TTAs are equal to the class of recursively enumerable languages, the class of languages generated by tree-to-string finite state translation systems (TSFSTSs) and the class of languages generated by deterministic TSFSTSs, respectively. As a corollary, it is shown that the yield language accepted by an SC-TTA (resp. a BD-TTA) is linear space (resp. polynomial time) recognizable.

Optimization of InGaAs/InAlAs multiple quantum well structures for high-speed and low-driving modulation, as well as polarization insensitivity and low chirp, was investigated as a function of well thickness and strain magnitude. As a result, very short optical pulses with 4-6 ps was obtained using a low driving-voltage (<2. 0 Vpp) electroabsorption modulator module operating at a 40-GHz large signal modulation. Small chirp operation for low insertion loss (<8 dB from fiber-to-fiber) with prebias was also demonstrated and the product of the pulse width and the spectral width was estimated to be 0. 39 for a 5 ps pulse width that is nearly transform-limited.

A traffic engineering method has been developed to meet the requirements for efficient bandwidth dimensioning and for a practical and consolidated network design method. It characterizes the offered-traffic burstiness on a transit link by using time-series measurement of the aggregate traffic. It estimates future traffic characteristics based on the average traffic volume at that time which is easily derived from trend analysis, i. e. , an x% increase in bandwidth each year and gives the required link capacity. Simulation showed that the parameters estimated using this method fit the actual behavior of a network well. This method enables an appropriate bandwidth to be allocated to a transit link without having to estimate the specific traffic characteristics for each connection over the link. Once the burstiness parameter and its trend have been identified based on this method, it is possible to use a simple traffic measurement method to detect changes in network traffic and feed them back to the engineering procedure.

This paper proposes a high-speed input and output buffering ATM switch, named Tandem-Crosspoint (TDXP) switch. The TDXP switch consists of multiple crossbar switch planes. These switch planes are connected in tandem at every crosspoint. Even if a cell can not be transmitted to an output port on the first plane, it has a chance to be transmitted on the next plane. Cell transmission is executed on each switch plane in a pipeline manner. Therefore, more than one cell can be transmitted to the same output port within one cell time slot, although the internal line speed of each switch is equal to the input /output line speed. The TDXP switch architecture has several advantages in implementation. First, the TDXP switch does not increase the internal line speed in eliminating Head-Of-Line (HOL) blocking. Second, since the TDXP switch employs a simple cell reading algorithm at the input buffer in order to retain the cell sequence, the TDXP switch does not require to rebuild the cell sequences at output buffers using time stamps, as is required by a parallel switch. These merits make implementing the high-speed ATM switch easy. Numerical results show that the TDXP switch can eliminate the HOL blocking effectively and achieve high throughput both for unicasting and multicasting traffic. This switch architecture is expected to enable the development of high-speed ATM switching systems that can realize over 1 Tb/s throughput in a cost-effective way.

In this papers, we will discuss the different percentages of embedding certain subsystems successfully into a n-cube according to the fault model used. We will discuss two fault models: the first one assumes that, in a faulty node, the computational function of the node is lost while the communication function of the faulty node remains intact, and, in the second, the communication function is also lost. In this paper, 2 types of fault tolerable subsystem embedding schemes will be introduced. The first one embeds a complete binary tree into a n-cube with faulty nodes, and the second embeds two (n-1)-subcubes whose total number of faulty nodes is less than half the number of nodes. These schemes are divided into 4 types based on the above two models. First, we will discuss how different the successful percentages of embedding are for 2 of the different types of embedded binary trees that are based on the above two models. Then, we will analyze the possibility that the component nodes of an embedded binary tree can communicate via the faulty nodes that are located in the embedded binary tree. In the embedding process, each faulty node was replaced with a nonfaulty node that was located on another (n-1)-subcube and at a Hamming distance of 1 from the faulty node. The number of faults that led to the successful percentage of embedding will be presented as an upper bound. Next, we will discuss how different the successful embedding percentages are for the 2 types of irregular (n-1)-subcubes based on the two models; that is, if 2n-2+1 or more of the nonfaulty nodes in both of the (n-1)-subcubes can communicate or not via faulty nodes. Here also, the number of faults that led to a successful embedding percentage will be presented as a critical value.