This paper describes two attacks against blind decryption (decode) based on the commutative random-self reducibility and RSA systems utilizing the transformability of digital signatures proposed in [2]. The transformable digital signature was introduced in [2],[8] for defeating an oracle attack, where the decrypter could be abused as an oracle to release useful information for an attacker acting as a requester of blind decryption. It was believed in [2],[8] that the correctness of a query to an oracle was ensured by the transformable signature derived from an original signature issued by the decrypter in advance, and a malicious query to an oracle could be detected before the blind decryption by the decrypter or would lead to release no useful information to an attacker. The first attack can decrypt all encrypted data with one access to an oracle. The second one generates a valid signature for an arbitrary message selected by an attacker abusing the validation check procedure.

In B-ISDN, network reliability is a very significant theme. This paper proposes the Failure-Resistant Virtual Path (FRVP) scheme that prevents any information loss even with network failure, to realize a high-end reliability service in B-ISDN. The FRVP scheme is based on simple parallel transmission established using the superior characteristics of ATM. In the FRVP scheme, the transmitter duplicates user cells and transmits them across several VPs simultaneously. The receiver chooses the perfect cells and sends them to the user. As a result, the cell stream output by the receiver is not affected by VP failure if at least one VP remains active. I develop a prototype FRVP system and conduct field trials using NTT's nationwide ATM testbed network. The FRVP scheme is shown to achieve extremely-reliable ATM networks and services.

We present an experimental and theoretical study of multiple diffraction rings of a cw Ar+ laser beam from a nitrobenzene solution of BDN (bis-(4-dimethylaminodithiobenzil)-nickel) caused by the spatial self-phase modulation. We examine in detail the effect of the intensity and phase shift profiles of the beam in the nonlinear medium by comparing the measured ring patterns with the theoretical results based on the Fraunhofer diffraction. Although the thickness of the sample is only 180 µm in our experiment, it is found that the intensity and phase shift profiles are broadened owing to the self-defocusing effect. It is also found that the phase shift profile is further broadened by the thermal diffusion. These two effects become remarkable when the focused beam is used.

Repeaterless transmission system design employing remote pumping in a single fiber is clarified. The design is aimed to realize cost effective submarine transmission systems with easy maintenance. Remote pumping in a single fiber can extend repeaterless transmission distance without decreasing the system capacity per cable. It is applicable for high-count-fiber cable such as the 100-fiber submarine cable already developed. A simple but effective system configuration is presented that uses remote pumping from receiver end; both remote-pre erbium-doped fiber (EDF) amplification and backward pumping Raman amplification are employed. Stable transmission can be obtained without optical isolators, therefore the optical time domain reflectometry (OTDR) method is supported by this system. Three fiber configurations, which consist of dispersion shifted fiber (DSF), pure silica core fiber (PSCF) and a combination of DSF and PSCF, are examined to compare system performance. Remote-pre EDF is optimized in terms of length and location from receiver end by optical SNR (OSNR) calculations. Maximum signal output power is also determined through a waveform simulation based on the split-step Fourier method, in order to avoid waveform distortion caused by the combined effect of self-phase modulation (SPM) and group velocity dispersion (GVD). Through these calculations and simulations, we confirm the proposed repeaterless transmission system performance of 600Mbit/s-451 km with PSCF, 2. 5 Gbit/s-407 km with DSF + PSCF, and 10 Gbit/s-376 km with DSF+PSCF, which include system margin.

A large-scale modular multicast ATM switch based on a three-stage Clos network architecture is proposed and its performance is studied in this paper. The complexity of our proposed switch is NN if the switch size is NN. The first stage of the proposed multicast switch consists of n sorting modules, where n=N. Each sorting module has n inputs and n outputs and is responsible for traffic distribution. The second and third stages consist of modified Knockout switches which are responsible for packet replication and switching. Although it is a multipath network, cell sequence is preserved because only output buffers are used in this architecture. The proposed multicast switch has the following advantages: 1) it is modular and suitable for large scale deployment; 2) no dedicated copy network is required since copying and switching are performed simultaneously; 3) two-stage packet replication is used which gives a maximum fan-out of n2; 4) translation tables are distributed which gives manageable table sizes; 5) high throughput performance for both uniform and nonuniform input traffic; 6) self-routing scheme is used. The performance of the switch under uniform and non-uniform input traffic is studied and numerical examples demonstrate that the cell loss probability is significantly improved when the distribution network is used. In a particular example, it is shown that for the largest cell loss probability in the second stage to be less then 10-11, the knockout expander, with the use of the distribution network, needs only be larger than 6. On the other hand, without the distribution network, the knockout expander must be larger than 13.

In this paper, we propose a new multicast address scheme based on bit map address (BA) and vertex isolation address (VIA) schemes. The proposed scheme can be utilized by the self-routing switch in a speed manner, while preserving the multicast capability. We analyze the processing delay of the proposed scheme and show the efficiency.

The semiconductor lasers operating with self-sustained pulsation are under developing to be lasers which are less disturbed by the optical feedback from a surface of optical disk. Structures setting saturable absorbing regions utilizing the multi-layer configuration become popularly used for giving stronger pulsation. However, the quantum (intensity) noise in these lasers tends to be enhanced. The ridge stripe structure, of which almost self-sustained pulsation lasers consist, seems to give a leak current flowing along plane of the cladding region. Such leak current also increases the quantum noise. In this paper, theoretical calculations of operating characteristics, such as the self-sustained pulsation, the optical output, the quantum noise as well as the transverse filed profile, are theoretically analyzed by including the above mentioned several phenomena.

We consider statistical multiplexing for various types of input data with different statistics in an integrated multimedia system such as ATM networks. The system is assumed to have a constant service rate and a finite buffer. The bit-rate of each data input is variable and is modeled by a fractional Brownian motion process. Under a criterion of quality of service, we obtain an acceptable region of statistical multiplexing. We introduce a new method of investigating the acceptable region of a statistical multiplexer. The results show that transmitting multitype input processes will increase the multiplexing gain.

This paper presents a new self-organization classification algorithm for remote-sensing images. Kohonen and other scholars have proposed self-organization algorithms. Kohonen's model easily converges to the local minimum by tuning the elaborate parameters. In addition to others, S. C. Amatur and Y. Takefuji have also proposed self-organization algorithm model. In their algorithm, the maximum neuron model (winner-take-all neuron model) is used where the parameter-tuning is not needed. The algorithm is able to shorten the computation time without a burden on the parameter-tuning. However, their model has a tendency to converge to the local minimum easily. To remove these obstacles produced by the two algorithms, we have proposed a new self-organization algorithm where these two algorithms are fused such that the advantages of the two algorithms are combined. The number of required neurons is the number of pixels multiplied by the number of clusters. The algorithm is composed of two stages: in the first stage we use the maximum self-organization algorithm until the state of the system converges to the local-minimum, then, the Kohonen self-organization algorithm is used in the last stage in order to improve the solution quality by escaping from the local minimum of the first stage. We have simulated a LANDSAT-TM image data with 500 pixel 100 pixel image and 8-bit gray scaled. The results justifies all our claims to the proposed algorithm.

In this paper, a simple frame synchronization method for the SS-CSC syytem is proposed, and the synchronization performance is analyzed. There have been growing interests in the M-ary/SS communication system and the bi-orthogonal modulation system because these systems can achieve the high frequency utilization efficiency. However, the frame synchronization is difficult. We proposed the SS-CSC system, and evaluated the bit error rate (BER) performance of the SS-CSC system under the completed synchronization. The BER performance of the SS-CSC system is much the same as that of the bi-orthogonal modulation system. In this paper, a frame synchronization method using the differential detector and racing counters is proposed. In particular, the lose lock time, the recovery time and the BER performance considering the synchronizing performance are analyzed. In consequence, the BER performance considering the synchronization performance can approach the lower bound of the SS-CSC system by tuning the number of the stages in racing counters.

A non-isothermal device simulation, consisting of solving heat flow equation three-dimensionally together with other semiconductor equations two-dimensionally, is reported for various arrangements of a pluralty of transistors mounted on a single chip. These arrangements are intended to simulate the real situation in an IC chip whereas a three-dimensional solution of the heat flow equation is aimed at accurately determining the thermal interdependence among individual transistors. As a result, the drain current versus drain voltage characteristics of a miniaturized transistor is found to exhibit a heat-induced negative resistance region.

This paper presents a new multi-clustering network for the purpose of intelligent data classification. In this network, the first layer is a self-organized clustering layer and the second layer is a restricted clustering layer with a neighborhood mechanism. A new clustering algorithm is developed in this system for the efficiently use of parallel processors. This parallel algorithm enables the nodes of this network to be independently processed in order to minimize data communication load among processors. Using the parallel processors, the quite low calculation cost can be realized among the conventional networks. For example, a 4-processor parallel computing system has shown its ability to reduce the time taken for data classification to 26.75% of a single processor system without declining its performance.

In fully connected Multilayer perceptron (MLP), all the hidden units are activated by samples from the whole input space. For complex problems, due to interference and cross coupling of hidden units' activations, the network needs many hidden units to represent the problem and the error surface becomes highly non-linear. Searching for the minimum is then complex and computationally expensive, and simple gradient descent algorithms usually fail. We propose a network, where the input space is partitioned into local sub-regions. Subsequently, a number of smaller networks are simultaneously trained by overlapping subsets of the input samples. Remarkable improvement of training efficiency as well as generalization performance of this combined network are observed through various simulations.

A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the self-timed circuit resets its own voltage to its standby state after 4 inverter delays. This pulsed nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme.

This paper describes cellular spaces (or cellular automata) with capabilities of parallel self-reproduction and of parallel universal simulation of other cellular spaces. It is shown that there is a 1-dimensional cellular space U, called a parallel universal simulator, that can simulate any given 1-dimensional cellular space S in the sense that if an initial configuration of U has a coded information of both the local function and an initial configuration of S, then U has the same computation result that S has and the computation time of U is proportional to that of S. Two models of nontrivial parallel self-reproduction are also shown. One model is based on "state-exchange" method, and the other is based on a fixed point program of the parallel universal simulator.

A highly reliable network which can restore itself from network failures is one important concept for the future high capacity broadband network. In such self-healing network, flooding based failure-restoration algorithm is used to locate new routes and then to reroute failure traffic to that routes automatically when network failures such as link or node failures occur. Since the speed of this algorithm is degraded by the large amount of restoration messages produced by the process, such large volume messages should be reduced. In this paper, the scheme will be proposed, which reduces the large volume messages and efficiently selects alternative routes. In this scheme, the Message Wall will be used to filter useless restoration messages at the tandem nodes and Multi-Message Selecting method will be used to rapidly select a group of link-disjointed alternative routes from the feasible ones in each Flooding Wave sequence. The simulation results show that restoration messages are dramatically reduced and adequate alternative routes can be quickly found out.

This paper describes an analytic method, experimental results and simulation results for self-heating in a SOI (Silicon On Insulator) high voltage MOS transistor. The new analytic method enabled the temperature-rise caused by self-heating to be measured precisely. The temperature-rise in an operating transistor was evaluated by measuring the change of the source current against the source current without the self-heating. In advance, the relation between the temperature-rise and the current change had been prepared by measuring the current decrease when the hot-chuck temperature had been changed in iso-thermal condition. By using this method, the dependence of the temperature-rise or the current decrease on the operating condition or the thermal resistance were clarified. Furthermore, these measurement results and the thermal resistance which is calculated by a FEM analysis enabled a fully coupled electrothermal device simulation to be analyzed more precisely. The dependence of the current decrease on the buried oxide thickness were also calculated.

An overview of known completion-detection methods is given and their advantages and drawbacks are briefly discussed. A relatively new class of single-rail completion-detection techniques is considered in more detail and dimulation results based on adder implementations are presented. A variant of a single-rail technique, which has the advantage of glitch-suppression and robust operation, is introduced. Simulation results are provided, based on a physical layout of the circuit with extracted parasitics.

The performance of synchronous VLSI system is limited by the speed of the global clock which is further constrained by the clock skew. Self-timed design technique, based on the Muller model, improves performance by eliminating the global clock. In order to prevent hazard, a self-timed system should satisfy certain assumptions and timing constraints, therefore special cells are required. The novel Self-timed Cell Library is designed for 1.2µm CMOS technology which contains Muller C-elements, DCVSL circuits, latches and delay elements. It is very useful because: (1) It avoids any possible violations of the assumptions and timing constraints since all cells are custom designed; (2) It provides a fast and reliable model for self-timed system verification using either SPICE simulator or Verilog simulator; (3) It is flexible since it is compatible with an existing Standard Cell Library. In this paper, the library is described. Moreover, the simulated and measured cell characteristics are compared. Using the library, two [18] [81] matrix multipliers employing (1) DCVSL technique, and (2) micropipeline technique have been implemented as design examples and the results are compared. In addition, this paper also demonstrates the benefits of custom-layouted C-elements and a new way to realize delay element for micropipeline. The last but not least, two new HCCs are also proposed.

Built-in self-test (BIST) has been applied to test an analog to digital converter (ADC) and a digital to analog converter (DAC) embedded in a DSP-core ASIC. The eight performance characteristics of the ADC and the DAC designed in accordance with the ITU-T recommendations are measured using the BIST. Three of the eight characteristics - the attenuation/frequency distortion, the variation of gain with input level, and the signal-to-total distortion - have been evaluated and the measured results have shown good agreement with measured results by conventional tests. In the BIST operation, the DSP-core generates input stimulus and analyzes output response by control of the self-test program, The sizes of the self-test program and coefficient data are 822 words of the IROM and 384 words of the data ROM, respectively. This area overhead is less than 0.5% of total chip area. Test-time by the BIST is reduced to approximately 3.2 seconds, which is one-tenth that of conventional testing. The mixed-signal DSP-core ASIC is testable with only logic test equipment, and as a result, test-cost - that is test investment and test-time - is reduced compared with conventional test methods.