We describe a low-cost and extremely stable millimeter-wave transmission system that uses a double-side-band (DSB) millimeter-wave self-heterodyne transmission technique. This technique allows us to use a comparatively low-cost and unstable millimeter-wave oscillator regardless of the modulation format. Furthermore, a transmission band-pass-filter (BPF) is not needed in the millimeter-wave band. The system cost can therefore be substantially reduced. We have theoretically and experimentally evaluated the carrier-to-noise power ratio (CNR) performance that can be obtained when using this technique relative to that attainable through a conventional millimeter-wave self-heterodyne technique where a single-side-band signal is transmitted. Our results show that the DSB self-heterodyne transmission technique can improve CNR by more than 3 dB.

This paper presents a review of volumetric erosion studies applied to electrical contacts. The numerical methods presented are generic and could equally be applied to a number of areas where surfaces have been eroded or damaged. Equally there is no scale limitation of the surfaces to which the numerical methods can be applied. The paper starts with an introduction of the issues associated with the measurement of contact erosion, and then presents a summary of various hardware system for making 3D measurements of surfaces such as electrical contacts. This is followed by a review of the generic form fitting methods and also volume calculation methods. The paper concludes with a review of results taken from a test system for contact studies and from contact samples taken from commercial relays.

Control scheme for accurately optimizing (and also automatically stabilizing) the interferometer phase bias of Symmetric-Mach-Zehnder (SMZ)-type ultrafast all-optical switches is proposed. In this control scheme, a weak cw light is used as a supervisory input light and its spectral power ratio at the switch output is used as a bipolar error signal. Our experimental result at 168-Gb/s 16:1 demultiplexing with a hybrid-integrated SMZ switch indicates the feasibility and the sensitivity of this control scheme.

This letter addresses the issue of RSVP path management in IP micro-mobility networks. We describe efficient RSVP QoS paths with a minimal impact to the existing protocol and underlying routing infrastructure. The goal of this letter is to reduce RSVP path reservation restoration latency and unnecessary control traffic caused by mobility events. We thus propose a RSVP branch-path rerouting scheme at a crossover router (CR) under IP micro-mobility networks. We show that this scheme could give a good tradeoff between the resource reservation cost and the link usage during the lifetime of a RSVP connection.

Polarimetric SAR interferometry has been successful and attractive for forest parameters (tree height and canopy extinction) estimation. In this paper, we propose to use the ESPRIT algorithm to extract the interferometric phase of local scatterers with polarimetric and interferometric SAR data. Two or three local scattering waves can be extracted at each image patch when a fully polarimetric data set (HH, HV, VV) is available. Furthermore, the ESPRIT can estimate two dominant local scattering centers when only a dual polarimetric data set (e.g., VV and VH) is provided. In order to demonstrate effectiveness the proposed technqiue, we examined the relation between local scattering centers extracted by this method and complex coherence of the coherent scattering model for vegetation cover. The results show that the three-wave estimation can be more accurate than the two-wave case. The extracted interferometric phases with full and dual polarization data sets correspond to effective ground and canopy scattering centers. In this investigation, SIR-C/X-SAR data of the Tien Shan flight-pass are used.

In recent years, information devices with network communication ability have become very popular, and many people actually own such kind of devices. Those information devices, however, do not share users' data in spite of their communication ability. This paper proposes "OCEAN: Object Communication Environment for Arbitrary Network" architecture, which provides liaison of objects stored in each device according to their profiles and situations. It eliminates redundant user operation on information devices, and enables novel communication scheme among users by sharing common objects in those devices. Furthermore, it maximizes the effective use of each device's limitation according to each environment. Finally, in this paper, we discuss our prototype of OCEAN.

A heterogeneous parallel computing environment consisting of different types of workstations and communication links plays an important role in parallel computing. In many applications on the system, collective communication operations are commonly used as communication primitives. Thus, design of the efficient collective communication operations is the key to achieve high-performance parallel computing. But the heterogeneity of the system complicates the design. In this paper, we consider design of an efficient gather operation, one of the most important collective operations. We show that an optimal gather schedule is found in O(n2k-1) time for the heterogeneous parallel computing environment with n processors of k distinct types, and that a nearly-optimal schedule is found in O(n) time if k=2.

A high efficient HBT MMIC power amplifier with a new on-chip bias control circuit was proposed for PCS applications. By adjusting the quiescent current in accordance with the output power levels, the average power usage efficiency of the power amplifier is improved by a factor of 1.4. The bias controlled power amplifier, depending on low (high) output power levels, shows 62(103) mA of quiescent current, 16(28) dBm output power with 7.5(35.4)% of power-added efficiency(PAE), -46(-45) dBc of adjacent-channel power ratio (ACPR), and 23.7(26.9) dB of gain

This paper presents a hardware-efficient architecture of tree-depth scan (TDS) and multiple quantization (MQ) scheme for zerotree coding in MPEG-4 still texture coder. The proposed TDS architecture can achieve its maximal throughput to area ratio and minimize the external memory access with only one wavelet-tree size on-chip buffer. The MQ scheme adopts the power-of-two (POT) quantization to realize a cost-effective hardware implementation. The prototyping chip has been implemented in TSMC 0.35 µm CMOS 1P4M technology. This architecture can handle 30 4-CIF (704576) frames per second with five spatial scalability and five SNR scalability layers at 100 MHz working frequency.

This paper presents a practical implementation scheme of the variable gain amplifier (VGA) using a Cds photo coupler (Cds PC) as a variable resister at the feedback loop. The fundamental design policies of IF amplifier stage in superheterodyne receiver were described. We demonstrated the VGA's experimental results. The results indicated the excellent IIP3 of +25 dBm achieved by a gain of 15 dB, and the reasonable thermal stability and variable gain range. Third-order intermodulation distortion (IMD3) comparison between the proposed VGA and conventional PIN diode attenuation type VGA was evaluated and the result indicated that the proposed VGA surpassed the PIN VGA. The proposed VGA was practically fabricated in 455 kHz IF amplifier stage for an airborne VHF communication receiver in order to improve the large signal handling capability to eliminate numerous interferences resulting from the collocated airborne VHF communication systems on the aircraft.

In the case of personal computers (PCs), interoperability among PCs are sufficiently realized with the advent of Microsoft Windows to take the position of mainstream OS, and major software applications following the mainstream for standardization, for more and more user-friendly human machine interface. Considering the case for PCs as above, it is not surprising to us at all, if the same concept is pursued in a radio communications terminal, which can freely access to different radio systems just by replacing the embedded software. This means that the prospective end user will gain the benefit to be able to change his radio set to one of the desired systems in the field, by installing the software of his choice. Such radio equipment is called Software Defined Radio (SDR), and various kinds of applications are expected for development in many fields. However, for the SDR to be in widespread use, we have many outstanding issues to be solved, which are not limited only in the technical matters. One barrier is interoperability among manufacturers. Namely, even when a technical problem is solved, the appropriate technical solution should be shared for the interoperability among as many manufacturers as possible. If such interoperability is unachievable, that technical solution could only be for internal use within the specific manufacturer, failing to take advantage of the true value of the SDR. Another barrier might be the Radio Law of Japan. Unless overcoming this barrier, the commercial implementation of the SDR is unachievable, resulting in the failure to entertain the real benefit from the SDR implication. Under such a background, this paper first describes the concept of and definition for the SDR to make them clearer for the readers. Then, the interoperability issue, which would be the key to the widespread use of SDR, is taken up as next topic. The last topic is focused on the legal and regulatory issue, to discuss what would be the problem under the Radio Law of Japan.

For real-time systems, multiprocessor support is indispensable to handle the large number of requests. Existing on-line scheduling algorithms such as Earliest Deadline First Algorithm (EDF) and Least Laxity Algorithm (LLA) may not be suitable for scheduling hard real-time tasks on multiprocessors. Although EDF has a low context switching overhead, it can produce arbitrarily low processor utilization. LLA has been shown as suboptimal, but has the potential for higher context switching overhead. We propose new on-line scheduling algorithms Earliest Deadline/Least Laxity (ED/LL) and Earliest Deadline Zero Laxity (EDZL) for identical multiprocessors. We show that ED/LL is suboptimal for multiprocessors and EDZL is suboptimal for two processors. Experimental results show that ED/LL and EDZL have low context switching overhead and low deadline miss rate.

Fiber-optic access system integration is the key to providing various kinds of services to home users. The combination of ATM- and SCM-PON systems is essential to support a high-speed data service and analog/digital video distribution services. From this viewpoint, a frequency-division- multiplexing technique for digital baseband and subcarrier multiplexed signals is required to achieve system integration. However, system integration for these two access systems has not been fully investigated yet. The SCM-PON system, which uses a super wideband optical FM converter, will enable these two different kinds of access system (ATM and SCM) to be integrated. In this paper, we describe experimentally obtained results for frequency- division-multiplexed signals consisting of digital baseband and subcarrier- multiplexed signals. The experiments were carried out using a 622-Mb/s baseband signal and an FM-converted signal containing AM and 64QAM signals. The experimental results reveal that the inter-channel interference between the digital baseband and FM-converted signals restricts the number of subcarriers for AM and 64QAM. With an intermediate frequency of 3 GHz for the FM-converted signal, an FDM signal consisting of 622-Mb/s baseband, 30 carriers of 64QAM, and 11 carriers of AM was successfully transmitted.

A debug system for heterogeneous multiple processors in a single chip has been developed. The system consists of the debug interface circuit integrated on the chip, the interface circuit board between the chip and PC, and the debug software implemented on a PC. This debug system has been designed for a multimedia communication processor, which includes an original video processor core, a RISC processor, and a DSP. The RISC processor controls the Video Processing Unit that includes an original video processor and other hardware functions. While in debug mode, the external debugger can control the Video Processing Unit in the same manner as the RISC processor. The JTAG based interface circuit contains registers for bus transaction for command, address, and data to be written, etc. and a bus transaction sequencer. In fact, this system can realize the same bus transaction control as the RISC processor's. By applying proposed debug system, simultaneous debug of the RISC Processing Unit and the Video Processing Unit can be realized. This allows problems to be investigated more quickly and the total time required for debugging is efficiently reduced. Without this technology an estimated 19 weeks is required to debug the chip, whereas use of this technology allowed debugging to be completed in 9 weeks.

We present an efficiency improvement on an existing unlinkable divisible e-cash system. In the based e-cash system, an e-coin can be divided to spent, and thus the exact payments are available. Furthermore, to protect customer's privacy, the system also satisfies the unlinkability in all the payments, which is not satisfied in other existing divisible e-cash systems. The unlinkability means the infeasibility of determining whether two payments are made by the same customer. However, in the unlinkable divisible e-cash system, the payment protocol needs O(N) computations, and thus inefficient, where N indicates the divisibility precision. For example, in case of N=100,000, about 200,000 exponentiations are needed for the worst. We improve the payment protocol using the tree approach. In case of N=100,000, the protocol with our improvement needs only about 600 exponentiations for the worst. This good result can be obtained for other N which is more than about 100.

As we move toward the transition to the IPv6 next generation network environment, it is necessary to realize heterogeneous communications between IPv6 and IPv4 terminals without sacrificing any convenience or frameworks of current communication methods. Mechanisms that satisfy such requirements are called translators. This paper categorizes various translator mechanisms and clarifies their characteristics. As a result of analyses, this paper proposes a SOCKS-based IPv6/IPv4 Translator, and describes its design and implementation. Compared with other translator mechanisms, the SOCKS-based translator have small constraints and good characteristics. For example, it can integrate DNS name resolving procedures, which is an important mechanism for the transition. The translator has already been implemented and it has been proved that it can support typical communication services such as telnet, ftp, http, mail without any problems.

Since any suggestion to regional services are not described in Kerberos, authentication between regions can be performed via PKINIT (Public Key Cryptography for Initial Authentication) presented by IETF (Internet Engineering Task Force) CAT working group. In this paper, an efficient Kerberos authentication mechanism associated with X.509 and Domain Name system (DNS) is presented by employing the two distinct key management systems - asymmetric and symmetric methods. A new protocol is better than the authentication mechanism proposed by IETF CAT Working group in terms of communication complexity.

The purpose of this paper is to improve the detection sensitivity of radio interferometry. The development of wideband signal processing techniques is necessary for high-sensitivity radio interferometry. The higher-order sampling technique can achieve wider bandwidth than expensive wide-baseband conversion system. The over sampling technique can improve the quantization loss from 11.89% to 3.99% at the 4-level quantized sampling. Moreover, the digital filter can reduce the folding noise incurred by the non-rectangular frequency response at a sampling process. It is confirmed that the wideband and low-loss A/D conversion system may be realized by implementing the higher-order sampling, over sampling and digital filtering techniques. In this paper, the key features focusing on these advanced techniques for radio astronomy are presented in detail.

A novel common emitter common collector transistor pair (CECCTP) mixer is presented. A LO pumped CECCTP enables even harmonic mixing operation, and a balanced CECCTP mixer configuration enables the suppression of both 2fLO and fIM2 which are undesirable component for direct conversion mixer. A 2 GHz-band balanced CECCTP mixer is fabricated in SiGe HBT process, and the direct conversion characteristics are measured. It performs conversion gain of 8.8 dB, NF of 14.9 dB and IIP2 of 42.3 dBm when LO power is -6 dBm, supplied voltage is 3 V and current is 5 mA.

In this paper, a novel method of clock feedthrough reduction in CMOS autozeroed operational amplifiers with three-phase clock operation is presented. The operational amplifiers in the method are configured by two autozeroed-gain stages. The differential input stage and the second output gain stage are autozeroed individually by a three-phase clock for autozeroing. The three-phase clock is provided so as to finish the compensation period of the input stage earlier than the end of the second stage compensation period. This operation makes it possible to absorb affection of clock feedthrough in the input stage with the second stage. As a result, residual error of offset compensation is much reduced by the voltage gain of the first stage. The effect of the two-stage autozeroing has been confirmed with SPICE simulation and fabricated CMOS circuit. The results of SPICE simulation showed that the two-stage autozeroed operational amplifier has significant advantage as compared to conventional configuration. Affection of clock feedthrough is reduced to about 1/50 in the two-stage configuration. Fabricated CMOS circuit also showed high potential of the two-stage autozeroed operational amplifier for feedthrough reduction. It has been proven experimentally that the two-stage autozeroing is an effective design approach to reduce clock feedthrough error in CMOS autozeroed operational amplifiers.