Recently with the advent of the IT and the wide spread use of the Internet, new user oriented production and logistic systems, such as the Supply Chain Management System, have been required in order to cope with the drastic and continuous changes on the markets and users' preferences. Therefore, heterogeneous database systems need to be integrated in a common environment which can cope with the heterogeneous requirements of each company under an ever-evolving changing environment. That is assurance. Autonomous Decentralized Database System (ADDS) is proposed as a system architecture in order to realize assurance in distributed database systems. In this system architecture, a loosely-consistency management technology is proposed in order to maintain the consistency of the system, each database can update autonomously, and confer the real time property. A background coordination technology, performed by an autonomous mobile agent, is devised to adapt the system to evolving situations. The system can achieve real time by allocating the information in advance among the sites that has different time constraints for updating. Moreover, an assurance information allocation technology is proposed when considering that a failure in the background coordination mechanism may lead to loss of data and unavailability of the system. This mechanism, in which the mobile agent autonomously regulate its own capacity for allocating the information, is proposed based on the real-time property and system's availability considerations. The effectiveness of the proposed architecture and technologies are evaluated by simulation.

This paper proposes a new on-chip linearizer self-adapting to the input power and its implementation to high linear monolithic microwave integrated circuit (MMIC) power amplifier for 1.95 GHz wide-band code division multiple-access (W-CDMA) system. The linearizer consists of InGaP/GaAs heterojunction bipolar transistor (HBT) active bias circuit and reverse biased junction diode of which dynamic admittance to input power level functions adaptively to control the bias to the amplifier. The proposed linearizer has little insertion power loss, and more importantly, it consumes no additional die area and DC power. The HBT MMIC power amplifier with the integrated linearizer exhibits a maximum output power of 30.3 dBm, a power gain of 27.5 dB, a power added efficiency of 42% at the maximum output power under an operation voltage of 3.4 V, and adjacent channel leakage power ratio of -38 dBc at 27 dBm of output power.

A new class of ternary sequence having a zero-correlation zone (zcz), based on Hadamard matrices, is presented. The proposed sequence construction can simultaneously generate a finite-length ternary zcz sequence set and a periodic ternary zcz sequence set. The generated finite-length ternary zcz sequence set has a zero-correlation zone for an aperiodic function. The generated periodic ternary zcz sequence set has a zero-correlation zone for even and odd correlation functions.

In this study, an improved heterojunction bipolar transistor (HBT) monolithic microwave integrated circuit (MMIC) active mixer is designed and fabricated. The HBT MMIC active mixer that is integrated with a low-noise amplifier (LNA) and active power adder can not only achieve high isolation, but can also dispense with one active component and reduce power consumption at the same time. Measurement results show that the conversion gain, LO-RF isolation, and double sideband noise figure (DSB-NF) of the proposed mixer are 22 dB, 40 dB, and 7 dB, respectively.

High-frequency characteristics of SiGe heterojunction bipolar transistors with different emitter sizes are studied based on pulsed measurements. Because the self-heating effect in transistors will enhance the Kirk effect, as the devices operate in high current region, the measured cutoff frequency and maximum oscillation frequency decrease with measurement time in the pulsed duration. By analyzing the equivalent small-signal device parameters, we know the reduction of cutoff frequency and maximum oscillation frequency is attributed to the reduction of transconductance and the increase of junction capacitances for fixed base-emitter voltage, while it is only attributed to the degradation of transconductance for fixed collector current. Besides, the degradation of high-frequency performance due to self-heating effect would be improved with the layout design combining narrow emitter finger and parallel-interconnected subcells structure.

This paper proposes the constraint availability and bandwidth shortest path (CABSP) selection algorithm and the extension of the adaptive modulation scheme to the CABSP (CABSP-AM) selection algorithm in the millimeter-wave (MMW) broadband entrance network for wireless heterogeneous systems. The CABSP algorithm considers the availability denoted as the quality of the MMW which is severely affected by the rainfall. The CABSP-AM algorithm, moreover, is proposed to further make more efficient use of bandwidth resources by considering the QoS requirements of each class of service in multimedia communication. As the results, the CABSP algorithm yields higher throughput performance than the conventional constraint shortest path (CSP) selection algorithm, but lower than the CABSP-AM algorithm. The spectrum efficiency improvements of the CABSP-AM over the CABSP are about 1.36 and 1.48 fold in case of error sensitive and non-sensitive classes respectively.

This paper proposes a hardware/software cosynthesis algorithm for processors with heterogeneous registers. Given a CDFG corresponding to an application program and a timing constraint, the algorithm generates a processor configuration minimizing area of the processor and an assembly code on the processor. First, the algorithm configures a datapath which can execute several DFG nodes with data dependency at one cycle. The datapath can execute the application program at the least number of cycles. The branch and bound algorithm is applied and all the number of functional units and memory banks are tried. For an assumed number of functional units and memory banks, an appropriate number of heterogeneous registers and connections to functional units and registers are explored. The experimental results show effectiveness and efficiency of the algorithm.

A single chip processor suitable for various multimedia communication products has been developed. This chip achieves real-time bi-directional encoding/decoding for CIF resolution video at a frame rate of 30 fr/s, and meets such standards, as H.320 and H.324. The chip is composed of a video-processing unit for MPEG-4 and H.26X standards, a DSP unit for speech codec and multiplex processes, and a RISC unit for managing the whole chip. By heterogeneous multiple processor architecture, careful study of task sharing for each processing unit and bus configuration, a single chip solution can be achieved with reasonable operation speed and low-power consumption suitable for consumer products. Moreover, by applying an original video processing unit architecture, this chip achieves real-time bi-directional encoding/decoding for CIF-resolution video at a frame rate of 30 fr/s. An original video bus was developed to provide high performance and low-power consumption while sharing one external memory which is necessary for various video processes and graphics functions. This shared memory also has the effect of minimizing die size and I/O ports. This chip has been fabricated with 4-metal 0.18 µm CMOS technology to produce a chip area of 10.510.5 mm2 with 1.2 W power dissipation including I/O power, at 1.8 V for internal supply and 3.3 V for I/O power supply.

We develop a non-concurrent single-failure occurring model, a restoration scheme based on adaptively-decided sub-lightpath rerouting algorithm is then proposed, which aims to achieve better service guaranty with less network status information.

This paper describes synthesis of a complex RiCR filter with a finite transmission zero except zero frequency. The frequency response of the proposed filter is similar to the conventional elliptic filter. The proposed filter can be composed of fewer elements than the conventional one. A new kernel function is proposed. As an example, a fifth-order RiCR filter is designed. We compare the proposed filter with the conventional complex elliptic filter from the viewpoint of the frequency response and the number of the required elements.

Temperature dependence of drain current is analyzed in detail in terms of mobility and threshold voltage. From the analyses, it is proved that a point exists that the drain current is fixed without depending on temperature when the MOSFET operates in strong inversion. Applying this characteristic, a CMOS temperature-voltage converter operating in strong inversion with high linearity is proposed. SPICE simulation and experimental results are shown, and the corresponding performances are discussed.

The present paper introduces a new construction of a class of binary sequence set having a zero-correlation zone (hereafter binary zcz sequence set). The cross-correlation function and the side-lobe of the auto-correlation function of the proposed sequence set is zero for the phase shifts within the zero-correlation zone. This paper shows that such a construction generates a binary zcz sequence set from an arbitrary pair of Hadamard matrices of common size. Since the proposed sequence construction generates a sequence set from an arbitrary pair of Hadamard matrices, many more types of sequence sets can be generated by the proposed sequence construction than is possible by a sequence construction that generates sequence sets from a single arbitrary Hadamard matrix.

Goldwasser and Sipser proved that every interactive proof system can be transformed into a public-coin one (a.k.a. an Arthur-Merlin game). Unfortunately, the applicability of their transformation to cryptography is limited because it does not preserve the computational complexity of the prover's strategy. Vadhan showed that this deficiency is inherent by constructing a promise problem Π with a private-coin interactive proof that cannot be transformed into an Arthur-Merlin game such that the new prover can be implemented in polynomial-time with oracle access to the original prover. However, the transformation formulated by Vadhan has a restriction, i.e., it does not allow the new prover and verifier to look at common input. This restriction is essential for the proof of Vadhan's negative result. This paper considers an unrestricted transformation where both the new prover and verifier are allowed to access and analyze common input. We show that an analogous negative result holds even in this unrestricted case under a non-standard computational assumption.

This paper presents a novel wavelet compression technique to increase compression of images. Based on zerotree entropy coding method, this technique initially uses only two symbols (significant and zerotree) to compress image data for each level. Additionally, sign bit is used for newly significant coefficients to indicate them being positive or negative. Contrary to isolated zero symbols used in conventional zerotree algorithms, the proposed algorithm changes them to significant coefficients and saves its location, they are then treated just like other significant coefficients. This is done to decrease number of symbols and hence, decrease number of bits to represent the symbols used. In the end, algorithm indicates isolated zero coordinates that are used to change the value back to original during reconstruction. Noticeably high compression ratio is achieved for most of the images, without changing image quality.

There are two main types of digital watermark systems. In the first, users are given their own detection programs by which to verify the presence of watermark in data they have in their possession. In the second, users must request such verification from a detection center. The disadvantage of the first type is the possibility that a user might be able to analyze the detection program sufficiently to be able to obtain the secret data (secret key) used to embed the watermark. The disadvantage of the second is the possibility that a center might give dishonest results. In this paper, we propose a watermark detection scheme that can be used to overcome the disadvantages of both: it prevents users from obtaining secret key, and it prevents a center from reporting dishonest results. Our scheme is based on a previously proposed scheme which nearly achieved the same goals but, unfortunately, allowed users to receive watermark detection results for data specially created by them so as to reveal, through the results, secret information about how a center created its watermarks. To overcome this drawback, we have developed new scheme by which a center can prove its detection results to a user without revealing any other information. This scheme was developed by extending the work found in. Moreover we provide an option that prevents the center from encroaching on a user's privacy. The resulting watermark detection scheme is the first that, in addition to protecting secret keys of watermarks from user-tampering, is also able to prevent a center from reporting dishonest results. Although the proposed scheme is introduced first using the patch-work watermarking system, it is straightforward to extend it to a scheme that uses the correlation-based watermarking system, which yields a more robust watermark detection scheme.

In this paper, we propose a compact representation of logic functions using Multi-valued Decision Diagrams (MDDs) called heterogeneous MDDs. In a heterogeneous MDD, each variable may take a different domain. By partitioning binary input variables and representing each partition as a single multi-valued variable, we can produce a heterogeneous MDD with 16% smaller memory size than a Reduced Ordered Binary Decision Diagram (ROBDD), and with comparable memory size to Free Binary Decision Diagrams (FBDDs). And also, heterogeneous MDDs have shorter Average Path Length (APL) than ROBDDs and FBDDs. We minimized a large number of benchmark functions to show the compactness of heterogeneous MDDs.

In this paper, the method of locating multiple transmission zeros by the tap-coupling technique is described for bandpass filters (BPFs), using short-ended λ/2 resonators and its application to a duplexer. First, the method of locating the transmission zero using the short-ended λ/2 resonators is examined with various excitation methods. We focus on four types of short-ended λ/2 resonators: the end-coupling type, tap-coupling type, capacitive tap-coupling type and inductive tap-coupling type. Secondly, the BPFs based on the basic characteristics of the respective resonators are proposed and designed on the basis of a general filter theory with narrow band approximation. Lastly, we propose and design new duplexers consisting of the proposed BPFs. The results lead to the conclusion that the basic characteristics of the short-ended λ/2 resonators are useful for realizing a BPF with multiple transmission zeros and a high-performance duplexer fabricated without increasing the number of elements.

One-dimentional equivalent circuit model of a heterostructure InAlAs/InGaAs/InP metal-semiconductor-metal photodetector is discussed. In this photodetector, InGaAs is used as an optical absorption layer and the InAlAs is used for Schottky barrier enhanement. The measured S11 parameter deviates from equi-resistance lines on the Smith chart, indicating the equivalent circuit is different from the conventional equivalent circuit using a series resistance, a depletion region capacitance and a depletion region resistance. The difference is due to band discontinuity at the heterojunctions, and we propose a equivalent circuit taking account of the band discontinuity. The band discontinuity is expressed by parallel combination of a resistance and a capacitance. The measured S11 parameter can be fitted well with the calculated S11 parameter from the proposed equivalent circuit, and we can successfully extract the device parameters from the fitted curve.

For the mass production of GaN-based electronic devices, growth of AlGaN/GaN heterostructures on substrates larger than 100 mm in diameter is indispensable. In this study, we demonstrate the growth of 100-mm-diameter Al0.26Ga0.74N/GaN heterostructures on sapphire substrates by metalorganic vapor phase epitaxy (MOVPE). The obtained films have specular surfaces, good crystal quality and good uniformity of alloy composition across the entire 100-mm-diameter epitaxial wafer. The bowing value of the 100-mm-diameter epitaxial wafer on c-face sapphire substrates is about 40 µm. This bowing value seems to be preferable for electronic device fabrication processes. These epitaxial wafers show good electrical properties.

TCAD is gaining acceptance in the heterostructure industry. This article discusses the specific challenges a device simulator must manage to be a useful tool in designing and optimizing modern heterostructure devices. Example simulation results are given for HEMTs and HBTs, illustrating the complex physical processes in heterostructure devices, such as nonlocal effects in carrier transport, lattice self-heating, hot-electron effects, traps, electron tunneling, and quantum transport.