The search functionality is under construction.
The search functionality is under construction.

Keyword Search Result

[Keyword] FA(3430hit)

781-800hit(3430hit)

  • NAND Phase Change Memory with Block Erase Architecture and Pass-Transistor Design Requirements for Write and Disturbance

    Koh JOHGUCHI  Kasuaki YOSHIOKA  Ken TAKEUCHI  

     
    PAPER

      Vol:
    E97-C No:4
      Page(s):
    351-359

    In this paper, we propose an optimum access method for a phase change memory (PCM) with NAND strings. A PCM with a block erase interface is proposed. The method, which has a SET block erase operation and fast RESET programming, is proposed since the SET operation causes a slow access time for conventional PCM;. From the results of measurement, the SET-ERASE operation is successfully completed while the RESET-ERASE operation is incomplete owing to serial connection. As a result, the block erase interface with the SET-ERASE and RESET program method realizes a 7.7 times faster write speed compared than a conventional RAM interface owing to the long SET time. We also give pass-transistor design guidelines for PCM with NAND strings. In addition, the write-capability and write-disturb problems are investigated. The ERASE operation for the proposed device structure can be realized with the same current as that for the SET operation of a single cell. For the pass transistor, about 4.4 times larger on-current is needed to carry out the RESET operation and to avoid the write-disturb problem than the minimum RESET current of a single cell. In this paper, the SET programming method is also verified for a conventional RAM interface. The experimental results show that the write-capability and write-disturb problems are negligible.

  • Hypersphere Sampling for Accelerating High-Dimension and Low-Failure Probability Circuit-Yield Analysis

    Shiho HAGIWARA  Takanori DATE  Kazuya MASU  Takashi SATO  

     
    PAPER

      Vol:
    E97-C No:4
      Page(s):
    280-288

    This paper proposes a novel and an efficient method termed hypersphere sampling to estimate the circuit yield of low-failure probability with a large number of variable sources. Importance sampling using a mean-shift Gaussian mixture distribution as an alternative distribution is used for yield estimation. Further, the proposed method is used to determine the shift locations of the Gaussian distributions. This method involves the bisection of cones whose bases are part of the hyperspheres, in order to locate probabilistically important regions of failure; the determination of these regions accelerates the convergence speed of importance sampling. Clustering of the failure samples determines the required number of Gaussian distributions. Successful static random access memory (SRAM) yield estimations of 6- to 24-dimensional problems are presented. The number of Monte Carlo trials has been reduced by 2-5 orders of magnitude as compared to conventional Monte Carlo simulation methods.

  • Effect of Multivariate Cauchy Mutation in Evolutionary Programming

    Chang-Yong LEE  Yong-Jin PARK  

     
    PAPER-Fundamentals of Information Systems

      Vol:
    E97-D No:4
      Page(s):
    821-829

    In this paper, we apply a mutation operation based on a multivariate Cauchy distribution to fast evolutionary programming and analyze its effect in terms of various function optimizations. The conventional fast evolutionary programming in-cooperates the univariate Cauchy mutation in order to overcome the slow convergence rate of the canonical Gaussian mutation. For a mutation of n variables, while the conventional method utilizes n independent random variables from a univariate Cauchy distribution, the proposed method adopts n mutually dependent random variables that satisfy a multivariate Cauchy distribution. The multivariate Cauchy distribution naturally has higher probabilities of generating random variables in inter-variable regions than the univariate Cauchy distribution due to the mutual dependence among variables. This implies that the multivariate Cauchy random variable enhances the search capability especially for a large number of correlated variables, and, as a result, is more appropriate for optimization schemes characterized by interdependence among variables. In this sense, the proposed mutation possesses the advantage of both the univariate Cauchy and Gaussian mutations. The proposed mutation is tested against various types of real-valued function optimizations. We empirically find that the proposed mutation outperformed the conventional Cauchy and Gaussian mutations in the optimization of functions having correlations among variables, whereas the conventional mutations showed better performance in functions of uncorrelated variables.

  • Analyzing Information Flow and Context for Facebook Fan Pages Open Access

    Kwanho KIM  Josué OBREGON  Jae-Yoon JUNG  

     
    LETTER

      Vol:
    E97-D No:4
      Page(s):
    811-814

    As the recent growth of online social network services such as Facebook and Twitter, people are able to easily share information with each other by writing posts or commenting for another's posts. In this paper, we firstly suggest a method of discovering information flows of posts on Facebook and their underlying contexts by incorporating process mining and text mining techniques. Based on comments collected from Facebook, the experiment results illustrate how the proposed method can be applied to analyze information flows and contexts of posts on social network services.

  • Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters

    Takashi MIYAMORI  Hui XU  Hiroyuki USUI  Soichiro HOSODA  Toru SANO  Kazumasa YAMAMOTO  Takeshi KODAKA  Nobuhiro NONOGAKI  Nau OZAKI  Jun TANABE  

     
    PAPER

      Vol:
    E97-C No:4
      Page(s):
    360-368

    New media processing applications such as image recognition and AR (Augment Reality) have become into practical on embedded systems for automotive, digital-consumer and mobile products. Many-core processors have been proposed to realize much higher performance than multi-core processors. We have developed a low-power many-core SoC for multimedia applications in 40nm CMOS technology. Within a 210mm2 die, two 32-core clusters are integrated with dynamically reconfigurable processors, hardware accelerators, 2-channel DDR3 I/Fs, and other peripherals. Processor cores in the cluster share a 2MB L2 cache connected through a tree-based Network-on-Chip (NoC). Its total peak performance exceeds 1.5TOPS (Tera Operations Per Second). The high scalability and low power consumption are accomplished by parallelized software for multimedia applications. In case of face detection, the performance scales up to 64 cores and the SoC consumes only 2.21W. Moreover, it can execute the 1080p 48fps H.264 decoding about 520mW by 28 cores and the 4K2K 15fps super resolution about 770mW by 32 cores in one cluster. Exploiting parallelism by low power processor cores, the many-core SoC provides several tens of times better energy efficiency than that of a high performance desk-top quad-core processor.

  • Facial Expression Recognition Based on Facial Region Segmentation and Modal Value Approach

    Gibran BENITEZ-GARCIA  Gabriel SANCHEZ-PEREZ  Hector PEREZ-MEANA  Keita TAKAHASHI  Masahide KANEKO  

     
    PAPER-Image Recognition, Computer Vision

      Vol:
    E97-D No:4
      Page(s):
    928-935

    This paper presents a facial expression recognition algorithm based on segmentation of a face image into four facial regions (eyes-eyebrows, forehead, mouth and nose). In order to unify the different results obtained from facial region combinations, a modal value approach that employs the most frequent decision of the classifiers is proposed. The robustness of the algorithm is also evaluated under partial occlusion, using four different types of occlusion (half left/right, eyes and mouth occlusion). The proposed method employs sub-block eigenphases algorithm that uses the phase spectrum and principal component analysis (PCA) for feature vector estimation which is fed to a support vector machine (SVM) for classification. Experimental results show that using modal value approach improves the average recognition rate achieving more than 90% and the performance can be kept high even in the case of partial occlusion by excluding occluded parts in the feature extraction process.

  • No-Reference Quality Metric of Blocking Artifacts Based on Color Discontinuity Analysis

    Leida LI  Hancheng ZHU  Jiansheng QIAN  Jeng-Shyang PAN  

     
    LETTER-Image Processing and Video Processing

      Vol:
    E97-D No:4
      Page(s):
    993-997

    This letter presents a no-reference blocking artifact measure based on analysis of color discontinuities in YUV color space. Color shift and color disappearance are first analyzed in JPEG images. For color-shifting and color-disappearing areas, the blocking artifact scores are obtained by computing the gradient differences across the block boundaries in U component and Y component, respectively. An overall quality score is then produced as the average of the local ones. Extensive simulations and comparisons demonstrate the efficiency of the proposed method.

  • Parameterized Multisurface Fitting for Multi-Frame Superresolution

    Hongliang XU  Fei ZHOU  Fan YANG  Qingmin LIAO  

     
    LETTER-Image Processing and Video Processing

      Vol:
    E97-D No:4
      Page(s):
    1001-1003

    We propose a parameterized multisurface fitting method for multi-frame super-resolution (SR) processing. A parameter assumed for the unknown high-resolution (HR) pixel is used for multisurface fitting. Each surface fitted at each low-resolution (LR) pixel is an expression of the parameter. Final SR result is obtained by fusing the sampling values from these surfaces in the maximum a posteriori fashion. Experimental results demonstrate the superiority of the proposed method.

  • Nb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process Evaluation Open Access

    Shuichi NAGASAWA  Kenji HINODE  Tetsuro SATOH  Mutsuo HIDAKA  Hiroyuki AKAIKE  Akira FUJIMAKI  Nobuyuki YOSHIKAWA  Kazuyoshi TAKAGI  Naofumi TAKAGI  

     
    INVITED PAPER

      Vol:
    E97-C No:3
      Page(s):
    132-140

    We describe the recent progress on a Nb nine-layer fabrication process for large-scale single flux quantum (SFQ) circuits. A device fabricated in this process is composed of an active layer including Josephson junctions (JJ) at the top, passive transmission line (PTL) layers in the middle, and a DC power layer at the bottom. We describe the process conditions and the fabrication equipment. We use both diagnostic chips and shift register (SR) chips to improve the fabrication process. The diagnostic chip was designed to evaluate the characteristics of basic elements such as junctions, contacts, resisters, and wiring, in addition to their defect evaluations. The SR chip was designed to evaluate defects depending on the size of the SFQ circuits. The results of a long-term evaluation of the diagnostic and SR chips showed that there was fairly good correlation between the defects of the diagnostic chips and yields of the SRs. We could obtain a yield of 100% for SRs including 70,000JJs. These results show that considerable progress has been made in reducing the number of defects and improving reliability.

  • Efficient Randomized Byzantine Fault-Tolerant Replication Based on Special Valued Coin Tossing

    Junya NAKAMURA  Tadashi ARARAGI  Shigeru MASUYAMA  Toshimitsu MASUZAWA  

     
    PAPER-Dependable Computing

      Vol:
    E97-D No:2
      Page(s):
    231-244

    We propose a fast and resource-efficient agreement protocol on a request set, which is used to realize Byzantine fault tolerant server replication. Although most existing randomized protocols for Byzantine agreement exploit a modular approach, that is, a combination of agreement on a bit value and a reduction of request set values to the bit values, our protocol directly solves the multi-valued agreement problem for request sets. We introduce a novel coin tossing scheme to select a candidate of an agreed request set randomly. This coin toss allows our protocol to reduce resource consumption and to attain faster response time than the existing representative protocols.

  • Secrecy Capacity and Outage Performance of Correlated Fading Wire-Tap Channel

    Jinxiao ZHU  Yulong SHEN  Xiaohong JIANG  Osamu TAKAHASHI  Norio SHIRATORI  

     
    PAPER-Fundamental Theories for Communications

      Vol:
    E97-B No:2
      Page(s):
    396-407

    The fading channel model is seen as an important approach that can efficiently capture the basic time-varying properties of wireless channels, while physical layer security is a promising approach to providing a strong form of security. This paper focuses on the fundamental performance study of applying physical layer security to achieve secure and reliable information transmission over the fading wire-tap channel. For the practical scenario where the main channel is correlated with the eavesdropper channel but only the real time channel state information (CSI) of the main channel is known at the transmitter, we conduct a comprehensive study on the fundamental performance limits of this system by theoretically modeling its secrecy capacity, transmission outage probability and secrecy outage probability. With the help of these theoretical models, we then explore the inherent performance tradeoffs under fading wire-tap channel and also the potential impact of channel correlation on such tradeoffs.

  • Time-Varying AR Spectral Estimation Using an Indefinite Matrix-Based Sliding Window Fast Linear Prediction

    Kiyoshi NISHIYAMA  

     
    PAPER-Digital Signal Processing

      Vol:
    E97-A No:2
      Page(s):
    547-556

    A method for efficiently estimating the time-varying spectra of nonstationary autoregressive (AR) signals is derived using an indefinite matrix-based sliding window fast linear prediction (ISWFLP). In the linear prediction, the indefinite matrix plays a very important role in sliding an exponentially weighted finite-length window over the prediction error samples. The resulting ISWFLP algorithm successively estimates the time-varying AR parameters of order N at a computational complexity of O(N) per sample. The performance of the AR parameter estimation is superior to the performances of the conventional techniques, including the Yule-Walker, covariance, and Burg methods. Consequently, the ISWFLP-based AR spectral estimation method is able to rapidly track variations in the frequency components with a high resolution and at a low computational cost. The effectiveness of the proposed method is demonstrated by the spectral analysis results of a sinusoidal signal and a speech signal.

  • Pose-Free Face Swapping Based on a Deformable 3D Shape Morphable Model

    Yuan LIN  Shengjin WANG  

     
    PAPER-Computer Graphics

      Vol:
    E97-D No:2
      Page(s):
    305-314

    Traditional face swapping technologies require that the faces of source images and target images have similar pose and appearance (usually frontal). For overcoming this limit in applications this paper presents a pose-free face swapping method based on personalized 3D face modeling. By using a deformable 3D shape morphable model, a photo-realistic 3D face is reconstructed from a single frontal view image. With the aid of the generated 3D face, a virtual source image of the person with the same pose as the target face can be rendered, which is used as a source image for face swapping. To solve the problem of illumination difference between the target face and the source face, a color transfer merging method is proposed. It outperforms the original color transfer method in dealing with the illumination gap problem. An experiment shows that the proposed face reconstruction method is fast and efficient. In addition, we have conducted experiments of face swapping in a variety of scenarios such as children's story book, role play, and face de-identification stripping facial information used for identification, and promising results have been obtained.

  • Voting Sharing: An Approach to Reducing Computation Time for Fault Diagnosis in Time-Triggered Systems

    Kohei SAKURAI  Masahiro MATSUBARA  Tatsuhiro TSUCHIYA  

     
    LETTER-Information Network

      Vol:
    E97-D No:2
      Page(s):
    344-348

    We propose a lightweight scheme for fault diagnosis in time-triggered (TT) systems. An existing scheme is preferable in its capability but incurs computation time that can be prohibitively large for some real-time systems, such as automotive control systems. Our proposed scheme, which we call voting sharing, can substantially reduce the computation time by sharing the diagnosis result obtained by each node with all nodes in the system. We clarify the properties of the voting sharing scheme with respect to fault tolerance and show some experimental results.

  • Rule-Based Redundant Via-Aware Standard Cell Design Considering Multiple Via Configuration

    Tsang-Chi KAN  Ying-Jung CHEN  Hung-Ming HONG  Shanq-Jang RUAN  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E97-A No:2
      Page(s):
    597-605

    Well designed redundant via-aware standard cells (SCs) can increase the redundant via1 insertion rate in cell-based designs. However, in conventional methods, manual- and visual-based checks are required to locate pins and tune the geometries of layouts. These tasks can be very time consuming and unreliable. In this work, an O(Nlog N) redundant via-aware standard cell optimization scheme is developed. The proposed method is an efficient layout check and optimization scheme that considers various redundant via configurations including the double-via and rectangle-via to shorten the design time for standard cells. The optimized SCs effectively increase the redundant via insertion rate, and in particular the insertion rate of via1 for both concurrent routing and post-layout optimization. Furthermore, an automatic layout checker and optimizer are more efficient in identifying expandable metal 1 pins in libraries that contain numerous cells than are conventional visual check and manual optimization. Therefore, the proposed scheme not only solves the problem of a low via1 insertion rate in nanometer regimes, but also provides an efficient layout optimizer for designing standard cells. Experimental results indicate that the optimized standard cells increase the double-via1 insertion rates by 21.9%.

  • Ideas, Inspirations and Hints Those I Met in the Research of Electromagnetic Theory Open Access

    Kazuo TANAKA  

     
    INVITED PAPER

      Vol:
    E97-C No:1
      Page(s):
    3-10

    “How to get the original ideas” is the fundamental and critical issue for the researchers in science and technology. In this paper, the author writes his experiences concerning how he could encounter the interesting and original ideas of three research subjects, i.e., the accelerating medium effect, the guided-mode extracted integral equation and the surface plasmon gap waveguide.

  • A Method of Parallelizing Consensuses for Accelerating Byzantine Fault Tolerance

    Junya NAKAMURA  Tadashi ARARAGI  Toshimitsu MASUZAWA  Shigeru MASUYAMA  

     
    PAPER-Dependable Computing

      Vol:
    E97-D No:1
      Page(s):
    53-64

    We propose a new method that accelerates asynchronous Byzantine Fault Tolerant (BFT) protocols designed on the principle of state machine replication. State machine replication protocols ensure consistency among replicas by applying operations in the same order to all of them. A naive way to determine the application order of the operations is to repeatedly execute the BFT consensus to determine the next executed operation, but this may introduce inefficiency caused by waiting for the completion of the previous execution of the consensus protocol. To reduce this inefficiency, our method allows parallel execution of the consensuses while keeping consistency of the consensus results at the replicas. In this paper, we also prove the correctness of our method and experimentally compare it with the existing method in terms of latency and throughput. The evaluation results show that our method makes a BFT protocol three or four times faster than the existing one when some machines or message transmissions are delayed.

  • Methods of Estimating Return-Path Capacitance in Electric-Field Intrabody Communication

    Tadashi MINOTANI  Mitsuru SHINAGAWA  

     
    PAPER-Antennas and Propagation

      Vol:
    E97-B No:1
      Page(s):
    114-121

    This paper describes a very accurate method of estimating the return-path-capacitance and validates the estimation based on low-error measurements for electric-field intrabody communication. The return-path capacitance, Cg, of a mobile transceiver is estimated in two ways. One uses the attenuation factor in transmission and capacitance, Cb, between a human body and the earth ground. The other uses the attenuation factor in reception. To avoid the influence of the lead wire in the estimation of Cb, Cb is estimated from the attenuation factor measured with an amplifier with a low input capacitance. The attenuation factor in reception is derived by using the applied-voltage dependence of the reception rate. This way avoids the influence of any additional instruments on the return-path capacitance and allows that capacitance to be estimated under the same condition as actual intrabody communication. The estimates obtained by the two methods agree well with each other, which means that the estimation of Cb is valid. The results demonstrate the usefulness of the methods.

  • Method of Image Green's Function in Grating Theory: Extinction Error Field

    Junichi NAKAYAMA  Yasuhiko TAMURA  

     
    BRIEF PAPER-Periodic Structures

      Vol:
    E97-C No:1
      Page(s):
    40-44

    This paper deals with an integral equation method for analyzing the diffraction of a transverse magnetic (TM) plane wave by a perfectly conductive periodic surface. In the region below the periodic surface, the extinction theorem holds, and the total field vanishes if the field solution is determined exactly. For an approximate solution, the extinction theorem does not hold but an extinction error field appears. By use of an image Green's function, new formulae are given for the extinction error field and the mean square extinction error (MSEE), which may be useful as a validity criterion. Numerical examples are given to demonstrate that the formulae work practically even at a critical angle of incidence.

  • Virtual Continuous CWmin Control Scheme of WLAN

    Yuki SANGENYA  Fumihiro INOUE  Masahiro MORIKURA  Koji YAMAMOTO  Fusao NUNO  Takatoshi SUGIYAMA  

     
    PAPER-Foundations

      Vol:
    E97-A No:1
      Page(s):
    40-48

    In this paper, a priority control problem between uplink and downlink flows in IEEE 802.11 wireless LANs is considered. The minimum contention window size (CWmin) has a nonnegative integer value. CWmin control scheme is one of the solutions for priority control to achieve the fairness between links. However, it has the problem that CWmin control scheme cannot achieve precise priority control when the CWmin values become small. As the solution of this problem, this paper proposes a new CWmin control method called a virtual continuous CWmin control (VCCC) scheme. The key concept of this method is that it involves the use of small and large CWmin values probabilistically. The proposed scheme realizes the expected value of CWmin as a nonnegative real number and solves the precise priority control problem. Moreover, we proposed a theoretical analysis model for the proposed VCCC scheme. Computer simulation results show that the proposed scheme improves the throughput performance and achieves fairness between the uplink and the downlink flows in an infrastructure mode of the IEEE 802.11 based wireless LAN. Throughput of the proposed scheme is 31% higher than that of a conventional scheme when the number of wireless stations is 18. The difference between the theoretical analysis results and computer simulation results of the throughput is within 1% when the number of STAs is less than 10.

781-800hit(3430hit)