Reduction of the complexity of the NLMS algorithm has received attention in the area of adaptive filtering. A processing cost reduction method, in which the component of the weight vector is updated when the absolute value of the sample is greater than or equal to the average of the absolute values of the input samples, has been proposed. The convergence analysis of the processing cost reduction method has been derived from a low-pass filter expression. However, in this analysis the effect of the weignt vector components whose adaptations are skipped is not considered in terms of the direction of the gradient estimation vector. In this paper, we use an arbitrary value instead of the average of the absolute values of the input samples as a threshold level, and we derive the convergence characteristics of the processing cost reduction method with arbitrary threshold level for zero-mean white Gaussian samples. From the analytical results, it is shown that the range of the gain constant to insure convergence and the misadjustment are independent of the threshold level. Moreover, it is shown that the convergence rate is a function of the threshold level as well as the gain constant. When the gain constant is small, the processing cost is reduced by using a large threshold level without a large degradation of the convergence rate.

A new multiple-valued mask-ROM cell and a technique suitable for data detection are proposed. The information is programmed in each of the memory cells as both the threshold voltage and the channel length of the memory cell transistor, and the stored data are detected by selecting the bias condition of both the word-line and the data-line. The datum stored in the channel length is read-out using punch-through effect at the high drain voltage. The feasibility of this mask-ROM's is studied with device simulation and circuit simulation. With this design, it would be possible to get the high-density mask-ROM's, which might be faster in access speed and easier in fabrication process than the conventional ones. Therefore, this design is expected to be one of the most practical multiple-valued mask-ROM's.

A method of range image segmentation using four Markov random field(MRF)s is described in this paper. MRFs are used in depth smoothing, gradient smoothing, edge detection and surface type labeling stage. First, range and its gradient images are smoothed preserving jump and roof edges respectively using line process concept one after another. Then jump and roof edges are extracted, combined and refined using penalizing undesirable edge patterns. Finally, curvatures are computed and the surface types are labeled according to the signs of principal curvatures. The surface type labels are refined using winner-takes-all layers in the stage. The final output is a set of regions with its exact surface type. The energy function is used in order to represent constraints of each stage and the minimum energy state is found using iterative method. Several experimental results show the generality of our approach and the execution speed of the proposed method is faster than that of a typical region merging method. This promises practical applications of our method.

This paper proposes a buried-LATID structure featuring a peaked vertical profile around gate edge for the n- drain unlike the reported conventional LATID structure. As compared to the conventional LATID FETs, the deep-submicron buried-LATID FETs achieve improved circuit speed by 7% (50% compared to LDD FETs) due to suppressed gate-to-drain capacitance and improved lifetime by 10 times (300 times compared to LDD FETs). The buried-LATID FETs are very promising for deep-submicron MOSFETs to achieve improved performance and hot-carrier reliability at the same time.

This paper describes a segment driver IC for high-quality liquid-crystal-displays (LCDs). Major design issues in the segment driver IC are a wide signal bandwidth and excessive output-offset variation both within a chip and between chips. After clarifying the trade-off relation between the signal bandwidth and the output-offset variation originated from conventional sample-and-hold (S/H) circuits, two wide-band S/H circuits with low output-offset variation have been introduced. The basic ideas for the proposed S/H circuits are to improve timing of the sampling pulses applied to MOS analog switches and to prevent channel charge injection onto a storage capacitor when the switches turn off. The inter-chip offset-cancellation technique has been also introduced by using an additional S/H circuit. Two test chips were implemented using the above S/H circuits for demonstration purposes. The intra-chip output-offset standard deviation of 9.5 mVrms with a 3dB bandwidth of 50 MHz was achieved. The inter-chip output-offset standard deviation was reduced to 5.1 mVrms by using the inter-chip offset-cancellation technique. The evaluation of picture quality of an LCD using the chips shows the applicability of the proposed approaches to displays used for multimedia applications.

This paper newly estimates the yield suppression for 1.5 V-1 Gbit DRAM caused by threshold voltage variation of MOSFET due to microscopic fluctuations in dopant distributions within the channel region and points out the limitation of the conventional redundancy techniques. The yield suppression is estimated for four main circuit blocks, the memory cell transfer transistor, bit line sense amplifier S/A, I/O line differential amplifier D/A, and the peripheral circuit. It is newly found that for 1.5 V-1 Gbit DRAM due to the effect of the newly estimated threshold voltage variation of MOSFET the bit failures of memory cells become the most dominant failure mode and the failure of D/A which can be ignored for 64 Mbit DRAM level can no longer be neglected. Furthermore, the novel optimized redundancy technique for replacing these failure is described.

This paper describes modeling and simulation of submicron NMOSFET current drive focusing on carrier velocity-saturation effects. A new simple analytical model is proposed which predicts a significant degradation of drain current in sub- and quarter-micron NMOSFET's. Numerical two-dimensional simulations clarify that the degradation is namely caused by high lateral electric field along the channel, which leads to deep velocity-saturation of channel electrons even at the source end. Experimental data of NMOSFET's, with gate oxide thickness (Tox) of 9-20 nm and effective channel lengths (Leff) of 0.35-3.0 µm, show good agreement with the proposed model. It is found that the maximum drain current at the supply voltage of Vdd=3.3 V is predicted to be proportional to Leff0.54 in submicron NMOSFET's, and this is verified with experiments.

An analog approach alternative to the Hopfield method is presented for solving constrained combinatorial optimization problems. In this new method, a saddle point of a Lagrangian function is searched using a constrained dynamical system with the aid of an appropriate transformation of variables. This method always gives feasible solutions in contrast to the Hopfield scheme which often outputs infeasible solutions. The convergence of the method is proved theoretically and some effective schemes are recommended for eliminating some variables for the case we resort to numerical simulation. An analog electronic circuit is devised which implements this method. This circuit requires fewer wirings than the Hopfield networks. Furthermore this circuit dissipates little electrical power owing to subthreshold operation of MOS transistors. An annealing process, if desired, can be performed easily by gradual increase in resistance of linear resistors in contrast to the Hopfield circuit which requires the variation in the gain of amplifiers. The objective function called an energy is ensured theoretically to decrease throughout the annealing process.

This paper describes the current situations and future directions of intelligent CAI researches/development in Japan. Then necessity of intelligence in CAIs/Educational systems are thought over corresponding to the model of teaching and the cognitive model of human learning like the situated learning, knowledge construction and so on. Originally, the main aims of ITSs/ICAIs are to tealize the high level environment of individual teaching/learning. So it is the most important to incorporate the intellectual function of teaching into the system. Whatever kinds of teaching purposes ITSs have, they have the quite complex structure which consists of the domain knowledge base (Expert system), student model, the tutoring knowledge base, the powerful human interface, and sophisticated inference engine with plural functions by artificial intelligence technology. In this paper, the technological and educational points of view are discussed, surveyed and summarized based on intelligent teaching functions of ITSs/ICAIs. Moreover, the meaning of new paradigm from ITSs to ILE are mentioned under the new technology of networking and multi-media.

Leakage enhancement after an ESD event has been analyzed for output buffer LDD MOSFETs. The HBM ESD failure threshold for the LDD MOSFETs is only 200-300 V and the failure is the leakage enhancement of the off-state MOSFETs called as "soft breakdown" leakage. This leakage enhancement is supposed to be caused by trapped electrons in the gate oxide and/or creation of interface states at the gate overlapped drain region due to snap-back stress during the ESD event. The mechanism of the lekage can be explained by band-to-band and/or interface state-to-band tunneling of electrons. The improvement of the HBM ESD threshold has been also evaluated by using two types of drain engineering which are additional arsenic implantation for the output LDD MOSFETs and "offset" gate MOSFET as a protection circuit for the output pins. By using these drain engineering, the threshold can be improved to more than 2000 V.

This is a full text of my presentation titled "Evaluation of Maintenability Improvement by Systems Reliability Growth" at the First Beijing International Conference on Reliability Maintenability and Safety (BICRMS'92). This thesis describes evaluation methods of reliability growth for field working systems by surveying maintenability improvement. And it also touch upon customer satisfaction. As unavailability is suitable for measuring reliability, I use in this thesis a decrease in unavailability per month as a means to evaluate reliability and its growth. "Maintenability" is broadly defined as a system's capability to maintain, repair and recover its functions with the aid of failsoft and RAISIS. The term "Customer satisfaction" is difficult to define, but on the practical market basis it can be fairly easily and objectively measured by examining the cancel rate by customers. This thesis includes topics such as: (1) When a system is in disorder it can restore its original functions although, strictly speaking, such system changes are classified as another systems statistically. (2) Despite this, we need to evaluate a specific system's reliability continously, and study reliability growth, industrial life, and customer satisfaction. Unavailability can be reduced by improving systems through upgrading component.

This paper presents a high-density multiple-valued content-addressable memory (MVCAM) based on a floating-gate MOS device. In the proposed CAM, a basic operation performed in each cell is a threshold function that is a kind of inverter whose threshold value is programmable. Various multiple-valued operations for data retrieval can be easily performed using threshold functions. Moreover, each cell circuit in the MVCAM can be implemented using only a single floating-gate MOS transistor. As a result, the cell area of the four-valued CAM are reduced to 37% in comparison with that of the conventional dynamic CAM cell.

For analyzing the transient electromagnetic fields caused by electrostatic discharge (ESD), a new ESD model is presented here. Numerical calculation is also given to explain the distinctive phenomenon being well-recognized in the ESD event.

To make a fast Bi-CMOS SRAM yield high without speed degradation, three defect-repair methods, the address comparison method, the fuse decoder method and the distributed fuse method, were considered in detail and their advantages and disadvantages were made clear. The distributed fuse method is demonstrated to be further improved by a built-in fuse word driver and a built-in fuse column selector, and fuse analog switches. This enhanced distributed fuse scheme was examined in a fast Bi-CMOS SRAM. A maximun access time of 14 ns and a chip size of 8.8 mm17.4 mm are expected for a 4 Mb Bi-CMOS SRAM in the future.

The method to optimize redundancy scheme for memory devices is proposed. Yield for new generation memories is predicted by failure mode analysis of previous generation memories. Fabrication line improvement and chip area penalty by the redundancy are taken into account for this yield prediction. The actual data of 16 Mbit EPROM failure analysis indicate the effectiveness of the prediction.

The effective dielectric constant εeff of discrete random medium composed of many dielectric spheres has been analyzed by EFA (Effective Field Approximation), QCA (Quasicrystalline Approximation) and QCA-CP (Quasicrystalline Approximation and Coherent Potential) in the case where the optical path length is very large in the medium. These methods lead to a reasonable K for non-large dielectric constants of spheres, while their methods yield an unphysical dependence of εeff on large dielectric constants of spheres: that is, the εeff does not become large for increasing the dielectric constant. In this paper, we remove the unphysical dependence and present new results for εeff of our method, comparing with the results for εeff of EFA, QCA and QCA-CP.

We propose a new multiple folding algorithm for the gate matrix layout, and apply it to generation of rectangular blocks with flexible size. The algorithm consists of two phases, the net partitioning and the gate arangement, and both algorithms are based on the multi-way mini-cut technique. In the first and second phases, the width and height of the multiple folded gate matrix block are directly minimized, resperctively, such that the area is minimized and desired aspect ratio of the block is obtained. The features of the present algorithm are as hollows: (1) Dead space on the gate matrix block can be minimized, (2) the aspect ratio can be controlled finely, (3) since polar graphs are successfully used in the second phase, the efficiency of the algorithm can be much improved. The experimental results show the effectiveness of our algorithm.

This paper presents a linear time optimal algorithm to a channel pin assignment problem for hierarchical building-block layout design. The channel pin assignment problem is to determine positions of the pins of nets on the top and the bottom sides of a channel, which are partitioned into several intervals, and the pins are permutable within their associated intervals. The channel pin assignment problem has been shown NP-hard in general. We present a linear time optimal algorithm for an important special case of the problem, in which there is at most one pin of a net within each interval in the channel. The proposed algorithm is optimal in a sense that it can minimize both the channel density and the total wire length of the channel. We also disscuss how to apply our algorithm to the pin assignment in the L-shaped and staircase channels. Experimental results indicate that substantial reduction in both channel density and estimated total wire length can be obtained by permuting pins in each interval. Combining the proposed algorithm with a conventional channel router, results of channel routing also achieve large amount of reduction of the number of tracks, total wire length, and the number of vias.

The fast and highly reliable method reported here uses two techniques to detect all types of defects, such as unsoldered leads, solder bridges, and misalignes leads in the minute solder joints of high density mounted devices. One technique uses external force applied by an air jet that vibrates or shifts unsoldered leads. The vibration and shift is detected as a change in the speckle pattern produced by laser illumination of the solder joints. The other technique uses fluorescence generated by short-wavelength laser illumination. The fluorescence from a printed circuit board produces a silhouette of the solder joint and this image is processed to detect defects. Experimental results show that this inspection method detects all kinds of defects accurately and with a very low false alarm rate.

This paper presents a new method to derive the phase difference between n-tuples of an m-sequence over GF(p) of period pn-1. For the binary m-sequence of the characteristic polynomial f(x)=xn+xd+1 with d=1,2c or n-2c, the explicit formulas of the phase difference from the initial n-tuple are efficiently derived by our method for specific n-tuples such as that consisting of all 1's and that cosisting of one 1 and n-1 0's, although the previously known formula exists only for that consisting of all 1's.