This paper presents a design procedure of a directional coupler consisting of a twofold symmetric four-port circuit with four identical matching networks at each port. The intrinsic power-split ratio and the equivalent admittance of the directional coupler are formularized in terms of the eigenadmittances of the original four-port without the matching networks. These formulas are useful for judgment on the realizability of a directional coupler in a given circuit structure and for design of the matching networks. Actually, the present procedure is applied to designing various quadrature hybrids and directional couplers, and its practical usefulness as well as several new circuit structures are demonstrated.

Replication to mask the effects of failures is a basic technique for improving reliability of a file system. Consistency control protocols are implemented to ensure the consistency among these replicas. The native token-based mechanism which merely sequences the distributed requests suffered from the poor system utilization due to the lack of dependence checking between writes and management of out-of-ordered requests. Hence, in this paper, by utilizing the idempotent property of NFS and executing ahead most of independent WRITE requests, the new consistency control scheme is proposed to improve the performance of operations and failure recovery. Finally, a numeric case shows the efficiency of the new scheme.

This paper presents a non-scan design scheme to enhance delay fault testability of controllers. In this scheme, we utilize a given state transition graph (STG) to test delay faults in its synthesized controller. The original behavior of the STG is used during test application. For faults that cannot be detected by using the original behavior, we design an extra logic, called an invalid test state and transition generator, to make those faults detectable. Our scheme allows achieving short test application time and at-speed testing. We show the effectiveness of our method by experiments.

A simple Minimum Rate Supporting Scheduler (MRSS) is proposed for HSDPA (High Speed Downlink Packet Access). MRSS guides the user selection in order to provide, if any, a prespecified minimum rate for each user. The simulation results show that MRSS successfully supports to keep the minimum rate up to fairly high traffic load, where existing methods fail, with tolerable degradation in throughput.

In this paper, iterative adaptive soft parallel interference canceller (ASPIC) is proposed for turbo coded multiple-input multiple-output (MIMO) multiplexing. ASPIC is applied to transform a MIMO channel into single-input multiple-output (SIMO) channels for maximum ratio diversity combining (MRC). In the ASPIC, replicas of the interference are generated and subtracted from the received signals. For the generation of replicas with higher reliability, iterative ASPIC is proposed. It performs the iterative interference cancellation by feedback of the log-likelihood ratio (LLR) sequence obtained as the turbo decoder output. For iterative ASPIC, at the transmitter, the information sequence and parity sequence are transmitted from different antennas. In this paper, the achievable bit error rate (BER) performance, in a Rayleigh fading channel, for the turbo coded MIMO multiplexing with the proposed iterative ASPIC system is evaluated by computer simulation.

This paper proposes a Real-Time Compression Architecture (RTCA), which maximizes the efficiency of web services, while reducing the response time at the same time. The developed architecture not only guarantees the freshness of compressed contents but also minimizes the time needed to compress the message, especially when the traffic is heavy.

An efficient data transmission interface for VLSI systems, Multi-Bit Parallel Code Division Multiple Access (MB/P-CDMA) interface, has been designed with 0.35 µm CMOS technology. The proposed interface achieves 1.12 Gb/s data rate (80 MHz, 8 bit bus) using multi-bit transmission at each clock per transmitter. The proposed CDMA interface ensures higher speed operation than conventional interface even in noisy environments. Each of the transmitters and receivers occupies the die area of 290 360 µm2 and 240 280 µm2, respectively.

We present a built-in self-reconfiguring system for a mesh-connected processor array where faulty processor elements are compensated for by spare processing elements located in one row and one column. It has advantages in that the number of spare processing elements is small and additional control circuits and networks for changing interconnections of processing elements is so simple that hardware overhead for reconfiguration is also small. First, to indicate the motivation to the proposed reconfiguration scheme, we briefly describe other schemes with the same number of spares as that of the proposed scheme where faulty processing elements are replaced using straight shifts toward spares, and compare their reconfiguration probabilities to each other. Then, we show that a variant of the proposed scheme has the highest probability. Next, we present a built-in self-reconfiguring system for the scheme and formally prove that it works correctly. It can automatically replace faulty processors by spare processors on detecting faults of processors.

This paper proposes a SNR estimation scheme based on Gibbs sampler. This scheme can estimate SNR using a very short received sequence, and does not require any prior information of the transmitted symbol. Compared with the existing estimators, the performance of this method is better when real SNR is larger than 5 dB in both single path channel and multi-path channel.

Energy consumption is one of the most critical constraints in the design of portable embedded systems. This paper describes an empirical study about the impacts of compiler optimizations on the energy consumption of the address bus between processor and instruction memory. Experiments using a number of real-world applications are presented, and the results show that transitions on the instruction address bus can be significantly reduced (by 85% on the average) by the compiler optimizations together with bus encoding.

Subcircuits designed for integrated silicon DCS1800/ PCS1900 base station receivers have been reconfigured into hybrid and single-chip Doppler radar transceivers. Radar chips have been fully integrated in 0.25 µm silicon CMOS and BiCMOS processes. These chips have been used to monitor heart and respiration activity without contact, and they have successfully detected heartbeat and respiration rate up to 1 m from the subject. This monitoring device may be useful in home monitoring, continuous monitoring, and physiological research.

The scattering problem by metallic gratings has become one of fundamental problems in electromagnetics. In this paper, a thin metallic grating placed in conical mounting is treated as a lossy dielectric grating expressed by complex permittivity and thickness. The solution of the metallic grating by using the matrix eigenvalue calculations is compared with that of the plane grating by using the resistive boundary condition and the spectral Galerkin procedure, and the availability of the resistive boundary condition for thin metallic gratings in conical mounting is investigated. In order to improve the convergence of the solutions of thin metallic gratings, the spatial harmonics of flux densities which are continuous function instead of electromagnetic fields are used.

Sensor nodes are prone to failure and have limited power capacity, so the evaluation of fault tolerance and the creation of technology for improved tolerance are among the most important issues for wireless sensor networks. The placement of sensor nodes is also important, since this affects the availability of nodes within sensing range of a target in a given location and of routes to the base station. However, there has been little research on the placement of sensor nodes. Furthermore, all research to date has been based on deterministic node placement, which is not suitable when a great many sensor nodes are to be placed over a large area. In such a situation, we require stochastic node placement, where the sensor-positions are in accord with a probability density function. In this paper, we examine how fault tolerance can be improved by stochastic node placement that produces scale-free characteristics, that is, where the degree of the nodes follows a power law.

This study proposes a 3 dB branch-line coupler using radial stubs to achieve reduced coupler size and simplified stub arrangement. As the electrical lengths of stubs used here are less than 90at center frequency, a method of comparing input impedances to obtain radial stubs that are equivalent to straight stubs is discussed. The frequency characteristics of the proposed coupler are derived by combining classical transmission line theory with the computed data of radial stub input impedances. The methods presented here increase possibilities for realizing reduced branch-line couplers by means of stub design. Experimental results agree well with theoretical results except for slight differences in the high frequency region.

A novel parallel acceleration technique is proposed based on intrinsic parallelism characteristics of shooting-and-bouncing ray launching (SBR) algorithm, which has been implemented using the MPI parallel library on common PC cluster instead of dedicated parallel machines. The results reveal that the new technique achieves very large speedup gains and could be the efficient and low-cost propagation prediction solution.

A cryogenic Whispering Gallery sapphire resonator oscillator has been investigated using a 4 K pulse-tube cryocooler. The turnover temperature of the chosen mode in the sapphire crystal was 9.17 K with an unloaded Q-factor of 7108. The prototype sapphire-loaded cavity oscillator was designed to oscillate at 9.195 GHz. A fractional frequency stability of 210-13 was measured at integration times of 10 s.

This paper presents a multipath interference canceller (MPIC) configuration based on multipath interference (MPI) replica generation per transmit antenna (called PTA-MPIC). This configuration is associated with Space Time Transmit Diversity (STTD) for the common control physical channel (CCPCH), which takes advantage of tentative decision data after STTD decoding, and with closed-loop type phase control (PC) transmit diversity for the dedicated physical channel (DPCH) employing tentative decision data after diversity combining, in the W-CDMA forward link. This paper also proposes transmitter carrier phase verification, i.e., an antenna verification method used in PC transmit diversity, that utilizes the dedicated pilot symbols in a DPCH after the PTA-MPIC removes the MPI components. The one-stage PTA-MPIC removes the MPI from the common pilot channel (CPICH), the CCPCH, and the synchronization channel (SCH). The simulation results show that this canceller reduces the required average transmit Eb/N0 of the DPCH at the average BER of 10-3 by approximately 3.0 dB compared to that using a MF-based Rake receiver (the transmit power ratio of each common channel to DPCH is RCPICH/DPCH = 3 dB, RCCPCH/DPCH = 5 dB, and RSCH/DPCH = 3 dB, with TPC and without antenna diversity reception at the user equipment). Furthermore, it is shown that in the two-stage PTA-MPIC with MPI suppression for all channels associated with PC transmit diversity, the required average transmit Eb/N0 employing the proposed antenna verification is reduced by approximately 0.3 dB, 0.5 dB, and 1.2 dB compared to that using the conventional antenna verification when the transmission power ratio of the interfering DPCH to the desired DPCH is RInt/Des = 0 dB, 3 dB, and 6 dB for ten DPCHs. This is because the number of detection errors of the transmitted carrier phase in the second antenna due to feedback information bit decoding error is reduced.

An analog neurochip for independent component analysis (ICA) is designed with on-line learning capability. Due to the limited dynamic range of analog device, the nonholonomic ICA algorithm is adopted. In order to accommodate the offsets due to device mismatches, a modified algorithm is developed with 2-quadrant multipliers and self-adjusting biases. Performance of the developed system was demonstrated by Monte-Carlo simulation.

Active replication is a common approach to building highly available and reliable distributed software applications. The redundant nested invocation (RNI) problem arises when servers in a replicated group issues nested invocations to other server groups in response to a client invocation. Automatic suppression of RNI is always a desirable solution, yet it is usually a difficult design issue. If the system has multithreading support, the difficulties of implementation increase dramatically. Intuitively, to design a deterministic thread execution control mechanism is a possible approach. Unfortunately, some modern operating systems implement thread on kernel level for execution fairness. For the kernel thread case, modification on thread control implies modifying the operating system kernel. This approach loses system portability which is one of the important requirements of CORBA or middleware. In this work, we propose a mechanism to perform the auto-suppression of redundant nested invocation in an active replication fault-tolerant (FT) CORBA system. Besides the mechanism design, we discuss the design correctness semantic and the correctness proof of our design.

This paper proposes a new implementation of an adaptive noise canceller based upon a parallel block structure, which aims to raise the processing and convergence rates and to improve the steady-state performance. The procedure is as follows: First, an IIR bandpass filter with a variable center angular frequency using adaptive Q-factor control and two adaptive control signal generators are realized by the parallel block structure. Secondly, a new algorithm for adaptive Q-factor control with parallel block structure is proposed to improve the convergence characteristic. In addition, the steady-state performance of the filter is stabilized by using the variable step size parameter in adaptive control of the center frequency and the speed up of the convergence rate is achieved by adopting a normalized gradient algorithm for adaptive control. Finally, simulation results are given to demonstrate the convergence performance.