Since components faults occurring at arbitrary places (primarily on the links) affect seriously network performance and reliability, the multicomputers operating in harsh environments should be designed to guarantee normal network-missions in presence of those faults. One solution to the end is a fault-tolerant routing scheme, which enables messages to safely reach their destinations avoiding failed links when transmission of messages is blocked by certain faults. In the paper, we develop a fault-tolerant routing algorithm with deadlock freedom in an n-dimensional meshed network, and validate its efficiency and effectiveness through proper simulations. The aspects of fault-tolerance is adopted by appending partial-adaptiveness and detouring to the e-cube algorithm, while using a wormhole routing for the backbone routing method. The phenomenon of deadlock incurred due to its adaptiveness is eliminated by classifying a physical channel into a couple of virtual channels.

Various types of wavelength-selectable light sources (WSLs) and wavelength-tunable laser diodes (LDs) have been developed, and the one based on an array of distributed feedback (DFB) laser diodes (LDs) has the advantage of tuning that is both simple and stable tuning. It requires only the selection of a DFB-LD and a temperature control. We report on monolithically integrated WSLs with a DFB-LD array, multimode interference (MMI) coupler, semiconductor optical amplifier (SOA), and electro-absorption (EA) modulator. To make them compact, we introduced microarray structures and to ensure that they were easy to fabricate, we used selective area growth. For the WSL with an integrated EA modulator, we developed a center-temperature-shift method that optimizes the detuning wavelength between the lasing wavelength and the absorption edge wavelength of the EA-modulator. Using this method, we obtained a uniform extinction ratio and were able to demonstrate error-free 2.5-Gb/s transmission over a 600-km fiber span. A CW-WSL without an EA-modulator should provide enough output power to compensate the loss caused by the external modulators, but the high-power operation of a CW-WSL is sensitive to optical feedback from the front facet. We therefore used an angled facet in our WSLs and eliminated a mode hop problem. More than 20 mW of fiber-coupled power was obtained over 23 ITU-T channels on a 50-GHz grid.

The redundancy allocation problem for a series-parallel system is a well known as one of NP-hard combinatorial problems and it generally belongs to the class of nonlinear integer programming (nIP) problem. Many researchers have developed the various methods which can be roughly categorized into exact solution methods, approximate methods, and heuristic methods. Though each method has both advantages and disadvantage, the heuristic methods have been received much attention since other methods involve more computation effort and usually require larger computer memory. Genetic algorithm (GA) as one of heuristic optimization techniques is a robust evolutionary optimization search technique with very few restrictions concerning with the various design problems. However, GAs cannot guarantee the optimality and sometimes can suffer from the premature convergence situation of its solution, because it has some unknown parameters and it neither uses a priori knowledge nor exploits the local search information. To improve these problems in GA, this paper proposes an effective hybrid genetic algorithm based on, 1) fuzzy logic controller (FLC) to automatically regulate GA parameters and 2) incorporation of the iterative hill climbing method to perform local exploitation around the near optimum solution for solving redundancy allocation problem. The effectiveness of this proposed method is demonstrated by comparison results with other conventional methods on two different types of redundancy allocation problems.

This paper deals with security issues in a mobile agent system, especially protecting agent data from malicious servers. For this purpose, one-time key generation system, OKGS in short, is proposed. In OKGS, we integrate notions of an one-way hash function and a coupler. A one-way function plays a major role in ensuring confidentiality and integrity of agent data. And the notion of a coupler is used to establish inter-relationship among consecutive encryption keys for agent data, i.e,. all agent keys form a unidirectional chain. With these two features of OKGS, therefore, only the agent owner, who creates the agent bearing data, can decrypt and protect all agent data which are gathered in its itinerary.

High-end telecommunication systems in the larger nationwide networks of the next decade will require routers having a packet switching throughput capacity of over 10 Tbps. In such future high-end routers, the packet switch, which is the biggest bottleneck of the router, will need higher processing speeds than semiconductor devices. We propose a high-end router system architecture using single flux quantum (SFQ) technology. This system consists of semiconductor line card units and an SFQ switch card unit. The features of this switch card architecture are (1) using internal speedup architecture to reduce effective loads in the network, (2) using a packet switch scheduler to attain non-blocking characteristics. This architecture can expand the switching capacity to a level greater than tens of Tbps scale, keeping with non-blocking characteristics.

In this letter, an algorithm that estimates one of the most important channel parameters, maximum Doppler frequency, fD, is proposed. The algorithm uses phase variations of received pilot signals, which is strongly related with fD in a fading environment. In addition, a phase variation measurement method for binary phase shift keying (BPSK) modulated signals is also proposed and it makes possible to estimate fD from BPSK modulated information signals as well as unmodulated pilot signals. The results show that the proposed algorithm is very simple and shows good performance over wide Doppler frequency range.

In this paper, we propose a new scheduling algorithm to achieve fault tolerance in multiprocessor systems. This algorithm first partitions a parallel program into subsets of tasks, based on the notion of height of a task graph. For each subset, the algorithm then duplicates and schedules the tasks in the subset successively. We prove that schedules obtained by the proposed algorithm can tolerate a single processor failure and show that the computational complexity of the algorithm is O(|V|4) where V is the set of nodes of a task graph. We conduct simulations by applying the algorithm to two kinds of practical task graphs (Gaussian elimination and LU-decomposition). The results of this experiment show that fault tolerance can be achieved at the cost of small degree of time redundancy, and that performance in the case of a processor failure is improved compared to a previous algorithm.

Pulse tube cryocoolers receive considerable attention due to their intrinsically higher durability and lower vibrations than other regenerative coolers such as Gifford-McMahon or Stirling cycle coolers. This paper describes basic function and classification of the pulse tube cryocoolers from the viewpoint of electronic applications.

In distributed systems, the provision for failure-recovery is always a hot design issue, whereas no fault-tolerant feature has been extensively considered in the current RMI, CORBA and other OODP environments. As a result, application developers have to implement their own fault tolerant mechanisms. In this paper, we propose a fault-tolerant development environment based on one kind of RMI, called FT_HORB, as a Java extension for the reliable distributed computing with checkpoints and rollback-recovery mechanism. The FT_HORB is implemented on the Sun Ultra10 workstations connected through a 100 Mbps network. We observe that experimental applications on the FT_HORB can continue their operations in spite of hardware and software failures. Three benchmark models such as the nqueens problem, the traveling salesman problem and the gaussian elimination problem are experimented with the FT_HORB to evaluate its performance. The results show the performance of FT_HORB is acceptable. In addition, experiments demonstrate its possibility of extension to fully support our optimal design goal.

A stabilized local oscillator is one of the key components for any radar system, especially for a Doppler radar in detecting slowly moving targets. Based on hybrid semiconductor/superconductor circuitry, the HTS local oscillator produces stable, low noise performance superior to that achieved with conventional technology. The device combines a high Q HTS sapphire cavity resonator (f=5.6 GHz) with a C-band low noise GsAs HEMT amplifier. The phase noise of the oscillator, measured by a HP 3048A noise measurement system, is -134 dBc/Hz at 10 kHz offset at 77 K.

This paper proposes constructive timing-violation (CTV) and evaluates its potential. It can be utilized both for increasing clock frequency and for reducing energy consumption. Increasing clock frequency over that determined by the critical paths causes timing violations. On the other hand, while supply voltage reduction can result in substantial power savings, it also causes larger gate delay and thus clock must be slow down in order not to violate timing constraints of critical paths. However, if any tolerant mechanisms are provided for the timing violations, it is not necessary to keep the constraints. Rather, the violations would be constructive for high clock frequency or for energy savings. From these observations, we propose the CTV, which is supported by the tolerant mechanism based on contemporary speculative execution mechanisms. We evaluate the CTV using a cycle-by-cycle simulator and present its considerably promising potential.

We achieved a dispersion tolerance of 25-ps/nm at 80-Gbit/s using novel carrier-suppressed return-to-zero (CS-RZ) coding realized by duty ratio and optical multiplexing phase control. We also show that the dispersion tolerance strongly depends on the relative optical phase difference between adjacent time slots, and demonstrate 80-Gbit/s 60-km DSF transmission without dispersion compensation by using a newly-fabricated stable 80-Gbit/s OTDM transmitter.

In this study, a hybrid genetic algorithm/neural network with fuzzy logic controller (NN-flcGA) is proposed to find the global optimum of reliability assignment/redundant allocation problems which should be simultaneously determined two different types of decision variables. Several researchers have obtained acceptable and satisfactory results using genetic algorithms for optimal reliability assignment/redundant allocation problems during the past decade. For large-size problems, however, genetic algorithms have to enumerate numerous feasible solutions due to the broad continuous search space. Recently, a hybridized GA combined with a neural network technique (NN-hGA) has been proposed to overcome this kind of difficulty. Unfortunately, it requires a high computational cost though NN-hGA leads to a robuster and steadier global optimum irrespective of the various initial conditions of the problems. The efficacy and efficiency of the NN-flcGA is demonstrated by comparing its results with those of other traditional methods in numerical experiments. The essential features of NN-flcGA namely, 1) its combination with a neural network (NN) technique to devise initial values for the GA, 2) its application of the concept of a fuzzy logic controller when tuning strategy GA parameters dynamically, and 3) its incorporation of the revised simplex search method, make it possible not only to improve the quality of solutions but also to reduce computational cost.

The C166S V2 is Infineon Technologies' latest generation 16-bit microcontroller core, member of the C166 family. This new core architecture is a huge step forward in performance and DSP capabilities: With its single cycle engine and enhanced MAC unit running at up to 200 MHz it more than doubles the performance of the fastest C166 based controllers (C166S V1) running at the same speed. Furthermore the instruction set is fully compatible with the previous C166 cores. This architecture is specifically suited for real-time embedded systems with high requirements for performance and signal processing functionality with tight cost and power budgets. As a fully synthesizable core, and with a large selection of peripherals available, the C166 V2 provides a straightforward path to the required specific systems-on-chip.

We have developed optical encoding devices for processing femtosecond pulses. These devices are based on spectral separation devices and light modulators with fiber gratings. Experiments were made to encode a light pulse in the spectral domain. These experiments utilize the characteristics that a femtosecond light pulse has a very broad spectrum. An input femtosecond light pulse is decomposed into a series of wavelength components. Each wavelength component with narrow spectra <1 nm width is successfully extracted into a single mode fiber. Light modulators corresponding to wavelength components are assigned to the 1st bit, the 2nd bit, the 3rd bit, , the nth bit, respectively. All of the encoded wavelength components are again recombined into a single time-varying signal and transmitted through an optical fiber. Decoding at receiving site is made by the reverse operation. Encoding and decoding for 2-bit and 4-bit signals were demonstrated for 200 fs input light pulse with about 40 nm spectral width.

A tunable external-cavity InGaAs/AlGaAs quantum-well laser using a grating coupler monolithically integrated in a selectively disordered waveguide is demonstrated. The laser consists of an amplifier with a narrow channel for lateral single-mode guiding and a tapered section, a grating coupler for output beam collimation and wavelength dispersion, and an external half mirror. Selective quantum-well disordering technique using SiO2 caps of different thicknesses and rapid thermal annealing was employed to reduce the passive waveguide loss in the grating coupler region. Loss reduction from 40 cm-1 to 3 cm-1 was accomplished. Resultant increase of the grating coupler efficiency and expansion of the effective aperture length led to significant improvement of the laser performances. The maximum output power of 105 mW and wide tuning range of 21.1 nm centered at 997 nm were obtained. The well collimated output beam of full diffraction angles at half maximum of 0.16 0.18 was obtained.

Antialiased is one of challenging problems to be solved for the high fidelity image synthesis in 3D graphics. In this paper a rasterization processor which is capable of single-pass full-screen antialiasing is presented. To implement a H/W accelerated single-pass antialiased rasterization processor at the reasonable H/W cost and minimized processing performance degradation, our work is mainly focused on the efficient H/W implementation of a modified version of the A-buffer algorithm. For the efficient handling of partial-pixel fragments of the rasterization phase, a new partial-pixel-merging scheme and a simple and efficient new dynamic memory management scheme are proposed. For the final blending of partial-pixels without loss of generality, a parallel subpixel blender is introduced. To study the feasibility of the proposed rasterization processor as a practical rasterization processor, a prototype processor has been designed using a 0.35 µm EML technology. It operates 100 MHz @3.3 V and has the rendering performance from 25M to 80M pixel-fragments/sec depending on the scene complexity.

A mesh-connected processor array consists of many similar processing elements (PEs), which can be executed in both parallel and pipeline processing. For the implementation of an array of large numbers of processors, it is necessary to consider some fault tolerant issues to enhance the (fabrication-time) yield and the (run-time) reliability. In this paper, we introduce the 1(1/2)-track switch torus array by changing the connections in 1(1/2)-track switch mesh array, and we apply our approximate reconfiguration algorithm to the torus array. We describe the reconfiguration strategy for the 1(1/2)-track switch torus array and its realization using WSI, especially 3-dimensional realization. A hardware realization of the algorithm is proposed and simulation results about the array reliability are shown. These imply that a self-reconfigurable system with no host computer can be realized using our method, hence our method is effective in enhancing the run-time reliability as well as the fabrication-time yield of processor arrays.

This paper treats the data routing problem for fault-tolerant systolic arrays based on Triple Modular Redundancy (TMR) in mixed spatial-temporal domain. The number of logical links required in TMR systolic array is basically 9 times larger than the one for corresponding non-fault-tolerant systolic array. The link sharing is a promising method for reducing the number of physical links, which may, however, degrade the fault tolerance of TMR system. This paper proposes several robust data-routing and resource-sharing (plural data transfers share a physical link, or a data transfer and a computational task share a PE as a relay node for the former and as a processor for the latter), by which certain classes of fault tolerant property will be guaranteed. A stage and a dominated set are introduced to characterize the features of routing/resource-sharing in TMR systems, and conditions on the dominated set and their resultant fault-tolerant properties are derived.

This paper investigates the interference suppression effect from much higher rate dedicated physical channels (DPCHs) of a parallel-type coherent multistage interference canceller (COMSIC) with iterative channel estimation (ICE) by laboratory experiments in the transmit-power-controlled W-CDMA reverse link. The experimental results elucidate that when two interfering DPCHs exist with the spreading factor (SF) of 8 and with the ratio of the target signal energy per bit-to-interference power spectrum density ratio (Eb/I0) of fast transmit power control, ΔEb/I0, of -6 dB (which corresponds to 64 simultaneous DPCHs with SF = 64, i.e., the same symbol rate as the desired DPCH), the implemented COMSIC receiver with ICE exhibits a significant decrease in the required transmit signal energy per bit-to-background noise power spectrum density ratio (Eb/N0) at the average bit error rate (BER) of 10-3 (while the matched filter (MF)-based Rake receiver could not realize the average BER of 10-3 due to severe multiple access interference (MAI)). It is also found that the achieved BER performance at the average BER of 10-3 of the COMSIC receiver with the A/D converter quantization of 8 bits in the laboratory experiments is degraded by approximately 1.0 dB and 4.0 dB compared to the computer simulation results, when ΔEb/I0=-6 dB and -9 dB, respectively, due to the quantization error of the desired signal and path search error for the Rake combiner. Finally, we show that the required transmit Eb/N0 at the average BER of 10-3 of the third-stage COMSIC with ICE is decreased by approximately 0.3 and 0.5 dB compared to that of COMSIC with decision-feedback type channel estimation (DFCE) with and without antenna diversity reception, respectively.