An advanced spare-connection scheme for K-out-of-N redundancy is proposed for constructing fault-tolerant ring- or toroidal mesh-connected processing-node arrays able to enhance emulation of binary hypercubes by using bypass networks. With this scheme, a component redundancy configuration for a base array with a fixed number of primary nodes, such as that for 8-node ring or 32-node toroidal mesh, can be constructed by using bypass links with a segmented bus structure to selectively connect the primary nodes to a spare node in parallel. These bypass links are allocated to the primary nodes by graph-node coloring with a minimum inter-node distance of three in order to use the bypass links as the hypercube connections as well as to attain strong fault tolerance for reconfiguring the base array with the primary network topology. An extended redundancy configuration for a large fault-tolerant array can be constructed by connecting the component configurations by using external switches of a hub type provided at the bus nodes of the bypass links. This configuration has a network topology of the parallel star-connections of sub-hypercubes whose diameter is smaller than that of the regular hypercube.

First, we give a graph-theoretic formalization for the spare assignment problems for two cases of reconfiguring NN mesh-connected processor arrays with spares on a diagonal line in the array or two orthogonal lines at the edges of the array. Second, we discuss the problems for minimizing the numbers of "dangerous processors" for the cases. Here, a dangerous processor is a nonfaulty one for which there remains no spare processor to be assigned if it becomes faulty, without modifying the spare assignments to other faulty processors. The problem for the latter case, originally presented by Melhem, has already been discussed and solved by the O(N2) algorithm in [3], but it's procedure is very complicated. Using the above graph-theoretic formalization, we give efficient plain algorithms for minimizing the numbers of dangerous processors by which the problems for both the cases can be solved in O(N) time.

In this paper, we propose the evolutionary algorithm-based reasoning system and its design methodology. In the proposed design methodology, reasoning rules behind the past cases in each task (in each case database) are extracted through genetic algorithms and are expressed as truth tables (we call them 'evolved truth tables'). Circuits for the reasoning systems are synthesized from the evolved truth tables. Parallelism in each task can be embedded directly in the circuits by the hardware implementation of the evolved truth tables, so that the high speed reasoning system with small or acceptable hardware size is achieved. We developed a prototype system using Xilinx Virtex FPGA chips and applied it to the gene boundary reasoning (GBR) and English pronunciation reasoning (EPR), which are very important practical tasks in the genome science and language processing field, respectively. The GBR and the EPR prototype systems are evaluated in terms of the reasoning accuracy, circuit size, and processing speed, and compared with the conventional approaches in the parallel AI and the artificial neural networks. Fault injection experiments are also carried out using the prototype system, and its high fault-tolerance, or graceful degradation against defective circuits that suits to the hardware implementation using wafer scale LSIs is demonstrated.

This paper describes a new architecture-based microprocessor, a dynamically programmable parallel processor (DPPP), that consists of large numbers of simplified ALUs (sALU) as processing blocks. All sALUs are interconnected via a code division multiple-access bus interface that provides complete routing flexibility by establishing connections virtually through code-matching instead of physical wires. This feature is utilized further to achieve high parallelism and fault tolerance. High fault tolerance is realized without the limitations of conventional fabrication-based techniques nor providing spare elements. Another feature of the DPPP is its simple programmability, as it can be configured by compiling numerical formula input using the provided user auto-program interface. A prototype chip based on the proposed architecture has been implemented on a 4.5 mm 4.5 mm chip using 0.6 µm CMOS process.

In this paper we propose a MIN (Multistage Interconnection Network) whose performance in the faulty case degrades as gracefully as possible. We focus on a two-dilated baseline network as a sort of MIN. The link connection pattern in our MIN is determined so that all the available paths established between an input terminal and an output terminal via an identical input of a SE (Switching Element) in some stage will never pass through an identical SE in the next stage. Extra links are useful in improving the performance of the MIN and do not complicate the routing scheme. There is no difference between our MIN and others constructed from a baseline network with regard to numbers of links and cross points in all SEs. The theoretical computation and simulation-based study show that our MIN is superior to others in performance, especially in robustness against concentrated SE faults in an identical stage.

A high assurance on-line recovery technology for a space on-board computer that can be realized using commercial devices is proposed whereby a faulty processor node confirms its normality and then recovers without affecting the other processor nodes in operation. Also, the result of an evaluation test using the breadboard model implementing this technology is reported. Because this technology enables simple and assured recovery of a faulty processor node regardless of its degree of redundancy, it can be applied to various applications, such as a launch vehicle, a satellite, and a reusable launch vehicle. As a result, decreasing the cost of an on-board computer is possible while maintaining its high reliability.

The millimeter wave filter using two whispering-gallery mode dielectric disk resonators is presented in this paper. The coupling coefficients of dual disk resonators and the external Q values of the single resonator excited by a dielectric waveguide are investigated theoretically and experimentally. A 2-stage bandpass filter which is designed at the center frequency of 69.85 GHz with a bandwidth of 500 MHz shows a low-loss property of 1.8 dB insertion loss.

The present paper treats the analysis and design method of the (H)NRD guide and E-plane rectangular waveguide integrated structures on the basis of the transverse resonance technique. The analysis is made by assuming a resonant cavity short-circuited at appropriate reference planes and considering the cavity as a waveguide discontinuity problem in the transverse direction. The resonant lengths are determined from the transverse equivalent circuit, and the scattering parameters are calculated from the lengths. We analyze (H)NRD discontinuities and design two types of HNRD guide to E-plane waveguide transitions and a directional coupler composed of HNRD and E-plane waveguide. The theoretical results are in good agreement with results calculated by an EM-simulator.

Using a point matching method, we have numerically analyzed resonance frequencies and unloaded Q factor of whispering gallery modes in a millimeter wave region that are well known as an intrinsic mode of a dielectric disk resonator. We express field distributions of the resonance modes by a summation of spherical waves. Tangential electromagnetic fields inside the disk are matched to those outside the disk at appropriate matching points on a boundary. As the result, a 4N 4N (N; number of matching points) determinant is derived as an eigenvalue equation of the disk resonator. Since elements of the determinant are complex numbers, a complex angular frequency is introduced to make a value of the determinant zero. For a location of the matching points, we also introduce a new technique which is derived from a field expression of the whispering gallery modes. Since an azimuthal angle dependence of the field distributions with a resonance mode number m is presented by the associated Legendre function Pnm(cos θ), we define abscissas θi of the matching points as solutions of Pm+2N-1m (cos θ) = 0. Considering the field symmetry, we also modify the eigenvalue equation to a new eigenvalue equation which is expressed (4N - 2) (4N - 2) determinant. From the results of our numerical analysis, we can find that the resonance frequencies and unloaded Q factor well converge for number of matching points N. A comparison of numerical results and experimental ones, in a millimeter wave band (50 - 100 GHz), shows a good agreement with each other. It is found that our analysis is effective for practical use in the same wave band.

The efficiency-fractional bandwidth product (EB), which is expressed as a ratio of the radiation resistance to the absolute value of the input reactance of an antenna, is used as a performance criterion for small dielectric loaded monopole antennas (DLMAs). The dependence of the EB on the permittivity of the dielectric loading (i.e., the electrical volume) is experimentally and numerically investigated for the first time in antenna research. As a result, it is found that the EBs of the some DLMAs are enhanced over a bare monopole antenna and an EB characteristic curve has a maximum point. This result suggests the presence of the optimum electrical volume for the dielectric loading in order to obtain the best EB performance. A general reason for the existence of the peak value is also explained using a mathematical deduction. Finally the system EB, which is an efficiency-fractional bandwidth product of the DLMA with a practical matching circuit, is defined and its dependence on the relative permittivity is illustrated. Consequently, the existence of the peak value is also confirmed for the system EBs. In addition, it is demonstrated that the enhancement of the system EB is mainly due to the enhancement in the efficiency of the antenna system.

The effect of Unbalanced-Magnetic-Pull (UMP) on vibration and run-outs has become stringent in the design for high performance HDD spindle motors. In this paper, reducing the UMP and also minimizing its variability for an 8-pole 9-slot spindle motor to achieve robustness in the performance is described and illustrated using novel robust design methods. A screening experiment identifies the key design parameters. Using Design of experiment (DOE) and Analysis of Variance (ANOVA), the parameter design reduces the amplitude of UMP and minimizes its variability by product parameter optimization. The tolerance design improves the quality by tightening tolerances on product or process parameters to reduce the performance variation. The optimal design process includes considerations of manufacturing and process noises, such as manufacturing tolerances for the slot opening and variation of the rotor magnet magnetization distribution due to the magnetization fixture and process. The optimal design procedure is briefly introduced and the results are presented.

Digital signal processors (DSPs) usually employ indirect addressing using address registers (ARs) to indicate their memory addresses, which often introduces overhead codes in AR updates for next memory accesses. Reduction of such overhead code is one of the important issues in automatic generation of highly-efficient DSP codes. In this paper, a new automatic address allocation method incorpolated with computational order rearrangement at local commutative parts is proposed. The method formulates a given memory access sequence by a graph representation, where several strategies to handle freedom in memory access orders at the computational commutative parts are introduced and examined. A compiler scheme is also extended such that computational order at the commutative parts is rearranged according to the derived memory allocation. The proposed methods are applied to an existing DSP compiler for µPD77230(NEC), and codes generated for several examples are compared with memory allocations by the conventional methods.

This letter focuses on the design of a unified estimator for scheduled control in nonlinear systems with unknown parameter. An estimation law with a finite convergence time is formulated to compute the unknown scheduling parameter that drives a scheduled controller. This estimator can also be extended to the types of scheduled controllers addressed in the literature.

In SDMA, a spatial domain interference canceller applying a multistage processing concept to the MMSE multibeam adaptive array has an attractive feature. Weak power signals strongly interfered can be detected in the succeeded stages after removing other strong power signals which are already detected. This idea can be enhanced to the reference timing estimation required in the MMSE algorithm. In this paper, the spatial domain interference canceller introducing multistage timing estimation is proposed and its performance is evaluated by computer simulations. The results show that the timing estimation performance highly improved.

The conventional method of fuzzy control realizes only nonlinear PI (proportional and integral) control actions and does not have the D (derivative) control action required to effectively improve control performance. Hence, the improvement of control performance is limited. Therefore, in this paper, a method for simple improvement of the PI fuzzy control used conventionally is proposed. The method proposed here improves the control performance simply by combining, in parallel, the conventional PI fuzzy controller with the D control action which is realized by using the fuzzy inference method. Then, based on the simulation results for the first- and second-order lag systems with dead time, the effectiveness of the proposed fuzzy control is shown compared with the conventional PI fuzzy control.

In order to make the ATM network fault-tolerant and the network service flexible, a method for the setting up of backup virtual paths (VP's for short) using multiagents is effective with respect to adaptability to change of network resource and user requirements, examples of which are failure of nodes and links and addition of VP's, respectively. In this method, under the assumption that candidates of backup VP's between different pairs of source and destination nodes are given, the optimum backup VP's are obtained by exchanging information among agents autonomously. First, this paper proposes measures for determining backup VP's between different pairs of source and destination nodes. Next, this paper presents simulation results to evaluate the adaptability of the method. The results show that the method efficiently obtains the optimum backup VP's even when the number of backup VP's increases and that different idle time at each destination node enables to shorten the total processing time while keeping complete detection of shared links.

Based on filtering ground clutter power directly in the frequency domain, a new non-coefficient Adaptive MTI (AMTI) scheme is presented in this letter. The results of simulation example show that this scheme has smaller signal-to-noise ratio loss than the classical AMTI based on spectral estimation, as well as high improvement factor.

This paper proposes Photonic Core Node based on a 2.56-Terabit/s opto-electronic switching fabric, which can economically handle the rapidly increasing multimedia traffics, such as Internet traffic. We have successfully developed the first prototype of Photonic Core Node. The prototype consists of a single-stage full-crossbar opto-electronic switching fabric, super-packet buffers for input queuing, and a desynchronized-round-robin scheduler. The switching fabric is upgradable up to 2.56 Tb/s, and employs wavelength-division-multiplexing techniques, which dramatically reduce the total number of optical switching elements down to one-eighth the number of those used in a conventional switching fabric. The super-packet buffer assembles 16 ATM cells routed to the same output port into a single fixed-length packet. The super-packet-switching scheme drastically reduces the overhead of optical switching from 32 to 2.9%, although it tends to decrease effective throughput. The desynchronized-round-robin scheduler maintains nearly 100% effective throughput for random traffic, recursively resolving the contention of connection requests in one scheduling routine while keeping fairness in a round robin manner. The proposed Photonic Core Node can accommodate not only ATM switching but also WDM optical path grooming/multiplexing, and IP routing by using IP input buffer interfaces, because optical switches are bit-rate/format-independent.

This paper proposes Photonic Core Node based on a 2.56-Terabit/s opto-electronic switching fabric, which can economically handle the rapidly increasing multimedia traffics, such as Internet traffic. We have successfully developed the first prototype of Photonic Core Node. The prototype consists of a single-stage full-crossbar opto-electronic switching fabric, super-packet buffers for input queuing, and a desynchronized-round-robin scheduler. The switching fabric is upgradable up to 2.56 Tb/s, and employs wavelength-division-multiplexing techniques, which dramatically reduce the total number of optical switching elements down to one-eighth the number of those used in a conventional switching fabric. The super-packet buffer assembles 16 ATM cells routed to the same output port into a single fixed-length packet. The super-packet-switching scheme drastically reduces the overhead of optical switching from 32 to 2.9%, although it tends to decrease effective throughput. The desynchronized-round-robin scheduler maintains nearly 100% effective throughput for random traffic, recursively resolving the contention of connection requests in one scheduling routine while keeping fairness in a round robin manner. The proposed Photonic Core Node can accommodate not only ATM switching but also WDM optical path grooming/multiplexing, and IP routing by using IP input buffer interfaces, because optical switches are bit-rate/format-independent.

We consider methods for threshold RSA decryption among distributed agencies without any dealer or trusted party. The first solution is a combination of two techniques by [9] and [7] . It demonstrates the feasibility of combining the distributed key generation and the RSA secure function application. The second solution is another approach making the distributed key distribution simpler and alleviating a burden of each shareholder in comparison with the first scheme. The latter scheme is newly developed technique based on [9] and further inspired by Simmons' protocol-failure of RSA (we believe that it is very interesting that a "protocol failure attack" be turned into a constructive method). Our comparison between these two schemes indicates a new measure of the performance of a distributed cryptographic protocol that consists of multiple stages.