Toward the actualization of an automatic navigation system for fetoscopic tracheal occlusion (FETO) surgery, this paper proposes a 3D ultrasound (US) calibration-based approach that can locate the fetal facial surface, oral cavity, and airways by a registration between a 3D fetal model and 3D US images. The proposed approach consists of an offline process and online process. The offline process first reconstructs the 3D fetal model with the anatomies of the oral cavity and airways. Then, a point-based 3D US calibration system based on real-time 3D US images, an electromagnetic (EM) tracking device, and a novel cones' phantom, computes the matrix that transforms the 3D US image space into the world coordinate system. In the online process, by scanning the mother's body with a 3D US probe, 3D US images containing the fetus are obtained. The fetal facial surface extracted from the 3D US images is registered to the 3D fetal model using an ICP-based (iterative closest point) algorithm and the calibration matrices, so that the fetal facial surface as well as the oral cavity and airways are located. The results indicate that the 3D US calibration system achieves an FRE (fiducial registration error) of 1.49±0.44mm and a TRE (target registration error) of 1.81±0.56mm by using 24 fiducial points from two US volumes. A mean TRE of 1.55±0.46 mm is also achieved for measuring location accuracy of the 3D fetal facial surface extracted from 3D US images by 14 target markers, and mean location errors of 2.51±0.47 mm and 3.04±0.59 mm are achieved for indirectly measuring location accuracy of the pharynx and the entrance of the trachea, respectively, which satisfy the requirement of the FETO surgery.

A 7bit 1GS/s flash ADC using two bit active interpolation and background offset calibration is proposed and tested. It achieves background calibration using 36 pre-amplifiers with 139 comparators. To cancel the offset, two pre-amplifiers and 12 comparators are set to offline in turn while the others are operating. A two bit active interpolation design and an offset cancellation scheme are implemented in the latch stage. The interpolation and background calibration significantly reduce analog input signal as well as reference voltage load. Fabricated with the 90nm CMOS process, the proposed ADC consumes 95mW under a 1.2V power supply.

A digital background calibration technique using signal-dependent dithering is proposed, to correct the nonlinear errors which results from capacitor mismatches and finite opamp gain in pipelined analog-to-digital converter (ADC). Large magnitude dithers are used to measure and correct both errors simultaneously in background. In the proposed calibration system, the 2.5-bit capacitor-flip-over multiplying digital-to-analog converter (MDAC) stage is modified for the injection of large magnitude dithering by adding six additional comparators, and thus only three correction parameters in every stage subjected to correction were measured and extracted by a simple calibration algorithm with multibit first stage. Behavioral simulation results show that, using the proposed calibration technique, the signal-to-noise-and-distortion ratio improves from 63.3 to 79.3dB and the spurious-free dynamic range is increased from 63.9 to 96.4dB after calibrating the first two stages, in a 14-bit 100-MS/s pipelined ADC with σ=0.2% capacitor mismatches and 60dB nonideal opamp gain. The time of calibrating the first two stages is around 1.34 seconds for the modeled ADC.

A promising application of a single-flux quantum (SFQ) circuit is read-out circuitry for a multi-channel superconductive sensor array. In such applications, the SFQ read-out circuit is expected to operate outside a magnetic shield. We investigated an SFQ circuit structure, which is tolerant to an external magnetic field, using the AIST 2.5kA/cm2 Nb standard 2 process, which has four Nb wiring layers including the ground plane. By covering the entire circuit using an upper Nb wiring layer called the control (CTL) layer, the influences of the external magnetic field on the SFQ circuit operation can be avoided. We experimentally evaluated the sheet inductance of the wiring layer underneath the CTL shielding layer to design a magnetic-field-tolerant SFQ circuit. We implemented and measured test circuits comprising toggle flip-flops (TFFs) to evaluate their magnetic field tolerances. The operating margin and maximum operating frequency of the designed TFF did not deteriorate with increases in the magnetic field applied to the test circuit, whereas the operating margin of the conventional TFF was reduced by applying the magnetic field. We have also demonstrated the high-speed operation of the designed TFF operated in an unshielded environment at a frequency of up to 120GHz with a wide operating margin.

The second generation digital terrestrial broadcasting system (DVB-T2) is the first broadcasting system employing MISO (Multiple-Input Single-Output) algorithms. The potential MISO gain of this system has been roughly predicted through simulations and field tests. Of course, the potential MISO SFN gain (MISO-SFNG) differs according to the simulation conditions, test methods, and measurement environments. In this paper, network gains of SISO-SFN and MISO-SFN are theoretically derived. Such network gains are also analyzed with respect to the receive power imbalance and coverage distances of SISO and MISO SFN. From the analysis, it is proven that MISO-SFNG is always larger than SISO SFN gain (SISO-SFNG) in terms of the achievable SNR. Further, both MISO-SFNG and SISO-SFNG depend on the power imbalance, but the network gains are constant regardless of the modulation order. Once the field strength of the complete SFN is obtained by coverage planning tools or field measurements, the SFN service coverage can be precisely calibrated by applying the closed-form SFNG formula.

This study investigated the relationship between human use of automation and their sensitivity to changes in automation and manual performance. In the real world, automation and manual performance change dynamically with changes in the environment. However, a few studies investigated whether changes in automation or manual performance have more effect on whether users choose to use automation. We used two types of experimental tracking tasks in which the participants had to select whether to use automation or conduct manual operation while monitoring the variable performance of automation and manual operation. As a result, we found that there is a mutual relationship between human use of automation and their sensitivity to automation and manual performance changes. Also, users do not react equally to both automation and manual performance changes although they use automation adequately.

This paper describes the analysis and design of low-noise analog circuits for a new architecture readout LSI, Qpix. In contrast to conventional readout LSIs using TOT method, Qpix measures deposited charge directly as well as time information. A preamplifier with a two-stage op amp and current-copy output buffers is proposed to realize these functions. This preamplifier is configured to implement a charge sensitive amplifier (CSA) and a trans-impedance amplifier (TIA). Design issues related to CSA are analyzed, which includes gain requirement of the op amp, stability and compensation of the two-stage cascode op amp, noise performance estimation, requirement for the resolution of the ADC and time response. The offset calibration method in the TIA to improve the charge detecting sensitivity is also presented. Also, some design principles for these analog circuits are presented. In order to verify the theoretical analysis, a 400-pixel high speed readout LSI: Qpix v.1 has been designed and fabricated in 180 nm CMOS process. Calculations and SPICE simulations show that the total output noise is about 0.31 mV (rms) at the output of the CSA and the offset voltage is less than 4 mV at the output of the TIA. These are attractive performances for experimental particle detector using Qpix v.1 chip as its readout LSI.

A 6-bit, 7 mW, 700 MS/s subranging ADC using Capacitive DAC (CDAC) and gate-weighted interpolation fabricated in 90 nm CMOS technology is demonstrated. CDACs are used as a reference selection circuit instead of resistive DACs (RDAC) for reducing settling time and power dissipation. A gate-weighted interpolation scheme is also incorporated to the comparators, to reduce the circuit components, power dissipation and mismatch of conversion stages. By virtue of recent technology scaling, an interpolation can be realized in the saturation region with small error. A digital offset calibration technique using capacitor reduces comparator's offset voltage from 10 mV to 1.5 mV per sigma. Experimental results show that the proposed ADC achieves a SNDR of 34 dB with calibration and FoM is 250 fJ/conv., which is very attractive as an embedded IP for low power SoCs.

We study the role of energy conversion in phase regulation of frequency entrainment. For an open dynamical system that interacts with its environment, energy conversion in the system is the key to a wide variety of nonlinear phenomena including frequency entrainment. In this paper, using the standard notion of energy, we study the phenomena of frequency entrainment by periodic forces in two different types of oscillations: libration and rotation. Theoretical analysis shows a relationship between phase regulation and energy conversion in the entrainment phenomena. Both of them are explained as a common phase regulation. On the other hand, no common relationship between transient behaviors and energy conversion is identified for the two different types of oscillations. For libration, the development of frequency entrainment does not depend on the energy conversion. The energy input to the oscillator affects the amplitude of libration. For the rotation, the development of frequency entrainment is governed by the amount of energy conversion. The energy input to the system directly regulates the phase of rotation, in other words, controls the entrainment phenomenon. These results suggest a different dynamical and control origin behind the two types of entrainment phenomena as the energy conversion in the systems.

A method of calibration for GPR responses is introduced in order to extract a target response from GPR data. This calibration procedure eliminates undesirable waveform distortion that is caused by antenna characteristics and multiple scattering effects between the antennas and the ground surface. An application result to measured GPR data shows that undesirable late-time responses caused by the antenna characteristics and multiple scattering effects are removed, and that the target response is clearly reconstructed. This result demonstrates that the waveform calibration of GPR data is significant and essential for reliable target identification.

A 60 GHz direct conversion transceiver which employs amplitude/phase imbalance cancellation technique is newly proposed. By using the proposed technique, the receive path of the transceiver achieves less than 0.2 dB of amplitude error and less than 3 of phase error at 60 GHz bands over a 10 GHz bandwidth, which relaxes the design accuracy required for baluns used in the transceiver. It also employs a simple and fast calibration algorithm to adjust the locking range of the divide-by-3 injection locked divider in the phase locked loop. Fabricated in 90 nm CMOS technology, the transceiver achieves a low power consumption of 230 mW in transmit mode and 173 mW in receive mode. The output spectrum of 1.76 Gsps π/2-BPSK/QPSK modulation shows the excellent distortion and spurious suppression that meet the IEEE802.11ad draft standard.

This paper proposes a cumulative DNL (CDNL) test methodology for the BIST of ADCs. It analyzes the histogram of the DNL of a predetermined k LSBs distance to determine the DNL and gain error. The advantage of this method over others is that the numbers of required code bins and required samples are significantly reduced. The simulation and measurements of a 12-bit ADC show that the proposed CDNL has an error of less than 5% with only 212 samples, which can only be achieved with 222 samples using the conventional method. It only needs 16 registers to store code bins in this experiment.

The need for the OpenGL-family of the 3D rendering API's are highly increasing, especially for graphical human-machine interfaces on various systems. In the case of safety-critical market for avionics, military, medical and automotive applications, OpenGL SC, the safety critical profile of the OpenGL standard plays the major role for graphical interfaces. In this paper, we present an efficient way of implementing OpenGL SC 3D graphics API for the environments with hardware-supported OpenGL 1.1 and its multi-texture extension facility, which is widely available on recent embedded systems. Our approach achieved the OpenGL SC features at the low development cost on the embedded systems and also on general personal computers. Our final result shows its compliance with the OpenGL SC standard specification. From the efficiency point of view, we measured its execution times for various application programs, to show a remarkable speed-up.

This paper describes latest RF Automated Test Equipment (RF ATE) technologies that include device under test (DUT) connections, a calibration method, and an RF test module mainly focusing on low cost of test (COT). Most important respect for low COT is how achieve a number of simultaneous measurements and short test time as well as a plain calibration. We realized these respects by a newly proposed calibration method and a drastically downsized RF test module with multiple resources and high throughput. The calibration method is very convenient for RF ATE. Major contribution for downsizing of the RF test module is RF circuit technology in form of RF functional system in package (RF-SIPs), resulting in very attractive test solutions.

A 4th-order programmable continuous-time filter (CTF) for hard-disk-drive (HDD) read channels was developed with 65-nm CMOS process technology. The CTF cutoff frequency and boost are programmable by switching units of the operational trans-conductance amplifier (OTA) banks and the capacitor banks. The switches are operated by lifted local-supply voltage to reduce on-resistance of the transistors. The CTF characteristics were robust against process technology variations and supply voltage and temperature ranges due to the introduction of a digitally assisted compensation scheme with analog auto-tuning circuits and digital calibration sequences. The digital calibration sequences, which fit into the operation sequence of the HDD read channel, compensate for the tuning circuits of the process technology variations, and the tuning circuits compensate for the CTF characteristics over the supply voltage and temperature ranges. As a result, the CTF had a programmability of 100–1000-MHz cutoff frequency and 0–12-dB boost.

The performance of successive approximation register (SAR) analog-to-digital converter (ADC) is well balanced between power and speed compare to the conventional flash or pipeline architecture. The nonlinearities suffer from the CDAC mismatch and comparator offset degrades SAR ADC performance in terms of DNL and INL. An on chip histogram-based digitally assisted background calibration technique is proposed to cancel and relax the aforesaid nonlinearities. The calibration is performed using the input signal, watching the digital codes in the specified vicinity of the decision boundaries, and feeding back to control the compensation capacitor periodically. The calibration does not require special calibration signal or additional analog hardware which is simple and amenable to hardware or software implementations. A 9-bit SAR ADC with split CDAC has been implemented in a 65 nm CMOS technology and it achieves a peak SNDR of 50.81 dB and consumes 1.34 mW from a 1.2-V supply. +0.4/-0.4 LSB DNL and +0.5/-0.7 LSB INL are achieved after calibration. The ADC has input capacitance of 180 fF and occupies an area of 0.10.13 mm2.

We have proposed a novel geometric model of the eye in order to avoid the problems faced while using the conventional spherical model of the cornea for three dimensional (3D) model-based gaze estimation. The proposed model models the eye, including the boundary region of the cornea, as a general surface of revolution about the optical axis of the eye. Furthermore, a method for calculating the point of gaze (POG) on the basis of our model has been proposed. A prototype system for estimating the POG was developed using this method. The average root mean square errors (RMSEs) of the proposed method were experimentally found to be smaller than those of the gaze estimation method that is based on a spherical model of the cornea.

Along with the miniaturization of CMOS-LSIs, control methods for LSIs have been extensively developed. The most predominant method is to digitize observed values as early as possible and to use digital control. Thus, many types of analog-to-digital converters (ADCs) have been developed such as temperature, time, delay, and frequency converters. ADCs are the easiest circuits into which digital correction methods can be introduced because their outputs are digital. Various types of calibration method have been developed, which has markedly improved the figure of merits by alleviating margins for device variations. The above calibration and correction methods not only overcome a circuit's weak points but also give us the chance to develop quite new circuit topologies and systems. In this paper, several digital calibration and correction methods for major analog-to-digital converters are described, such as pipelined ADCs, delta-sigma ADCs, and successive approximation ADCs.

This paper analyzes a pseudo-differential dynamic comparator with a dynamic pre-amplifier. The transient gain of a dynamic pre-amplifier is derived and applied to equations of the thermal noise and the regeneration time of a comparator. This analysis enhances understanding of the roles of transistor's parameters in pre-amplifier's gain. Based on the calculated gain, two calibration methods are also analyzed. One is calibration of a load capacitance and the other is calibration of a bypass current. The analysis helps designers' estimation for the accuracy of calibration, dead-zone of a comparator with a calibration circuit, and the influence of PVT variation. The analyzed comparator uses 90-nm CMOS technology as an example and each estimation is compared with simulation results.

The probe used in the conventional SAR measurement is usually calibrated in a well filled with tissue-equivalent liquid surrounded by a rectangular waveguide and a matching dielectric window in the frequency range from 800 MHz to 3 GHz. However, below 800 MHz, the waveguides are too large to be used for the calibration. Therefore, we have developed another technique of calibrating the SAR-probe, that is, relating the output voltage of the probe to the field intensity produced by a reference antenna in the tissue-equivalent liquid by using two-antenna method. In this paper, the calibration system using the reference dipole antennas in the liquid at 450 MHz, 900 MHz and 2450 MHz is presented and far-field gain of the reference antenna and calibration factor of the SAR-probe are measured and compared with those obtained by using the conventional waveguide system.