The transmission S-parameter, S21, between dipole elements on a rectangular finite ground plane is calculated by the MoM with planar-segments in the horizontally and vertically polarized configurations. Supposed a 1/10 scaling, the frequency range is selected 0.15-0.8 GHz. The size of the finite ground plane is 40 cm 100 cm. The dipole-element length is 18.8 cm (half-wavelength at 0.8 GHz). The distance between dipole elements is 30 cm. The results are compared to the calculated results with the conventional MoM-GTD hybrid method and also the measured results with a TRL-calibrated network analyzer. It makes clear that the MoM-GTD hybrid method is not applicable to a small ground plane in the vertically polarized configuration. The results calculated by the MoM with planar-segments agree well to the measured results both in the horizontal and vertical polarizations. The results show that the size of the finite ground plane for the vertical polarization should be much larger than for the horizontal polarization.

A history of the English IEICE Transactions from the beginning is stated through the eyes of the person who has been involved in promoting the Transactions, by a description of why and how it has actually been reformed. The purpose and significance of the English IEICE Transactions, especially of the IEICE Trans. Fundamentals, are clarified.

High-speed systems require a wide-frequency-range clock system for data processing. Phase-locked loop (PLL) is used for such a system that requires wide-range variable frequency clock. Frequency calibration method enables the voltage-controlled oscillator (VCO) in a PLL to cover the expected frequency range for high-speed applications that require a wide locking range. Frequency range adjustment is implemented by means of a current digital to analog converter (DAC), which controls the performance curves of a VCO and a bias circuit. This method adjusts the VCO's frequency-voltage performance curves before functional operation so that a PLL can cover requested frequency range with its best condition. Both the limit of control voltage and its target reference voltage are given with same voltage reference. This ensures correct performance after frequency adjustment even under the temperature fluctuation. It eliminates post-production physical adjustment such as fuse trimming which increases the cost and TAT in manufacturing and testing. A high-speed wide-locking range VCO with an automatic frequency performance calibration circuit is implemented within small space in a high-speed hard disk drive channel with 0.25-µm 2.5 V CMOS four-layer metal technology.

The transmission S-parameter between two dipole-elements is a measure to evaluate sites for measuring complex antenna factors (CAF). In this paper, the S-parameter between two dipole-elements on a ground plane is measured using a network analyzer with its TRL (Thru-Reflect-Line) calibration. The S-parameter is also calculated by the method of moment (MoM) and compared to the measurement results. The comparison shows that the calculated S-parameter is usable as a reference value in the evaluation of CAF measurement sites. As an example of the evaluation and selection of measurement sites, the transmission S-parameter on a finite ground plane is calculated using the hybrid method combined the geometrical theory of diffraction (GTD) and MoM. As a result, a preferable antenna setting on the finite ground plane is recommended.

Program slicing is a technique for statically analyzing a program and extracting an executable sub-program, which is called a program slice, from the original program. This technique has been widely applied to program testing, debugging and maintenance. This paper presents a slicing method for extracting program slices from a program that calls library functions, which are provided as object code. The method this paper presents analyzes dependence relationships between library functions using global data that are referred to by the library functions but not explicitly declared in a program. In this method, before slicing a program with respect to a slicing criterion, a Def-Slice-Use table will be generated that stores slice information for each function in the program by slicing these functions in advance, and then the program can be efficiently sliced using this table. The paper also illustrates some examples of program slicing using a program slicer LibSlicer that implements this method.

We present a simulation system which meets the requirements for practical application of inverse modeling in a professional environment. A tool interface for the integration of arbitrary simulation tools at the user level is introduced and a methodology for the formation of simulation networks is described. A Levenberg-Marquardt optimizer automates the inverse modeling procedure. Strategies for the efficient execution of simulation tools are discussed. An example demonstrates the extraction of doping profile information on the basis of electrical measurements.

As scaling has been continued more than 20 years, it has yielded faster and denser chips with ever increasing functionality. The scaling will continue down to or beyond 0.1 µm as proposed in SIA Technical Road map. With scaling, device performance improves, however, interconnect performance is degraded. In this scaled deep submicron technology, however, interconnects limit the performance, packing density and yield, if not properly modeled. In order to properly model and design the interconnect-dominated circuits, accurate and proper interconnect modeling is a must to assure the performance and functionality of ever-increasing complex multi-million transistor VLSI circuits. In this paper, the overall flow of interconnect modeling in IC design is reviewed including interconnect characterization, various 2-D/3-D field solvers, 2-D/3-D interconnect model library generation, and parameter extraction. And advanced topics of interconnect modeling in deep submicron are reviewed; statistical interconnect modeling.

In MPU and ASIC design with 0.2 µm BiCMOS LSIs, it is well known that interconnect delay becomes one of the key data to ensure high operating frequency. To verify the whole path delay accurately, one needs to create huge delay and waveform libraries which reflect updated process and interconnect structure as well as device performance. Because of the necessity for more than 100 k times of circuit simulation to create the libraries, it was impossible to update the library quickly including process variation effects. In this paper, we have proposed a realistic new method to generate the libraries on the basis of RSM (Response Surface Method). In application for a BiCMOS ASIC process, we have verified that the new method has achieved the reduction of library creation time to 1/100 within the delay error of 3%. This technique can be used in our TCAD and DA framework, which gives a predictive TCAD generation of delay libraries in concurrent ASIC system and process development.

In this paper we deal with the problem of calibrating a rotating and zooming camera, without 3D pattern, whose internal calibration parameters change frame by frame. First, we theoretically show the existence of the calibration parameters up to an orthogonal transformation under the assumption that the skew of the camera is zero. Auto-calibration becomes possible by analyzing inter-image homographies which can be obtained from the matches in images of the same scene, or through direct nonlinear iteration. In general, at least four homographies are needed for auto-calibration. When we further assume that the aspect ratio is known and the principal point is fixed during the sequence then one homography yields camera parameters, and when the aspect ratio is assumed to be unknown with fixed principal point then two homographies are enough. In the case of a fixed principal point, we suggest a method for obtaining the calibration parameters by searching the space of the principal point. If this is not the case, then nonlinear iteration is applied. The algorithm is implemented and validated on several sets of synthetic data. Also experimental results for real images are given.

In this work, a CMOS on-chip current reference circuit for memory, operational amplifiers, comparators, and data converters is proposed. The reference current is nearly insensitive to temperature and supply-voltage variations. In the proposed circuit, the current component with a positive temperature coefficient cancels that with a negative temperature coefficient each other. While conventional current reference circuits are based on bipolar transistors in BiCMOS, bipolar, or CMOS processes, the proposed circuit can be integrated on a single chip with other digital and analog circuits using a standard CMOS process and extra masks are not required. Measured results are demonstrated for two different prototypes. The first is fabricated employing a 1.0 µm p-well double-poly double-metal CMOS process and operates at 5 V nominally. The second, based on a 0.6 µm n-well process, is optimized for 3 V to 5 V operation. The latter prototype achieves the temperature coefficient of 98 ppm/ over a temperature range from -25 to 75 and the output variation of 1.5% with the supply-voltage changes from 2.5 V to 5.5 V. A simple calibration technique for reducing output current variations improves circuit yield.

In many applications of digital video database systems such as digital library, video data is often compressed with MPEG video algorithms. It will be an important technique to insert the additional information data like indexes and contents effectively into video database which is compressed with MPEG, because we can always deal with the additional information with video data itself easily. We propose a method for inserting optional binary data such as index information of digital library into MPEG-1 and -2 bitstreams. The binary data inserted MPEG video bitstreams using our proposed scheme are also according to the specification of the MPEG video frame structure. The proposed method allows us to extract the inserted binary data perfectly though MPEG-1 and -2 video are lossy algorithms. And the quality of decoded images after extracting added information is almost the same as that of ordinary MPEG bitstreams. Furthermore, traditional standard MPEG-1 and -2 video decoder which can not extract inserted binary data can also decode images from the binary data inserted MPEG video bitstreams without obvious image degradation. There are some different points between the proposed insertion technique of the binary data and the watermarking technique. The technique of watermarking prepares to deal with alter watermarking by others. And the technique of watermarking is required for the identification of the signature and the perfect extraction of the inserted image signature is not required in the lossy MPEG video environment. On the other hand, we have to extract all of the inserted binary information data correctly with the insertion technique of the binary information. Simulations using MPEG video sequences with inserted binary data are presented to quantify some performance factors concerned. We have not heard about inserting data method which purpose is such as index and content information insertion.

TCAD (Technology Computer Aided Design) is the simulation of semiconductor processes and devices. Despite twenty years of development, there are still many TCAD skeptics. This paper will discuss some of the problems and limitations of TCAD, present some successful examples of its use, and discuss future simulation needs from a user's perspective. A key point is that the time pressures in modern semiconductor technology development often dictate the use of simple models for approximate results.

DC offset causes performance degradation in signal processing systems especially for high-speed applications. A new offset cancellation method that relaxes the requirement for the offset of the circuit components in the differential analog data path to about 10 times larger is introduced. This method moves the adjusting target from analog-to-digital converter (ADC) to its input buffer and adjusts DC level of ADC input to its center before the final offset cancellation. It eliminates post-production adjustment such as fuse trimming, which increases the cost and TAT in manufacturing and testing. Execution and simulation times are shortened down to 1/9 for less settling time in buffer and with improved logic. An automatic quick offset calibration circuit is implemented in a small silicon space in a high-speed hard disk drive (HDD) channel with 0.25-µm four-layer metal CMOS process. The measured data show this method works effectively in this system.

We investigated a radio interferometer for geodetic use that incorporates commercially available fiber-optic links modulated in the radio-frequency range, and a method for compensating for the delay occurring in the links. With this type of radio interferometer, we can perform baseline analysis without the need for estimating the clock difference between observation stations, which causes a relatively large error in the vertical component of the estimated position of the station. Another advantage of the interferometer is utilization of phase delay, which improves the accuracy of delay determination considerably. By analyzing the interferometer's signal-to-noise ratio, we estimated the practicable cable length to be 58.0 km. The results of preliminary experiments with short optical fiber links show that the differences in the cable delays of the fiber-optic links can be compensated for by calibration signals which make a round trip between the analysis station and the observation sites, and that phase delay can be measured successfully.

This paper reviews recent developments in small-sized broadband antennas for EMI measurements, especially in the microwave frequency region. Transient EMI measurements are also discussed by introducing complex antenna factors and conversion of frequency-domain data into time-domain data. This paper also focuses on considerable improvements achieved in calibration techniques for conventional EMI antennas in VHF/UHF bands.

A radio propagation experiment at the Okinawa Radio Observatory of the Communications Research Laboratory is investigating the feasibility of calibrating the spaceborne precipitation radar onboard the Tropical Rainfall Measuring Mission by using the path-averaged rainfall rate estimated from rain attenuation. Because this estimated rainfall rate has errors due to the spatial inhomogeneity of rainfall rate and the variability of raindrop size distribution, we used distrometer data to evaluate both of these errors by computer simulation.

In this paper, we propose a camera calibration method that estimates both intrinsic parameters (perspective and distortion) and extrinsic parameters (rotational and translational). All camera parameters can be determined from one or more images of planar pattern consists of parallelogramatic grid points. As far as the pattern can be visible, the relative relations between camera and patterns are arbitrary. So, we have only to prepare a pattern, and take one or more images changing the relative relation between camera and the pattern, arbitrarily; neither solid object of ground truth nor precise z-stage are required. Moreover, constraint conditions that are imposed on rotational parameters are explicitly satisfied; no intermediate parameter that connected several actual camera parameters are used. Taking account of the conflicting fact that the amount of distortion is small in the neighborhood of the image center, and that small image has poor clues of 3-D information, we adopt iterative procedure. The best parameters are searched changing the size and number of parallelograms selected from grid points. The procedure of the iteration is as follows: The perspective parameters are estimated from the shape of parallelogram by nonlinear optimizations. The rotational parameters are calculated from the shape of parallelogram. The translational parameters are estimated from the size of parallelogram by least squares method. Then, the distortion parameters are estimated using all grid points by least squares method. The computer simulation demonstrates the efficiency of the proposed method. And the results of the implementation using real images are also shown.

A calibrating analog-to digital (A/D) converter employing a T-Model neural network is described. The T-Model neural-based A/D converter architecure is presented with particular emphasis on the elimination of local minimum of the Hopfield neural network. Furthermore, a teacher forcing algorithm is presented and used to synthesize the A/D converter and correct errors of the converter due to offset and device mismatch. An experimental A/D converter using standard 5-µm CMOS discrete IC circuits demonstrates high-performance analog-to-digital conversion and calibrating.

In VLSI or PCB layout, one often encounters a region that is either of rectilinear shape or can be approximated by a rectilinear region. Although many placement methods have been proposed, most of them are applicable only to rectangular regions. For these algorithms to be applied to a rectilinear region, two processing steps, region partitioning and rectangular region cell placement are necessary. Hence, the placement results are so far dependent on the locations of the regions partitioned and frequently become trapped in local minima. Recently, neural networks have been suggested as a new way to resolve the cell placement problem. This paper proposed a unified modeling method that uses a neural net model with additional calibration nodes to model rectilinear region cell placement. In this method, the ideal distance between cells is preserved to simultaneously minimize both the total wire length and the module overlap. Unlike traditional approaches, the proposed algorithm requires only a single processing step. Experiments have been conducted to verify the performance of the proposed algorithm. The total wire length obtained by our method is shorter than those generated by previous methods.

Standard Site Method (SSM) is theoretically analyzed using matrix representations to examine its validity and develop an improved method. The analysis reveals that the SSM yields an antenna factor specifically related to the effective load impedance presented by the cable and associated devices which are disconnected from the antenna during the SSM site attenuation measurements. Therefore, an additional conversion is required to determine the desired antenna factor under actual load conditions. It is also concluded that the SSM is not applicable to antennas having height-dependent antenna factors. In addition, the SSM correction factors are found to be theoretically inappropriate. Uncertainty of the antenna factor obtained using the SSM is discussed and the required antenna separation distance is investigated. To improve the existing SSM, it is proposed that both transmitting and receiving antennas are placed at the same height during the site attenuation measurements. Experiments exhibit the superiority of the improved method.