Fully integrated CMOS power amplifiers (PAs) with a two-winding and single-winding combined transformer (TS transformer) are presented. The general analysis of the TS transformer and other power-combining transformers, i.e., the series-combining transformer and parallel-combining transformer, is presented in terms of the transformer design parameters. Compared with other power-combining transformers, the proposed power-combining TS transformer offers high-efficiency with a compact form factor. In addition, a fully integrated CMOS PA using the TS transformer with multi-gated transistors (MGTRs) and adaptive bias circuit has been proposed to improve linearity. The proposed PAs are implemented using 65-nm CMOS technology. The implemented PA with the TS transformer achieves a saturated output power of 26.7 dBm with drain efficiency (DE) of 47.7%. The PA achieves 20.13-dBm output power with 21.4% DE while satisfying the -25-dB error vector magnitude (EVM) requirement when tested with the WLAN 802.11g signal. The implemented PA using the TS transformer with MGTRs and adaptive bias circuit achieves the -30-dB EVM requirement up to an output power of 17.13 dBm with 10.43% DE when tested using the WLAN 802.11ac signal.

Malware has become a growing threat as malware writers have learned that signature-based detectors can be easily evaded by packing the malware. Packing is a major challenge to malware analysis. The generic unpacking approach is the major solution to the threat of packed malware, and it is based on the intrinsic nature of the execution of packed executables. That is, the original code should be extracted in memory and get executed at run-time. The existing generic unpacking approaches need a simulated environment to monitor the executing of the packed executables. Unfortunately, the simulated environment is easily detected by the environment-sensitive packers. It makes the existing generic unpacking approaches easily evaded by the packer. In this paper, we propose a novel unpacking approach, BareUnpack, to monitor the execution of the packed executables on the bare-metal operating system, and then extracts the hidden code of the executable. BareUnpack does not need any simulated environment (debugger, emulator or VM), and it works on the bare-metal operating system directly. Our experimental results show that BareUnpack can resist the environment-sensitive packers, and improve the unpacking effectiveness, which outperforms other existing unpacking approaches.

A parallel phrase matching (PM) engine for dictionary compression is presented. Hardware based parallel chaining hash can eliminate erroneous PM results raised by hash collision; while newly-designed storage architecture holding PM results solved the data dependency issue; Thus, the average compression speed is increased by 53%.

In this paper, we investigate how to obtain binary locally repairable codes (LRCs) with good locality and availability from binary Simplex codes. We first propose a Combination code having the generator matrix with all the columns of positive weights less than or equal to a given value. Such a code can be also obtained by puncturing all the columns of weights larger than a given value from a binary Simplex Code. We call by block-puncturing such puncturing method. Furthermore, we suggest a heuristic puncturing method, called subblock-puncturing, that punctures a few more columns of the largest weight from the Combination code. We determine the minimum distance, locality, availability, joint information locality, joint information availability of Combination codes in closed-form. We also demonstrate the optimality of the proposed codes with certain choices of parameters in terms of some well-known bounds.

In terms of spatial online aggregation, traditional stand-alone serial methods gradually become limited. Although parallel computing is widely studied nowadays, there scarcely has research conducted on the index-based parallel online aggregation methods, specifically for spatial data. In this letter, a parallel multilevel indexing method is proposed to accelerate spatial online aggregation analyses, which contains two steps. In the first step, a parallel aR tree index is built to accelerate aggregate query locally. In the second step, a multilevel sampling data pyramid structure is built based on the parallel aR tree index, which contribute to the concurrent returned query results with certain confidence degree. Experimental and analytical results verify that the methods are capable of handling billion-scale data.

This letter proposes a novel speech enhancement system based on the ‘L’ shaped triple-microphone. The modified coherence-based algorithm and the first-order differential beamforming are combined to filter the spatial distributed noise. The experimental results reveal that the proposed algorithm achieves significant performance in spatial filtering under different noise scenarios.

In real-time 3D ball tracking of sports analysis in computer vision technology, complex algorithms which assure the accuracy could be time-consuming. Particle filter based algorithm has a large potential to accelerate since the algorithm between particles has the chance to be paralleled in heterogeneous CPU-GPU platform. Still, with the target multi-view 3D ball tracking algorithm, challenges exist: 1) serial flowchart for each step in the algorithm; 2) repeated processing for multiple views' processing; 3) the low degree of parallelism in reweight and resampling steps for sequential processing. On the CPU-GPU platform, this paper proposes the double stream system flow, the view priority based threads allocation, and the binary search oriented reweight. Double stream system flow assigns tasks which there is no data dependency exists into different streams for each frame processing to achieve parallelism in system structure level. View priority based threads allocation manipulates threads in multi-view observation task. Threads number is view number multiplied by particles number, and with view priority assigning, which could help both memory accessing and computing achieving parallelism. Binary search oriented reweight reduces the time complexity by avoiding to generate cumulative distribution function and uses an unordered array to implement a binary search. The experiment is based on videos which record the final game of an official volleyball match (2014 Inter-High School Games of Men's Volleyball held in Tokyo Metropolitan Gymnasium in Aug. 2014) and the test sequences are taken by multiple-view system which is made of 4 cameras locating at the four corners of the court. The success rate achieves 99.23% which is the same as target algorithm while the time consumption has been accelerated from 75.1ms/frame in CPU environment to 3.05ms/frame in the proposed system which is 24.62 times speed up, also, it achieves 2.33 times speedup compared with basic GPU implemented work.

We propose a new context-adaptive arithmetic coding (CAAC) scheme for lossless bit rate reduction of parametric stereo (PS) in enhanced aacPlus. Based on the probability analysis of stereo parameters indexes in PS, we propose a stereo band-dependent CAAC scheme for PS. We also propose a new coding structure of the scheme which is simple but effective. The proposed scheme has normal and memory-reduced versions, which are superior to the original and conventional schemes and guarantees significant bit rate reduction of PS. The proposed scheme can be an alternative to the original PS coding scheme at low bit rate, where coding efficiency is very important.

We propose waveguide to microstrip line transitions for automotive millimeter wave radar modules. The transitions perpendicularly connect one waveguide and one or two microstrip lines. The configuration is simple because it consists of a waveguide and a dielectric substrate with copper foils. Additionally the transitions do not need via holes on the substrate. It leads to lower costs and improved reliability. We have already proposed a via-less transition by using multi-stage impedance transformers. The impedance transformers are used for suppressing undesirable radiation from the transition as well as impedance matching. In this paper, we propose a new transition with the microstrip lines on the long axis of the waveguide while most transitions place the microstrip lines on the minor axis (electric field direction) of the waveguide. Though our transition uses bend structures of microstrip lines, which basically cause radiation, our optimized configuration can keep small radiation. We also design a transition with a single microstrip line. The proposed transition with 2 microstrip lines can be modified to the 1 microstrip line version with minimum radiation loss. Electromagnetic simulations confirm the small radiation levels expected. Additionally we fabricate the transitions with back to back structure and determine the transmission and radiation performance. We also fabricates the transition for a patch array antenna. We confirm that the undesirable radiation from the proposed transition is small and the radiation pattern of the array antenna is not worsen by the transition.

Several types of capacitive crosstalk avoidance codes have been devised in order to prevent capacitive crosstalk in on-chip buses. These codes are designed to prohibit transition patterns prone to capacitive crosstalk from any two consecutive words transmitted to on-chip buses. The present paper provides a rigorous analysis of the asymptotic rate for (p,q)-transition free word sequences under the assumption that coding is based on a stateful encoder and a stateless decoder. Here, p and q represent k-bit transition patterns that should not appear in any two consecutive words at the same adjacent k-bit positions. The maximum rate for the sequences is proven to be equal to the subgraph domatic number of the (p,q)-transition free graph. Based on the theoretical results for the subgraph domatic partition problem, lower and upper bounds on the asymptotic rate are derived. We also show that the asymptotic rate 0.8325 is achievable for p=01 and q=10 transition free word sequences.

In this study, spatially coupled low-density parity-check (SC-LDPC) codes on the two-dimensional array erasure (2DAE) channel are devised, including a method for generating new SC-LDPC codes with a restriction on the check node constraint. A density evolution analysis confirms the improvement in the threshold of the proposed two-dimensional SC-LDPC code ensembles over the one-dimensional SC-LDPC code ensembles. We show that the BP threshold of the proposed codes can approach the corresponding maximum a posteriori (MAP) threshold of the original residual graph on the 2DAE channel. Moreover, we show that the rates of the residual graph of the two-dimensional LDPC block code ensemble are smaller than those of the one-dimensional LDPC block code ensemble. In other words, a high performance can be obtained by choosing the two-dimensional SC-LDPC codes.

Locally repairable codes, which can repair erased symbols from other symbols, have attracted a good deal of attention in recent years because its local repair property is effective on distributed storage systems. (ru, δu)u∈[s]-locally repairable codes with multiple localities, which are an extension of ordinary locally repairable codes, can repair δu-1 erased symbols simultaneously from a set consisting of at most ru symbols. An upper bound on the minimum distance of these codes and a construction method of optimal codes, attaining this bound with equality, were given by Chen, Hao, and Xia. In this paper, we discuss the parameter restrictions of the existing construction, and we propose explicit constructions of optimal codes with multiple localities with relaxed restrictions based on the encoding polynomial introduced by Tamo and Barg. The proposed construction can design a code whose minimum distance is unrealizable by the existing construction.

Racetrack memory (RM) has attracted much attention. In RM, insertion and deletion (ID) errors occur as a result of an unstable reading process and are called position errors. In this paper, we first define a probabilistic channel model of ID errors in RM with multiple read-heads (RHs). Then, we propose a joint iterative decoding algorithm for spatially coupled low-density parity-check (SC-LDPC) codes over such a channel. We investigate the asymptotic behaviors of SC-LDPC codes under the proposed decoding algorithm using density evolution (DE). With DE, we reveal the relationship between the number of RHs and achievable information rates, along with the iterative decoding thresholds. The results show that increasing the number of RHs provides higher decoding performances, although the proposed decoding algorithm requires each codeword bit to be read only once regardless of the number of RHs. Moreover, we show the performance improvement produced by adjusting the order of the SC-LDPC codeword bits in RM.

In multilevel flash memory, in general, multiple read thresholds are required to read a single logical page. Random I/O (RIO) code, introduced by Sharon and Alrod, is a coding scheme that enables the reading of one logical page using a single read threshold. It was shown that the construction of RIO codes is equivalent to the construction of write-once memory (WOM) codes. Yaakobi and Motwani proposed a family of RIO codes, called parallel RIO (P-RIO) code, in which all logical pages are encoded in parallel. In this paper, we utilize coset coding with Hamming codes in order to construct P-RIO codes. Coset coding is a technique to construct WOM codes using linear binary codes. We leverage information on the data of all pages to encode each page. Our P-RIO codes, using which more pages can be stored than RIO codes constructed via coset coding, have parameters for which RIO codes do not exist.

Recent years have seen increasing efforts to improve the input/output performance of multilevel flash memory. In this regard, we propose a coding scheme for two-page unrestricted-rate parallel random input-output (P-RIO) code, which enables different code rates to be used for each page of multilevel memory. On the second page, the set of cell-state vectors for each message consists of two complementary vectors with length n. There are a total of 2n-1 sets that are disjoint to guarantee that they are uniquely decodable for 2n-1 messages. On the first page, the set of cell-state vectors for each message consists of all weight-u vectors with their non-zero elements restricted to the same (2u-1) positions, where the non-negative integer u is less than or equal to half of the code length. Finding cell-state vector sets such that they are disjoint on the first page is equivalent to the construction of constant-weight codes, and the number of disjoint sets is the best-known number of code words in the constant-weight codes. Our coding scheme is constructive, and the code length is arbitrary. The sum rates of our proposed codes are higher than those of previous work.

Spatially “Mt. Fuji” coupled (SFC) low density parity check (LDPC) codes are constructed as a chain of block LDPC codes. A difference between the SFC-LDPC codes and the original spatially coupled (SC) LDPC codes is code lengths of the underlying block LDPC codes. The code length of the block LDPC code at the middle of the chain is larger than that at the end of the chain. It is experimentally confirmed that the bit error probability in the error floor region of the SFC-LDPC code is lower than that of the SC-LDPC code whose code length and design rate are the same as those of the SFC-LDPC code. In this letter, we calculate the weight distribution of the SFC-LDPC code and try to explain causes of the low bit error rates of the SFC-LDPC code.

We propose an approach to allocate bandwidth for a satellite communications (SATCOM) system that includes the recent high-throughput satellite (HTS) with frequency flexibility. To efficiently operate the system, we manage the limited bandwidth resources available for SATCOM by employing a control method that allows the allocated bandwidths to exceed the communication demand of user terminals per HTS beam. To this end, we consider bandwidth allocation for SATCOM as an optimal control problem. Then, assuming that the model of communication requests is available, we propose an optimal control method by combining model predictive control and sparse optimization. The resulting control method enables the efficient use of the limited bandwidth and reduces the bandwidth loss and number of control actions for the HTS compared to a setup with conventional frequency allocation and no frequency flexibility. Furthermore, the proposed method allows to allocate bandwidth depending on various control objectives and beam priorities by tuning the corresponding weighting matrices. These findings were verified through numerical simulations by using a simple time variation model of the communication requests and predicted aircraft communication demand obtained from the analysis of actual flight tracking data.

The order/degree problem consists of finding the smallest diameter graph for a given order and degree. Such a graph is beneficial for designing low-latency networks with high performance for massively parallel computers. The average shortest path length (ASPL) of a graph has an influence on latency. In this paper, we propose a novel order adjustment approach. In the proposed approach, we search for Cayley graphs of the given degree that are close to the given order. We then adjust the order of the best Cayley graph to meet the given order. For some order and degree pairs, we explain how to derive the smallest known graphs from the Graph Golf 2016 and 2017 competitions.

Indoor fingerprint location based on WiFi in large-scale indoor parking lots is more and more widely employed for vehicle lookup. However, the challenge is to ensure the location functionality because of the particularity and complexities of the indoor parking lot environment. To reduce the need to deploy of reference points (RPs) and the offline sampling workload, a partition-fitting fingerprint algorithm (P-FP) is proposed. To improve the location accuracy of the target, the PS-FP algorithm, a sampling importance resampling (SIR) particle filter with threshold based on P-FP, is further proposed. Firstly, the entire indoor parking lot is partitioned and the environmental coefficients of each partitioned section are gained by using the polynomial fitting model. To improve the quality of the offline fingerprint database, an error characteristic matrix is established using the difference between the fitting values and the actual measured values. Thus, the virtual RPs are deployed and C-means clustering is utilized to reduce the amount of online computation. To decrease the fluctuation of location coordinates, the SIR particle filter with a threshold setting is adopted to optimize the location coordinates. Finally, the optimal threshold value is obtained by comparing the mean location error. Test results demonstrated that PS-FP could achieve high location accuracy with few RPs and the mean location error is only about 0.7m. The cumulative distribution function (CDF) show that, using PS-FP, 98% of location errors are within 2m. Compared with the weighted K-nearest neighbors (WKNN) algorithm, the location accuracy by PS-FP exhibit an 84% improvement.

This study proposes a multiple-output differential-input operational transconductance amplifier-C (MODI OTA-C) filter with an impedance scaler to detect cardiac activity. A ladder-type fifth-orderButterworth low-pass filter with a large time constant and low noise is implemented to reduce coefficient sensitivity and address signal distortion. Moreover, linearized MODI OTA structures with reduced transconductance and impedance scaler circuits for noise reduction are used to achieve a wide dynamic range (DR). The OTA-based circuit is operated in the subthreshold region at a supply voltage of 1 V to reduce the power consumption of the wearable device in long-term use. Experimental results of the filter with a bandwidth of 250 Hz reveal that DR is 57.6 dB, and the harmonic distortion components are below -59 dB. The power consumption of the filter, which is fabricated through a TSMC 0.18 µm CMOS process, is lower than 390 nW, and the active area is 0.135 mm2.