Two types of CPW-fed active antenna for television receivers, printed on thin dielectric film, are analyzed numerically and experimentally and their broadband operations are reported. The actual gain of the receiving active antenna is expressed in terms of the transducer power gain of the amplifier circuit and the effective length of the passive antenna. Between the feed point of the passive antenna element and the CPW, the silicon transistor 2SC2585 or 2SC3604 is integrated with a dipole antenna or loop antenna. The actual gains of a dipole antenna with 24 cm length are more than 8 dBd (relative gain to the standard half-wave dipole) at frequencies from 470 to 770 MHz for television channels 13-62 in Japan. In the case of a loop antenna with a size of 25. 8 cm12 cm, actual gains of more than 3. 5 dBd are obtained for channels 1-12, from 90 to 222 MHz, and more than 6. 5 dBd for channels 13-62, from 470 to 770 MHz.

Properties of a quarter-wavelength coplanar waveguide resonator such as resonant frequency, external quality factor (Qe) are characterized by a theoretical approach and verified by the experiment. The unloaded quality factor (Q0) of the resonator is also examined experimentally. After new types of combline bandpass filter (BPF) made of these resonators are realized, their transmission and reflection characteristics are examined theoretically and experimentally. A new combline BPF having attenuation poles are also realized. A simple method to produce two-port equivalent circuit of these BPF is presented in this paper. The transmission characteristics including such as the control of attenuation poles of these filters are explained by the created equivalent circuit with the concept of even and odd modes. A new method of describing attenuation poles is established.

The TMN that appears to operate the various communication networks generally and efficiently is developed under the different platform environment such as the different hardware and the different operating system. One of the main problems is that all the agents of the TMN system must be duplicated and maintain the software and the data blocks that perform the identical function. Therefore, the standard of the Q3 interface development cannot be defined and the multi-platform cannot be supported in the development of the TMN agent. In order to overcome these problems, the Farming methodology that is based on the Farmer model has been suggested. The main concept of the Farming methodology is that the software and the data components that are duplicated and stored in each distributed object are saved in the Platform Independent Class Repository (PICR) by converting into the format of the independent componentware in the platform, so that the componentwares that are essential for the execution can be loaded and used statically or dynamically from PICR as described in the framework of each distributed object. The distributed TMN agent of the personal communication network is designed and developed by using the Farmer model.

Rapid system prototyping is one of the main applications for field-programmable gate arrays (FPGAs). At the stage of rapid system prototyping, design specifications can often be changed since they cannot be determined completely. In this paper, layout design change is focused on and a layout reconfiguration algorithm is proposed for FPGAs. The target FPGA architecture is developed for transport processing. In order to implement more various circuits flexibly, it has three-input lookup tables (LUTs) as minimum logic cells. Since its logic granularity is finer than that of conventional FPGAs, it requires more routing resources to connect them and minimization of routing congestion is indispensable. In layout reconfiguration, the main problem is to add LUTs to initial layouts. Our algorithm consists of two steps: For given placement and global routing of LUTs, in Step 1 an added LUT is placed with allowing that the position of the added LUT may overlap that of a preplaced LUT; Then in Step 2 preplaced LUTs are moved to their adjacent positions so that the overlap of the LUT positions can be resolved. Global routes are updated corresponding to reconfiguration of placement. The algorithm keeps routing congestion small by evaluating global routes directly both in Steps 1 and 2. Especially in Step 2, if the minimum number of preplaced LUTs are moved to their adjacent positions, our algorithm minimizes routing congestion. Experimental results demonstrate that, if the number of added LUTs is at most 20% of the number of initial LUTs, our algorithm generates the reconfigured layouts whose routing congestion is as small as that obtained by executing a conventional placement and global routing algorithm. Run time of our algorithm is within approximately one second.

A floorplan is a partition of a rectangle into subrectangles, each of which is associated with a module. Zero-wasted-area layouts are known to exist when the height and width of modules are constrained only by the area, and several methods have been proposed for deriving such layouts. However, because these methods are global and indirect, they are inherently slow. We propose a new algorithm which simulates the air-pressure mechanics. It begins with a layout, which is not necessarily feasible, and iterates the movement of one wall at a time to the force-balancing position. The key issue is that it is guaranteed that every movement makes a current layout approach a zero-wasted-area layout by the measure of energy which is defined here. Experimental results on the example in several literatures and artificially made complex examples showed very fast convergence. The algorithm is evolved to methods which move all the walls simultaneously, resulting in a further speed enhancement.

A simulation model for natural convection was developed for determining the surface temperature distribution in base plates with rectangular vertical fins in communication equipment. An estimated velocity derived from the buoyancy and pressure drop equations in a duct was used for laminar forced convection cooling simulations in parallel plates. Temperature distributions in finned plates were calculated by numerical integration of the heat conduction equation. An experimental study was also performed, to check these simulation results, by changing the height of fins, the pitch of fins, and the heat generation conditions. Experimental results and analytical results were found to agree well. Also, this simulation method was extended to analyze natural convection cooling in vertical base plates with inclined parallel fins. We placed alternately on the plates the sections without fins and the sections with fins on the plates. Using the inclined fins, air flow rate between fins was large and fresh air flew into the fins from the side of the plates. The natural convective heat-transfer rate for inclined fins was found to be 14% higher than that for vertical fins.

In the floorplan design problem, soft blocks can take various rectilinear shapes. The conventional floorplanning methods, however, restrict their shapes only to rectangle. As a result, waste area often remains in the layout. Some floorplanning methods have been developed to handle rectilinear hard blocks, however, no floorplanning methods have been developed to optimize rectilinear soft blocks. In this paper, we propose a floorplanning method which places rectilinear soft blocks. The advantages of the method are reducing both waste area and wire length. We present Separate-Rejoin method which efficiently forms rectilinear shapes for soft blocks. The result is obtained quickly because the method is based on the slicing structure in spite of handling rectilinear block. Thus, our method is suitable for practical use in terms of layout area, wire length and processing time. We applied our method to a benchmark example and an industrial data. For the benchmark example, our method reduces waste area by 25% and wire length by 13% in comparison with the conventional rectangular soft block approach.

Gold on connector contacts is superior in environmental resistance. However, pores existing gold film are source to trigger the corrosion reaction between gold and base metal. For examination of the contacts, it has been popular to apply "Salt Spray Test" and "Sulfur Dioxide Test. " There are some differences of the corrosion products between two tests. Main metal forming the product in Salt Spray is Copper, and main metal in Sulfur Dioxide is Nickel. To investigate the reason, we tried to employ an electro-chemical method. As a result, it was found that there was the difference between the respective galvanic cell combinations generated through pores.

A more judicious choice of trial functions to implement the Improved Circuit Theory (ICT) application to multi-element antennas is achieved. These new trial functions, based on Tai's modified variational implementation for single element antennas, leads to an ICT implementation applicable to much longer co-planar dipole arrays. The accuracy of the generalized impedance formulas is in good agreement with the method of moments. Moreover, all these generalized formulas including the radiation pattern expressions are all in closed-form. This leads to an ICT implementation which still requires much shorter CPU time and lesser computer storage compared to method of moments. Thus, for co-planar dipole arrays, the proposed implementation presents a relatively very efficient method and would therefore be found useful in applications such as CAD/CAE systems.

Detection of facial emotions are mainly addressed by computer vision researchers based on facial display. Also detection of vocal expressions of emotions is found in research work done by acoustic researchers. Most of these research paradigms are devoted purely to visual or purely to auditory human emotion detection. However we found that it is very interesting to consider both of these auditory and visual informations together, for processing, since we hope this kind of multimodal information processing will become a datum of information processing in future multimedia era. By several intensive subjective evaluation studies we found that human beings recognize Anger, happiness, Surprise and Dislike by their visual appearance, compared to voice only detection. When the audio track of each emotion clip is dubbed with a different type of auditory emotional expression, still Anger, Happiness and Surprise were video dominant. However Dislike emotion gave mixed responses to different speakers. In both studies we found that Sadness and Fear emotions were audio dominant. As a conclusion to the paper we propose a method of facial emotion detection by using a hybrid approach, which uses multimodal informations for facial emotion recognition.

In this paper, we propose an algorithm of classification by feature partitioning (CFP) which learns concepts in the batch mode. The proposed algorithm achieved almost the same predictive accuracies as the best results of a CFP algorithm presented by Guvenir and Sirin. However, our algorithm is not affected by parameters and the order of examples.

We report on 1.9-GHz performance of the Buried-Channel self-aligned WN/W-gate GaAs MESFET (BC-MESFET) for use in digital mobile telephone handsets with low power consumption. The BC-MESFET incorporates undoped i-GaAs epitaxial-grown surface layer on the ion-implanted channel. Both the power and noise performance of the BC-MESFET are superior to the conventional MESFET. The 0.6-µm gate power BC-MESFET exhibits a high power-added efficiency of 57% at 1-dB gain compression, which leads to low power dissipation of the handset. This power performance is attributed to high breakdown voltage which the undoped i-GaAs surface layer has brought about. The BC-MESFET has also shown a minimum noise figure of below 0.4 dB. Taking the IC-oriented fabrication process of the BC-MESFET into consideration, these FET performances demonstrate that the BC-MESFET is suitable for the single-chip MMIC that integrates RF front-end blocks for the 1.9-GHz small-size mobile telephone handset with long battery lifetime.

A bicomplex representation for time-harmonic electromagnetic fields appearing in scattering and diffraction problems is given using two imaginary units i and j. Fieldsolution integral-expressions obtained in the high-frequency and low-frequency limits are shown to provide the new relation between high-frequency diffraction and low-frequency scattering. Simple examples for direct scattering problems are illustrated. It may also be possible to characterize electric or magnetic currents induced on the obstacle in terms of geometrical optics far-fields. This paper outlines some algebraic rules of bicomplex mathematics for diffraction or scattering fields and describes mathematical evidence of the solutions. Major discussions on the relationship between high-frequency and low-frequency fields are relegated to the companion paper which will be published in another journal.

Characterization of a mitered, a squarely cut, and a circular E-plane bend in rectangular waveguide is implemented by combining the port reflection coefficient method and the mode-matching method. Based on the port reflection coefficient method, the two-port waveguide bend is converted to a one-port structure comprised of cascaded waveguide step-junctions. After solving the reflection coefficient caused by these waveguide step-junctions using the mode-matching method, the desired scattering parameters of the bend are obtained readily. Convergence properties of the calculated numerical results are validated. Influences of the mitered, the squarely cut, and the circular part of the bend on the scattering parameters are investigated, and the optimal design dimensions for realizing wide-band and low return loss bends are found. Based on the optimal compensation dimension, an E-plane waveguide circular bend is fabricated and tested. The measured result agrees well with the theoretical prediction, and a full-band matched bend is practically realized.

We consider the problem of estimating one- and two-dimensional direction of arrivals for arbitrary plane waves in an incoherent/coherent source environment. For the one-dimensional case, we use matrix pencil (MP) method developed by Y. Hua for signal-poles estimation. We then extend this method to estimate the two-dimensional direction of arrivals (2D-DOA), resulting in the "Extended Matrix Pencil" (EMP) method. This method can be applied successfully as much for an incoherent source environment as for a coherent source environment. To study the performance of these methods, in both cases results are compared with the "Total Least Squares-Estimation of Signal Parameters via Rotational Invariance Techniques" (TLS-ESPRIT) and the "Spatial Smoothing-TLS-ESPRIT" (SS-TLS-ESPRIT) methods. The results show that the MP method estimates the DOA more accurately and better than the TLS-ESPRIT and the SS-TLS-ESPRIT, even with few snapshots. Simulation results show that the EMP method, presented in this paper, estimates the 2-DOA better than the other two methods used for comparison.

The EMC-adequate design of microelectronic systems includes all actions intended to eliminate electromagnetic interference in electronic systems. Challenges faced in the microelectronic area include a growing system complexity, high integration levels and higher operating speeds at all levels of integration (chip, MCM, printed circuit board and system). The growing complexity, denser design and higher speed all lead to a substantial increase in EMC problems and accordingly the design time. EMC is not commonly accepted as a vital topic in microelectronic design. Microelectronic designers often are of the opinion that EMC is limited to electrical and electronic systems and the mandatory product regulations instead of setting requirements also for the integrated circuit they are designing. In this contribution a concept for an EMC-adequate design of electronic systems will be introduced. This concept is based on a generalized development process to integrate EMC-constraints into the system design. A prototype of an environment to analyse signal integrity effects on PCB based on a workflow oriented integration approach will be presented. Based on this approach the generation of user specific design and analysis environments including various set of EMC-tools is possible.

In computer hardware there is a constant evolution towards smaller transistor sizes. At the same time, more and more transistors are placed on one chip. Both trends make the pin limitation problem worse. Scaling down chip sizes adds to the shortage of available pins while increasing the number of transistors per chip imposes a higher need for chip terminals. The use of three-dimensional systems would alleviate this pin limitation problem. In order to decide whether the benefits of such systems balance the higher processing costs, one must be able to characterize these benefits accurately. This can be done by estimating important layout properties of electronic designs, such as space requirements and interconnection length values. For a two-dimensional placement, Donath found an upper bound for the average interconnection length that follows the trends of experimentally obtained average lengths. Yet, this upper bound deviates from the experimentally obtained value by a factor of approximately 2 which is not sufficiently accurate for some applications. In this paper, we first extend Donath's technique to a three-dimensional placement. We then compute a significantly more accurate estimate by taking into account the inherent features of the optimal placement process.

This paper proposes cell-attached frame encapsulation schemes in which encapsulation processing can be performed without cell reassembly. The proposed schemes are especially useful for a global networking service platform to integrate widely distributed user LANs into a single internetwork. The platform itself is an ATM-based frame forwarding network composed of access networks and a core network. These elemental networks are interconnected via edge nodes. In order to improve network interworking performance, these edge nodes should perform encapsulation processing without cell reassembly. Our proposal solves this problem. In the proposed schemes, when the first cell of a cell-divided access network frame arrives at an ingress edge node, a core-header-cell is generated from the IP header described in the first cell payload. This core-header-cell is first transmitted and then succeeding incoming cells including the first cell are forwarded cell-by-cell as soon as they arrive. Since cell-by-cell forwarding-processing reduces frame forwarding latency and cell buffer capacity, these schemes are effective from the viewpoint of both performance improvement and cost reduction.

This is a review of our high-Tc superconductor (HTS) sampler development. The design and experimental demonstration of a Josephson sampler circuit based on YBa2 Cu3Ox(YBCO)/PrBa2Cu3Ox/YBCO ramp-edge junctions is described. The sampler circuit contains five edge junctions with a stacked YBCO groundplane and is based on single-flux quantum (SFQ) operations. Computer simulation results show that the time resolution of the sampler circuit depends strongly on the IcRn product of the junction and can be reduced to a few picoseconds with realistic parameter values. The edge junctions were fabricated using an in-situ process in which a barrier and a counter-electrode layer are deposited immediately after the edge etching without breaking the vacuum. The in-situ process improved the critical current uniformity of the junctions to 1σ20% in twelve 4-µm-width junctions. An YBCO groundplane was placed on the junctions in a multilayer structure we call the HUG (HTS cricuit with an upper-layer groundplane) structure. The inductance of YBCO lines was reduced to 1 pH per square without junction-quality degradation in the HUG structure. SFQ current-pulse generation, SFQ storage, and SFQ readout in the circuit have been confirmed by function tests using 3-kHz pulse currents. The successful operation of the sampler circuit has been demonstrated by measuring a signal-current waveform at 50K.

We propose a transistor placement algorithm to generate standard cell layout in a two-dimensional placement style. The algorithm optimizes the one-dimensional placement in the first stage, folds the large transistors in the second stage, and optimizes the two-dimensional placement in the final stage. We also propose "cost function" based on wiring length, which closely match the cell optimization. This transistor placement algorithm has been applied to several standard cells, and demonstrated the capability to generate a two-dimensional placement that is comparable to manually designed placement.