In this paper, a high-speed PLA based on dynamic array logic circuits with latch sense amplifiers is presented. The present circuit consists of logic cell arrays, dual-rail bit-lines, latch sense amplifiers, and control blocks. By using a charge sharing scheme and latch sense amplifiers, voltage swings of the bit-lines are reduced compared to the conventional circuits, thus a high-speed and low-power operation is achieved. The present array logic configuration can realize any logic function expressed in the sum-of-products form by using PLA structure. As an application of the proposed PLA, a 32-bit binary comparator is designed and implemented in a 0.6-µm double-poly triple-metal CMOS process. Results of HSPICE simulation show a better performance compared to the conventional circuits. Functional testing using electron beam probing shows that the present circuit operates correctly.

In mechanical splice technology, loss change during temperature cycling is mainly caused by fiber slippage or shift at the interface between fibers and fiber clamping substrates. The upper limit of the fabrication accuracy of the fibers and substrates restricts the total number of fibers in a splice. To overcome this, we propose a novel fiber clamping method using the elasticity of the substrate surface. We clamp the fibers more strongly at the fiber clamping ends, where the fibers need a greater friction force than around the butt-joint, to hold them in position. Taking the case of an 8-fiber ribbon splice, we compared linear marks on the substrates with the boundary linewidth curves for the onset of slippage. We achieved an insertion loss change of less than 0.1 dB during a temperature cycling test in accordance with Telcordia Technologies test specification. When we clamp fibers using the plasticity of the substrate surface, we can also reduce the required fabrication accuracy. However, insufficient accuracy causes an unexpected loss change due to fiber shift as a result of a plastic flow on the substrate surface in contact with the fibers.

Negative differential conductance based on lateral interband tunnel effect is demonstrated in a planar degenerate p+-n+ diode (Esaki tunnel diode). The device is fabricated with the current silicon ultralarge scale integration (Si ULSI) process, paying attention to the processing damage so as to reduce an excess tunnel current that flows over some intermediate states in the tunnel junction. I-V characteristics at a low temperature clearly show an intrinsic electron transport, indicating phonon-assisted tunneling in Si as in the case of the previous Esaki diodes fabricated by the alloying method. In addition, a simple circuit function of bistable operation is demonstrated by connecting the planar Esaki diode with conventional Si metal-oxide-semiconductor field effect transistors (MOSFETs). The planar Esaki diode will be a promising device element in the functional library for enhancing the total system performance for the coming system-on-a-chip (SoC) era.

This paper describes distributed communications based on a new paradigm of middleware platform called the typed bus (TB) platform. While traditional middleware platforms provide the same type of communication paths between distributed objects, the TB platform provides typed buses, which are communication paths differentiated according to application's communication characteristics. Each typed bus represents unique communication type and controls communications between distributed objects according to its type as a hardware system bus constrains communication between hardware components. Distributed communications are achieved via typed buses, which check if the communications are compliant with their types. In this paper we propose the architecture of the TB platform, introduce TB Type Definition Language used to specify a typed bus's type, and describe an implementation of our platform.

MPEG-4 emphasizes on coding efficiency and allows for content-based access and transmission of arbitrary shaped object. It addresses the encoding of video object using shape coding, motion estimation, and texture coding for interactivity, high compression ratio, and scalability. In this letter, an advanced object-adaptive vertex-based shape coding method is proposed for encoding the shape of video objects. This method exploits octant-based representation to represent the relation of adjacent vertices and that relation can be used to improve coding efficiency. Simulation results demonstrate that the proposed method may reduce more bits for closely spaced vertices.

A gradient ascent learning algorithm of the Hopfield neural networks for graph planarization is presented. This learning algorithm uses the Hopfield neural network to get a near-maximal planar subgraph, and increases the energy by modifying parameters in a gradient ascent direction to help the network escape from the state of the near-maximal planar subgraph to the state of the maximal planar subgraph or better one. The proposed algorithm is applied to several graphs up to 150 vertices and 1064 edges. The performance of our algorithm is compared with that of Takefuji/Lee's method. Simulation results show that the proposed algorithm is much better than Takefuji/Lee's method in terms of the solution quality for every tested graph.

This paper concerns resource planning in a VLSI assembly facility. The facility can process more than 100 sorts of WIPs (Works-In-Process) simultaneously. Specifically it performs product-mix production. An old resource estimation system, which gave a good estimation for a memory VLSI production facility, went wrong for an assembly facility. To adjust the estimation of required machinery resources of the assembly facility, a new parameter--the tuning value for the service time--is introduced. The tuning value expresses the reduction in machine utilization in the processing steps due to the product-mix. The value is empirically determined and the machinery resources can be estimated in good accuracy. Also the waiting time for processing in the incoming buffer is successfully considered in the estimation of turnaround time. However the tuning value is not enough in estimating human resources. A novel algorithm to estimate the resources for machine adjustments is proposed. The algorithm is based on a periodic assignment of multiple sorts of WIPs in a single machine, where the adjustments of machines for the product-mix are considered. The adjustments are additional operator's jobs in the product-mix. It estimates the operator request rate and machine utilization rate when multiple sorts of WIPs with different arrival rates are processed in a single machine. Finally, this resource estimation system considers the operator allocated not only to the preprocessing and postprocessing but also to the adjustments of machines for the product-mix. The estimated machinery, human resources, and turnaround time were evaluated in a real facility, and the proposed method is confirmed to be applicable in the weekly or monthly resource planning for the facility.

A low loss magnetic plate positioned near an antenna is proposed to increase radiation efficiency of cellular phones. This magnetic plate is used to control the nearby magnetic field around the cellular phone's antenna, and this field controlling is shown to be effective for the improvement of radiation efficiency and far-field pattern. As for the material design of the plate, a magnetic plate having high µr and low µr" (complex relative permeability: µr = µr - j µr") is found to be effective for achieving high performance. In our sample fabrication, a low loss magnetic sample with µr = 5.7 - j 0.7 at 900 MHz is realized. It is demonstrated that this low loss sample contributes to increased efficiency and improved far-field characteristics.

A new IDDQ testable design method is proposed for static CMOS PLA circuits. A testable PLA circuit of NOR-NOR type is designed using this method. It is shown that all bridging faults in NOR planes of the testable designed PLA circuit can be detected by IDDQ testing with 4 sets of test input vectors. The test input vectors are independent of the logical functions to be realized in the PLA circuit. PLA circuits are designed using this method so that the quiescent supply current generated when they are tested will be zero. Thus, high resolution of IDDQ tests for the PLA circuits can be obtained by using the testable design method. Results of IDDQ tests of PLA circuits designed using this testable design method confirm not that the expected output can be generated from the circuits but that the circuits are fabricated without bridging faults in NOR planes. Since bridging faults often occur in state-of-the-art IC fabrication, the testable design is indispensable for realizing highly reliable logic systems.

We have developed a new planar lightwave circuit (PLC) platform eliminating Si terraces for hybrid integrated optical modules. This PLC platform has the advantage of a lower fabrication cost than the conventional PLC platform with an Si terrace, because it does not require fabrication processes such as Si terrace forming and mechanical polishing. Using our new PLC platform structure, we fabricated a transceiver for optical access networks and an 8-channel multi-channel photoreceiver for wavelength division multiplexing (WDM) interconnection systems.

We have developed a new planar lightwave circuit (PLC) platform eliminating Si terraces for hybrid integrated optical modules. This PLC platform has the advantage of a lower fabrication cost than the conventional PLC platform with an Si terrace, because it does not require fabrication processes such as Si terrace forming and mechanical polishing. Using our new PLC platform structure, we fabricated a transceiver for optical access networks and an 8-channel multi-channel photoreceiver for wavelength division multiplexing (WDM) interconnection systems.

Let m 2, n 2, and q 2 be positive integers. Let Sr and Sb be two disjoint sets of points in the plane such that no three points of Sr Sb are collinear, |Sr| = nq, and |Sb| = mq. This paper shows that Kaneko and Kano's conjecture is true, i.e., there are q disjoint convex regions of the plain such that each region includes n points of Sr and m points of Sb. This is a generalization of 2-dimension Ham Sandwich Theorem.

This paper proposes a managed IP multicast platform that enables IP multicast services to be used for business. Nowadays, many business applications have switched from traditional network platforms to the IP platform. Among these applications, one-to-many or many-to -many types of applications are especially essential to business users. These applications may use IP Multicasting for transmitting data to many users. However, for business applications, it is difficult to use the present IP Multicast services, because they lack many requirements for business usage. The requirements are address management, authentication, time management, and guaranteed throughput. To satisfy the business users, we made the design of a managed IP multicast platform that will meet these requirements. Our platform, which separates the routing control layer and the packet forwarding layer, is called GMN-CL (Connection Technologies for Global Mega-media Network). The routing control layer manages routing information and controls network routing centrally, so it can understand the whole network situation and perform efficient routing. The packet forwarding layer can concentrate completely on forwarding, so the forwarding speed and copying speed is higher than when using routers. We have implemented our design of a managed IP multicast platform over GMN-CL. This paper reports the system design, implementation, and evaluation.

We propose middleware which works on widely-used commercial off-the-shelf platforms (UDP/IP, FastEthernet, and Windows NT or commercial real-time kernels) to realize real-time distributed services for plant monitoring and control systems. It is not suitable to use TCP/IP for the systems because of its unpredictable re-transmission, while, as well known, UDP/IP does not guarantee certain arrivals of packets and it is also not acceptable for the systems. With UDP/IP, packets are lost mainly because of collisions in a network and buffer overflows. To avoid these packet losses, the middleware controls scheduling of all the packets transmitted between the nodes in a distributed system and prevents excessive collisions and buffer overflows. The middleware provides a necessary set of functions for plant monitoring and control applications. The middleware on each node in a distributed system consists of library functions and run-time modules. An application program on the node is required to use these library functions according to the rules the middleware provides. In this way the middleware can manage all the traffic among the nodes in the system. Receiving requests from the application via library functions, the run-time module of the middleware schedules transmission of messages to other nodes, avoiding unexpected delivery delays or buffer overflows. The module also guarantees application-to-application quality of service (QoS), such as transmission period and delivery deadline, required by the applications. This is achieved by assigning the resources not shared by other services to each distributed service and scheduling these resources so as not to violate the assignment. Here, resources include maximum numbers of packets which a node can receive or send in a specific period (20 msec, for example). We show implementation of the middleware to make it clear how to guarantee application-to-application QoS with some application examples.

The transmission S-parameter, S21, between dipole elements on a rectangular finite ground plane is calculated by the MoM with planar-segments in the horizontally and vertically polarized configurations. Supposed a 1/10 scaling, the frequency range is selected 0.15-0.8 GHz. The size of the finite ground plane is 40 cm 100 cm. The dipole-element length is 18.8 cm (half-wavelength at 0.8 GHz). The distance between dipole elements is 30 cm. The results are compared to the calculated results with the conventional MoM-GTD hybrid method and also the measured results with a TRL-calibrated network analyzer. It makes clear that the MoM-GTD hybrid method is not applicable to a small ground plane in the vertically polarized configuration. The results calculated by the MoM with planar-segments agree well to the measured results both in the horizontal and vertical polarizations. The results show that the size of the finite ground plane for the vertical polarization should be much larger than for the horizontal polarization.

This paper newly formalizes some notions of security for probabilistic public-key encryption schemes. The framework for these notions was originally presented in the work by Bellare et al., in which they consider non-malleability and indistinguishability under chosen-plaintext attack, non-adaptive chosen-ciphertext attack and adaptive chosen-ciphertext attack. This paper extends the results of Bellare et al. by introducing two goals, equivalence undecidability and non-verifiability under the above three attack models. Such goals are sometimes required in electronic voting and bids systems. It is shown that equivalence undecidability, non-verifiability and indistinguishability are all equivalent under the three attack models.

Fabrication technology for Nb integrated circuits has been developed. In developing fabrication technology, the key process steps are the etching to form fine Nb electrodes and the formation of reliable insulation layers. The standard process has been developed focusing on reproducibility and reliability. In the process, conventional reactive ion etching and RF bias-sputter deposition are used. The number of Nb wiring layers is two, and standard deviation (σ) of critical current is 0.9%, 2.3%, and 4.7% for the junction sizes of 2 µm, 1.4 µm, and 1 µm, respectively. The advanced process has also been developed focusing on capability of increasing the integration scale. Electron-cyclotron-resonance plasma etching and mechanical polishing planarization have been developed as advanced process technology. The number of Nb wiring layers is three, and σ is improved to 0.8%, 0.7%, and 1.7% for the junction sizes of 2 µm, 1.4 µm, and 1 µm, respectively. Integration limits are discussed and it is estimated that the maximum number of junctions is in the order of 105 and 107 for the standard and the advanced process, respectively. A large-scale superconducting circuit such as a several M-bit RAM can be realized in the future by using these fabrication technologies.

We introduce a refined definition of semantic security. The new definition is valid against not only chosen-plaintext attacks but also chosen-ciphertext attacks whereas the original one is defined against only chosen-plaintext attacks. We show that semantic security formalized by the new definition is equivalent to indistinguishability, due to Goldwasser and Micali for each of chosen-plaintext attacks, non-adaptive chosen-ciphertext attack, and adaptive chosen-ciphertext attack.

This paper introduces a flexible, stream-oriented dataflow processing model based on the "Communicating Logic (CL)" framework. As the target architecture, we adopt the dual layered "Plastic Cell Architecture (PCA). " Datapath processing functionality is encapsulated in asynchronous hardware objects with variable graining and implemented using look-up tables. Communication (i.e. connectivity and control) between the distributed processing objects is achieved by means of inter-object message passing. The key point of the CL approach is that it offers the merits of scalable performance, low power hardware implementation with the user friendly compilation and linking capabilities unique to software.

Recently, Plastic Cell Architecture (PCA) has been proposed as a hard-wired general-purpose autonomously reconfigurable processor. PCA consists of two layers, the plastic part on which sequential logic circuits are implemented, and the built-in part which induces the plastic part to dynamically reconfigure the circuits and transports messages among the circuits. The plastic part consists of an array of LUT-based reconfigurable logic primitives, each of which is connected only to adjacent ones. Combining logic and layout synthesis, we propose a new array-based algorithm to map logic functions into the PCA plastic part. This algorithm produces a folded array of sum-of-multi-input-complex-terms, especially for the PCA plastic part.