In this letter, base station placement is automatically determined from pre-defined candidate sites using a genetic approach, and the transmit power is obtained taking the interference situation into account in cases of interference-dominant systems. In order to apply a genetic algorithm to the base station placement problem, a real-valued representation scheme is proposed. Corresponding operators such as crossover and mutation are also introduced. The proposed algorithm is applied to an inhomogeneous traffic density environment, where a base station's coverage may be limited by offered traffic loads. An objective function is designed for performing the cell planning in a coverage- and cost-effective manner.

In this letter, we show that Fan-Chen-Yeh's blind signature scheme and Chien-Jan-Tseng's partially blind signature scheme are vulnerable to the chosen-plaintext attack. We also show that both schemes can be modified so that the chosen-plaintext attack is impossible. But, still Chien-Jan-Tseng's partially blind signature scheme is vulnerable. It fails to satisfy the partial blindness property.

Buffer caching is an integral part of the operating system. In this paper, we propose a scheme that integrates buffer cache management and prefetching via cache partitioning. The scheme, which we call SA-W2R, is simple to implement, making it a feasible solution in real systems. In its basic form, for buffer replacement, it uses the LRU policy. However, its modular design allows for any replacement policy to be incorporated into the scheme. For prefetching, it uses the LRU-One Block Lookahead (LRU-OBL) approach, eliminating any extra burden that is generally necessary in other prefetching approaches. Implementation studies based on the GNU/Linux kernel version 2.2.14 show that the SA-W2R performs better than the scheme currently used, with a maximum increases of 23% for the workloads considered.

The problem of optimal placement of pilot symbols is considered for single carrier packet-based transmission over time varying channels. Both flat and frequency-selective fading channels are considered, and the time variation of the channel is modeled by Gauss-Markov process. The semi-blind linear minimum mean-square error (LMMSE) channel estimation is used. Two different performance criteria, namely the maximum mean square error (MSE) of the channel tap state over a packet and the cumulative channel MSE over a packet, are used to compare different placement schemes. The pilot symbols are assumed to be placed in clusters of length (2L+1) where L is the channel order, and only one non-zero training symbols is placed at the center of each cluster. It is shown that, at high SNR, either performance metric is minimized by distributing the pilot clusters throughout the packet periodically. It is shown that at low SNR, the placement is in fact not optimal. Finally, the performance under the periodic placement is compared with that obtained with superimposed pilots.

In this paper, the power plane resonance problem in a multi-layered PCB is numerically analyzed by applying the alternating-direction implicit (ADI) FDTD method. This method is extremely suitable for analyzing the power plane resonance problems having locally fine structures of two closely located planes. This paper also analyzes the effect of the decoupling capacitor, which is one of the solutions for reducing the resonance problem. The results of the ADI-FDTD agree well with those of the conventional FDTD and the analytic solutions, and the computational CPU time is reduced to about a half of that of the conventional FDTD.

Changing vehicle structures and backgrounds makes it very difficult to correctly extract a license plate region from a vehicle image. In this paper, we propose a simple method to extract the license plate region using edge properties of wavelet subband. The High Frequency Subband (HFS) of an image has edge information for each direction. Edge information is concentrated in each direction of the Headlight-Radiator-Headlight (H-R-H) and the license plate region compared to other regions in the vehicle image. This paper shows a license plate region extraction method using these edge properties and our experimental results with various vehicle images.

As a typical planar antenna in Japan, a microstrip antenna and radial line slot antenna are chosen and some original technologies are introduced for them. About the microstrip antenna, the analyzing method is described first and the method based on the theory of microstrip planar circuit born in Japan is introduced. According to the formulas derived by this method, the design procedure considering the bandwidth is established. In addition, it is shown clearly that a microstrip antenna can produce the circular polarizations at two kinds of frequencies with a single feed. Furthermore, two kinds of broadband techniques born in Japan are picked up. About other unique microstrip antennas, they may be introduced in a suitable section each time. As for the RLSA, the history on invention is briefly presented. The radiation mechanisms depending on the slot-set arrangement and the excitation mode are discussed. The slot-coupling analysis to simulate the excitation of a two-dimensional uniformly-excited slot array is explained. The simple design based on the operation with traveling-wave propagation is also described. The technical progress to keep high efficiency in a wide gain range for satellite-TV reception is reviewed. Extensions of the RLSAs to millimeter-wave bands and plasma etching systems are finally summarized.

This paper presents a miniaturized reverse-phase hybrid ring by the use of shunt capacitors, and successfully designs a very miniature hybrid ring of a 0.28-wavelength circumference with a wide bandwidth comparable to the regular reverse-phase hybrid ring based on the equivalent admittance approach. Moreover, a method of broadening the bandwidth with adding a matching network consisting of a very short transmission line and two shunt capacitors at each port is also described. The validity of the proposed design is demonstrated by electromagnetic simulator (Sonnet em) for a uniplanar hybrid ring.

Many services on the Internet are provided by multiple identical servers in order to improve performance and robustness. The number, the location and the distribution of servers affect the performance and reliability of a service. The server placement is, however, often determined based on the empirical knowledge of the administrators. This paper investigates issues of the server placement in terms of the service performance and the server load. We identify that a server selection mechanism plays an important role in server placement, and thus, evaluate different server selection algorithms. The result shows that it is essential to the robustness of a service to employ a mechanism which distributes service requests to the servers according to the measured response time of each server. As a case study, we evaluate the server selection mechanisms employed by different DNS (Domain Name System) implementations. Then, we show the effects of the different server selection algorithms using root-server measurements taken at different locations around the world.

Basic characteristics of a short-ended half-wavelength resonator made of a coplanar waveguide (CPW) and their applications to bandpass filters (BPFs) are discussed. The first part of this paper gives the essence for improving out-of-band characteristics of the BPF by describing the basic characteristics of a tap-coupled resonator. Secondly, a new BPF with attenuation poles using the short-ended half-wavelength CPW resonators is proposed and realized. It is confirmed that our methodology is useful for improving out-of-band characteristics of the BPF using the short-ended half-wavelength CPW resonators without complicated filter design.

A high temperature superconductor (HTS) 5 GHz 10-pole bandpass filter (BPF) is designed by using coplanar waveguide (CPW) quarter-wavelength resonators. The 10-pole Chebyshev BPF has a center frequency 5.0 GHz and a fractional bandwidth 3.2%. Based on an equivalent circuit with J- and K-inverters, the filter is first designed by using an EM simulator. Next an optimization algorithm is employed to diagnose the discrepancy between the filter responses calculated by the EM simulator and the equivalent circuit. Adjustment of the dimensions of the filter is made thereby. The frequency response of the adjusted filter satisfies well the design specifications.

The encryption algorithm Camellia is a 128 bit block cipher proposed by NTT and Mitsubishi, Japan. Since the algebraic degree of the outputs after 3 rounds is greater than 128, designers estimate that it is impossible to attack Camellia by higher order differential. In this paper, we show a new higher order differential attack which controls the value of differential using proper fixed value of plaintext. As the result, we found that 6-round F-function can be attacked using 8th order differentials. The attack requires 217 chosen plaintexts and 222 F-function operations. Our computer simulation took about 2 seconds for the attack. If we take 2-R elimination algorithm, 7-round F-function will be attacked using 8th order differentials. This attack requires 219 chosen plaintexts and 264 F-function operations, which is less than exhaustive search for 128 bit key.

As an RF high Tc superconducting (HTS) front end for a microwave receiver, we propose a new design method for the broadband matching circuit composed of coplanar waveguide (CPW) meanderline resonators connecting a slot antenna with CMOS low noise amplifier (LNA). The parameters of the antenna sections with matching circuit are calculated and simulated with the circuit simulator and electromagnetic field simulator. CMOS LNA was designed and its input and output impedances and noise figure were obtained by SPICE simulation.

The sequence-pair was proposed as a representation method of block placement to determine the densest possible placement of rectangular modules in VLSI layout design. A method of achieving bottom left corner packing in O(n2) time based on a given sequence-pair of n rectangles was proposed using horizontal/vertical constraint graphs. Also, a method of determining packing from a sequence-pair in O(n log n) time was proposed. Another method of obtaining packing in O(n log log n) time was recently proposed, but further improvement was still required. In this paper, we propose a method of obtaining packing via the Q-sequence (representation of rectangular dissection) in O(n+k) time from a given sequence-pair of n rectangles with k subsequences called adjacent crosses, given the position of adjacent crosses and the insertion order of dummy modules into adjacent crosses. The position of adjacent crosses and insertion order of dummy modules can be obtained from a sequence-pair in O(n+k) time using the conventional method. Here, we prove that arbitrary packing can be represented by a sequence-pair, keeping the value of k not more than n-3. Therefore, we can determine packing from a sequence-pair with k of O(n) in linear time using the proposed method and the conventional method.

In this paper, we propose a floorplanning method for VLSI building block layout. The proposed method produces a floorplan under the timing constraint for a given netlist. To evaluate the wiring delay, the proposed method estimates the global routing cost for each net with buffer insertion and wire sizing. The slicing structure is adopted to represent a floorplan, and the Elmore delay model is used to estimate the wiring delay. The proposed method is based on simulated annealing. To shorten the computation time, a table look-up method is adopted to calculate the wiring delay. Experimental results show that the proposed algorithm performs well for producing satisfactory floorplans for industrial data.

This paper describes high power density and low distortion characteristics of a novel InGaP channel field-modulating plate FET (InGaP FP-FET) under high voltage operation of over 50 V. The developed InGaP FP-FET exhibited an extremely high breakdown voltage of 100 V with an impact ionization coefficient about 103 times smaller than that of GaAs. These superior breakdown characteristics indicate that the InGaP FP-FET is one of the most desirable device structures for high-voltage high-power operation. The InGaP FP-FET delivered an output power density of 1.6 W/mm at 1.95 GHz operated at a drain bias voltage of 55 V. As power operation moves from class A to class AB, both 3rd-order intermodulation distortion (IM3) and power-added efficiency (PAE) at higher output-power region were improved, resulting from a suppressed gate leakage current near the power saturation point. These results promise that the developed InGaP FP-FET is suited for applications in which both high efficiency and low distortion are required.

As a design flow for low-power FPGA implementation, Datapath-Layout-Driven Design (DLDD) has been proposed. This letter reports the effect of DLDD for standard-cell-based ASIC implementation, and proposes necessary improvements. Experimental results shows that about 8.3% reduction of power dissipation is achieved in the best case.

Near-fields of electromagnetic waves scattered by slightly rough metal surfaces which support the surface plasmon mode at optical frequencies were studied theoretically by using the stochastic functional approach. Fidelity of near-field intensity images, defined by the correlation coefficient between the surface profile and the intensity of the scattered wave field, was investigated in order to discuss field distributions of the surface plasmon on complicated structures. We show that the fidelity strongly depends on the incident wavenumber and polarization when the incident wave corresponds to the surface plasmon mode.

We propose linearization techniques for MMIC amplifiers. The key points of these techniques are increased linearity of a newly-developed low-distortion MESFET (LD-FET) and maximized IP3 by combining the LD-FET with a high-gain depletion-mode MESFET (D-FET) with no increase in power consumption. The LD-FET is characterized by its unique channel dopant-profile prepared by a buried p-type ion-implantation and double n-type ion-implantations with high- and low-acceleration energies. This FET achieves flatter behavior in terms of mutual conductance (gm) compared with conventional MESFETs irrespective of changes in the gate bias voltage (Vgs). A self-alignment/selective ion-implantation process enables the LD-FET and D-FET to be fabricated simultaneously. This process encourages IP3 maximization of the multi-stage amplifier by appropriately combining the advantages of the two differently characterized MESFETs. We fabricated and tested a highly linearized two-stage MMIC amplifier utilizing the proposed techniques, and found that its third-order intermodulation ratio (IMR) performance was 8.7 dB better than that of conventional MMIC amplifiers at an input signal level of -20 dBm with no increase in current dissipation. The configuration constructed by using the proposed techniques equivalently reduces the current dissipation of the second stage to 1/2.72 times that of the conventional configuration, which requires a 2.72 times larger D-FET at the second stage to obtain an 8.7-dB IMR improvement. Furthermore, we were able to improve the IMR by 3.5 dB by optimizing the gate bias conditions for the LD-FET. These results confirm the validity of the proposed techniques.

Recently, Lin et al. addressed two weaknesses of a new strong-password authentication scheme, the SAS protocol, and then proposed an improved one called the OSPA (Optimal Strong-Password Authentication) protocol. However, we find that both the OSPA protocol and the SAS protocol are vulnerable to the stolen-verifier attack.