Interdigital transducers (IDTs) with leaky-SAWs propagating on 36 YX-LiTaO3, and 41 and 64 YX-LiNbO3 were theoretically analyzed, providing a new equivalent circuit. This equivalent circuit included attenuation constant due to leakage as well as conductance caused by bulkwave radiation. All circuit parameters were derived by solving integral equations. Fundamental experiments showed fairly good agreement between theoretical and experimental results, which gave very accurate design tools for leaky-SAW devices.

An optoelectronic technique to control both the amplitude and phase of a radio frequency (RF) signal is presented that uses two electrically controllable birefringence mode nematic liquid-crystal spatial light modulators (ECB mode nematic LC-SLMs). An experimental circuit was built and its performance was examined. The intensity could be changed down to -25 dB, and a phase shift of up to 240 degrees was achieved, by changing LC-SLM supplied voltages. Carrier-to-noise ratio (CNR) and intermodulation characteristics of an RF signal were measured. It was, for the first time, found that CNR was not degraded by the amplitude control and phase shift performed by the LC-SLMs.

Future digital land mobile communication, for a moving picture, requires more transmission speed and less bit error rate than the existing system does for speech. In the system, the intersymbol interference may not be ignored, because of higher transmission speed. An adaptive equalizer is necessary to cancel intersymbol interference. To achieve low bit error rate performance on the mobile radio channel, trellis-coded modulation with interleaving is necessary. This paper proposes an interleaved trellis-coded modulation scheme combined with a decision feedback type adaptive equalizer of high performance. The reliable symbol reconstructed in the trellis decoder is used as the feedback signal. To make equalizer be free from decoding delay, deinterleaving is effectively utilized. The branch metric, for trellis-coded modulation decoding, is calculated as terms of squared errors between a received signal and an expected signal by taking the reconstructed symbol and the impulse response estimated by the recursive least squares algorithm into account. The metric is constructed to have good discrimination performance to incorrect symbols even in non-minimum phase and to realize path diversity effect in a frequency selective fading channel. Computer simulation results are shown for several channel models. On a frequency selective fading channel, average bit error rate is less than 1/100 of that of the RLS-MLSE equalizer for fdTs=1/1000 at average Eb/N0 beyond 15dB. Performance degradation due to equalization error is less than 1.8dB. Performance is greatly improved by the effect of the reconstructed symbol feedback.

The distributed measurement-based quasi-fixed frequency assignment (also known as quasi-static adaptive frequency assignment-QSAFA) methodology is a practical solution for frequency assignment in the emerging TDMA personal communications networks (PCN/PCS). Five different QSAFA algorithms are studied in this paper under different interference threshold settings. It is found that a simple aggressive algorithm without using a threshold (LIA-Least Interference Algorithm) performs the best under the conditions studied. The performance of this algorithm is also justified by the theoretical proof presented at the end of this paper.

The investigation of device functions required from the systems point of view will be important for the development of the next generation of VLSI devices and systems. In this paper, a super pass transistor (SPT) model is presented as a quantum device candidate for future VLSI systems based on multiple-valued logic. A possible quantum device structure for the SPT model is also described, which employs the concepts of a lateral-resonant-tunneling quantum-dot transistor and a heterostructure field-effect transistor. Since it has the powerful capability of detecting multiple signal levels, the SPT will be useful for the implementation of highly compact multiple-valued VLSI systems. To exploit the functionality of the SPT, a super pass gate (SP-gate) corresponding to a single SPT is proposed as a multiple-valued universal logic module. The mathematical properties of the SP-gate are discussed. A design method for a multiple-valued SP-gate network is presented. An application of SP-gates to a multiple-valued image processing system is also demonstrated. The SP-gate network for the multiple-valued image processing system is evaluated in comparison with the corresponding NMOS implementation in terms of the number of transistors, interconnections and cascaded transistor stages. The size of a generalized series-parallel SP-gate network is also evaluated in comparison with a functionally equivalent multiple-valued series-parallel MOS pass transistor network. The results show that highly compact multiple-valued VLSI systems can be achieved if the SPT-model can be realized by an actual quantum device.

A channel equalization technique on a time division duplex CDMA/TDMA system for wireless multimedia networks is investigated, and the bit error rate performance of the system is theoretically analyzed. The assumed network connects mobile terminals to a node of ATM based high speed LAN through a radio central unit. Only human interface facilities are implemented into the terminal so that users access integrated services through the node of the network. The uplink (from a mobile terminal to a radio central unit) employs a CDMA scheme to transmit human interface signals and the downlink employs a TDMA scheme to transmit display interface signals. Both the CDMA and the TDMA signals occupy the same frequency band. To mitigate bit error rate degradation due to fading, the radio central unit estimates the impulse response of the channel from the received CDMA signals and subtracts the replica signal to cancel the major intersymbol interference (ISI) component. Numerical results using the Nakagami-m fading model and recent propagation measurements show that the proposed TPC technique compensates the fading attenuation and the proposed CEQ cancels the major ISI component. The bit error rate performance of the downlink with the proposed CEQ is superior to that with the DFE by 12dB of the symbol SNR at the BER=10-6 over a specular channel, and the system with the proposed CEQ achieves a BER=10-6 at the symbol SNR=12dB. Furthermore, the channel equalizer is implemented without increases in complexity of the terminal because all the processing on the equalization is carried out only in the radio central unit.

The scattering characteristics of a waveguide T-junction with an inductive post are analyzed by the port reflection coefficient method (PRCM), combined with the mode-matching technique. Variation behaviors of the scattering parameters are provided as a function of the operating frequency and the dimensions of the junction. The results are helpful for the design of power dividers using this type of T-junction configuration.

To support high bit rate and high quality indoor radio communication systems, we have to solve intersymbol interference (ISI) problem caused by frequency-selective fading. Recently multi-carrier modulation technique is considered to be one of the effective methods for this problem. In this paper we propose Partial Frequency ARQ (Automatic Repeat reQuest) system which can achieve effective ARQ scheme for multi-carrier packet communication. This system operates partial retransmission of erroneous power faded packets, and it is superior to the traditional ARQ systems. Furthermore two different protocols are examined for this system: Static Carrier Assignment (SCA) and Dynamic Carrier Assignment (DCA). By computer simulation we found that DCA method can achieve better performance than SCA in terms of both throughput and packet transmission delay.

CDMA cellular land network (CCLN) consists of base stations connected to selector bank subsystem. In the case of considering only the voice traffics, CCLN can be designed based on E1/T1 physical line and HDLC protocol with fixed or variable length. However, it is necessary to support not only voice but also data traffics in CDMA cellular system. Thus, it is needed to use physical lines efficiently to increase bandwidth efficiency and transmission speed. However, the conventional CCLN has some problems that the bandwidth is wasted because each BTS has its own private line. In this paper, the method using Distributed Queue Dual Bus (DQDB) Metropolitan Area Network (MAN) as a CDMA interconnect subsystem (CIS) is considered, and the performances of conventional and proposed methods constructing CIS are analyzed by computer simulation. According to the simulation results, if the traffics from all mobile stations are uniformly distributed among all BTSs, the performances of both conventional and proposed methodology have turned out to be almost equal. However, the performance of methodology using the DQDB MAN is much better than that of conventional method, in the case that the traffics from all mobile stations are nonuniformly distributed.

A generalized surface scattering radar equation for a near-nadir-looking pencil beam radar, which covers both beam-limited and pulse-limited regions, is derived. This equation is a generalization of the commonly used nadir-pointing beam-limited radar equation taking both antenna beam and pulse wave form weighting functions into account, and is convenient for the calculation of radar received power and scattering cross-section of the surface.

An adaptive digital filter with adaptive sampling phase is proposed. The structure of the filter makes use of an adaptive delay device at the input of the filter. The algorithm is derived to determine the value of the delay and the filter coefficients by minimizing MSE (mean square error) between the desired signal and the filter output. The computer simulation of the convergence of the proposed adaptive filter with the input of sinusoidal wave and BPSK modulated wave are shown. According to the simulation, the MSE of the proposed adaptive delay algorithm is lower than that of the conventional LMS algorithm.

An optimum design scheme for logical network topologies on a Flexible Multi-QoS Logical ATM Network, named Full-Net, is proposed. Full-Net offers high-quality Virtual-Path (VP) networks and controls end-to-end QoS only at the VP-network's access points. To develop the optimum network topology for multimedia traffic in a single ATM network, a logically con figured Virtual Channel Handler (VCH) interconnection network is associated with each QoS class. Many logical networks can be mapped at the same time on the same network, because mapping is independent of the network's physical implementation. To achieve an optimum design scheme for logical networks, the number of disjoint routes is introduced as the parameter used to optimize logical network topology. The number of disjoint routes is chosen so as to maximize total network efficiency. The optimum number of disjoint routes depends on the required QoS, VC-traffic characteristics, and traffic demand. By choosing the relevant cost characteristics, the network operator can easily maximize network efficiency and provide customers with the QoS they request at minimum cost. The proposed optimum multi-QoS network design scheme on a Full-Net architecture is an efficient solution to implementing multi-QoS control in an ATM network.

This paper gives several explicit formulas for the waiting times in each stage in an alternating-service, two-stage tandem queue (M/G/1 type queue) with a gate in the first stage and server vacations (or setup time). These formula are obtained by using simple conversion relationships between the performance measures. This study has been motivated by the performance evaluation of call (packet or message) processing in telecommunication switching systems.

A test system with a fuzzy logic controller is proposed to assure stable outgoing quality as well as to raise throughput. The test system controls the number of items under test in accordance with fuzzy information as well as statistical information about incoming quality and outgoing quality. First, an algorithm, minimum-minimum-the center of gravity-weighted mean method, is studied with both fuzzy reasoning rules and membership functions which are used for the control. Second, characteristics of the test system are verified and examined with computer simulations so that the fuzzy logic control rules are determined to realize sufficient sensitivity to process changes. Third, the control rules are installed in the test management processor which commands test equipment for testing very large scale integrated circuits, with programming language C. The authors have obtained satisfactory results through a trial run using a series of lots of 16 bit micro controller units in an IC manufacturing factory. Finally, they study the stability condition of the fuzzy test system.

Current testing has been proposed as an alternative technique for testing fully CMOS digital LSIs. Current testing has higher fault coverage than conventional stuck-at fault (SAF) testing and is more economical because it detects a wide range of faults and requires fewer test vectors than does SAF testing. We have proposed a current testing that measures the integral of the power supply current (IDD) during one clock period including the switching current. Since this method cannot be affected by the switching current, it can be used to test an LSI operating at a relatively high clock freuqnecy. This paper presents an improved current testing method for CMOS digital and analog LSIs. The method uses two current values (i.e., an upper limit and a lower limit) and judges the circuit under test to be faulty if the measured IDD is outside these limits. The proposed current testing is evaluated here for some kinds of faults (e.g., the bridging fault and the breaking fault) in digital and mixed-signal LSIs, and its efficiency of the current testing using SPICE3.

The firing squad synchronization problem is considered for defective cellular automata. A lower bound of time tf for the problem is derived. The state complexity to solve the problem is investigated and it is shown that the state set has to be arbitrary large to obtain solutions of time complexity (n). For memory-augmented defective cellular automata a tf-time solution is given.

A method to design one-dimensional cellular arrays to be used as TPG circuits of BIST is described. The interconnections between cells are not limited to adjacent ones but allowed to some neighbors. Completely regular structures that have full-transition coverages for every k-dimensional subspace of state variables are first shown. Then, almost regular arrays which can operate on maximum cycles are derived based on fast parallel implementations of LFSRs.

Conformance testing techniques are required for the efficient production of reliable communication protocols. A lot of conformance testing techniques have been developed. However, most of them can only decide whether an implemented protocol conforms to its specification. That is, the exact locations of faults are not determined by them. This paper presents some conditions that enable to find locations of multiple faults, and then proposes a test sequence generation technique under such conditions. The correctness proof and complexity analysis of the proposed technique are also given. The characteristics of this technique are to generate test sequences based on protocol specifications and interim test results, and to find locations of multiple faults in protocol implementations. Although the length of the test sequence generated by the proposed technique is a little longer than the one generated by the previous one, the class to which the proposed technique can be applied is larger than that to which the previous one can be applied.

The subject is the horizontal coil's temperature rise in DY for high frequency by being unavoidable for the tendency of more information on display monitor equipments. Writers made the temperature-balance model from a point of view that this temperature rise is coming from the heat rise and the conductivity, and we expressed the temperature rise of DY by using amount of the heat rise and conductivity characteristics of each element. Also, we indicated the method to decide about the selection of the wire size of coils, the section area and deflection sensitivity, with regard to reducing the temperature rise. We confirmed the effect of the temperature rise reduction by about 9 on products, under the condition of 64 kHz horizontal frequency.

In the final stages of VLSI testing, improved quality VLSI testing is an important subject for ensuring reliability in the forwarded VLSI market. On the other hand, developments in high integration technology have resulted in an increased number of functional blocks in VLSI devices and an increased number of gates for each terminal. Consequently, it has become more difficult to improve the quality of VLSI tests. We have developed a new test method in addition to conventional testing methods intended for improving the test coverage in VLSI tests. This new test method analyzes the relationship between IDDq (Quiescent Power Supply Current) of DUT and DUT failure by applying the concept of the toggle rate. Accordingly, in this paper we report that the results of IDDq testing confirm a correlation with defect level.