A method of sequential circuit synthesis is proposed for Single-Flux-Quantum (SFQ) digital circuits. Since all logic gates of SFQ digital circuits are driven by a clock signal, methods of sequential circuit synthesis for semiconductor digital circuits cannot derive the full power of high-throughput computation of SFQ circuit technology. In the method, a 'state module' consisting of a DFF and several AND gates is used. First, states of a sequential machine are encoded by one-hot encoding and state modules are assigned to the states one-by-one, and then, the modules are connected with each other according to the state transition. For the connection, Confluence Buffers (CBs), i.e., merger gates without clock signals are used. Consequently, gates driven by a clock signal are removed from its feedback loops, and therefore, a high-throughput SFQ sequential circuit is achieved. The experimental results on benchmark circuits show that compared with a conventional method for semiconductor digital circuits, the proposed method synthesizes circuits that work with 4.9 times higher clock frequency and have 17.3% more gates on average.

This paper reviews our progress on the high-Tc superconducting (HTS) sampler development, covering from the circuit design to the latest experimental data in the sinusoidal and pulse waveform measurements. A computer simulation has revealed that our sampler circuit with an improved design enables waveform measurement with the bandwidth over 100 GHz even with the thermal noise at around 40 K. Using the HTS sampler circuits fabricated employing an improved layout, we demonstrated waveform measurements for sinusoidal signals with frequencies of up to 50 GHz, the upper limit of the signal generator we used, both in the voltage-input-type system with a high-frequency input line and in the current-input-type one with a superconducting pickup coil. In the pulse measurement using an on-chip sampler, we succeeded in observing pico-second-order-wide single flux quantum (SFQ) current pulses, suggesting the potential bandwidth of our HTS sampler of more than 125 GHz.

Single flux quantum (SFQ) circuit elements have been designed and fabricated using the YBa2Cu3O7-δ ramp-edge junction technology. Logic operations of SFQ circuit elements, such as a toggle flip-flop (T-FF), a set-reset flip-flop (RS-FF), and a 96-junction Josephson transmission line (JTL), were successfully demonstrated, and dc supply current margins were confirmed up to temperatures higher than 30 K. The circuit layout was improved in order to suppress the critical current (Ic) spread that appears during the junction fabrication procedure. By employing the new circuit layout rule, correct operations at temperatures from 27 K to 34 K with dc supply current margins wider than 7% were confirmed for the T-FF with a single output. Moreover, the maximum operating frequencies of T-FFs were measured to be 360 GHz at 4.2 K and 210 GHz at 41 K, which are substantially higher than the values for the circuits with the conventional layout. According to the simulation result, the maximum operating frequency at 40 K was expected to be approximately 50% of the characteristic frequency at a bit error rate (BER) less than 10-6.

We propose a new method of logic synthesis for dual-rail RSFQ (rapid single-flux-quantum) digital circuits. RSFQ circuit technology is one of the strongest candidates for the next generation technology of digital circuits. For representing logic functions, we use a root-shared binary decision diagram (RSBDD) which is a directed acyclic graph constructed from binary decision diagrams. In the method, first we construct an RSBDD from given logic functions, and then reduce the number of nodes in the constructed RSBDD by variable re-ordering. Finally, we synthesize a dual-rail RSFQ circuit from the reduced RSBDD. We have implemented the method and have synthesized benchmark circuits. We have synthesized dual-rail circuits that consist of about 27% fewer logic elements than those synthesized by a Transduction-based method on average.

We have fabricated a multilayer structure for single flux quantum (SFQ) circuit application using a high-temperature superconductor (HTS). La0.2-Y0.9Ba1.9Cu3Ox (La-YBCO) base electrode layers were prepared by a dc or rf magnetron sputtering method. The reproducibility of film quality for dc-sputtered La-YBCO films was better than that for rf-sputtered films, and the dc sputtered films exhibited the average surface roughness Ra less than 1.0 nm and a Tc zero value of 88 K. By using the dc-sputtered La-YBCO films, a multilayer structure of SrSnO3/La-YBCO/SrSnO3/La-YBCO on MgO substrate with Ra below 2.0 nm was obtained. Interface-modified ramp-edge junctions with La0.2-Yb0.9Ba1.9Cu3Ox (La-YbBCO) counter electrodes have been fabricated by using this multilayer structure with dc-sputtered films. The fabricated junctions exhibited RSJ-type I-V characteristics with IcRn products of about 3 mV at 4.2 K. We also obtained a 1-σ Ic spread of 8% for a 1000-junction series-array. The sheet inductance values at 4.2 K for the base and counter electrodes on La-YBCO ground planes were 0.8 pH and 0.7 pH per square, respectively. Operation of several types of elementary SFQ circuits has been successfully demonstrated by using this multilayer structure.

To enable the use of passive transmission lines (PTLs) for the interconnection of single-flux-quantum (SFQ) circuits, we have implemented a driver and a receiver and have developed a method for designing SFQ circuits with passive interconnections. Basic components and properties of passive interconnections, such as the frequency characteristics of the driver and receiver, the PTL delay, and the crosstalk between PTLs, have been experimentally verified. Our developed components and design method have been applied to actual SFQ circuits, such as a 44 switch having block-to-block passive interconnections and a 22 switch having gate-to-gate passive interconnections. We have also shown the advantages of PTLs over Josephson transmission lines (JTLs). We also discuss the prospects of SFQ circuits having passive interconnections.

We have developed a planarization method applicable to large-scale superconductive Nb device fabrication. A planarized multi-layer wiring structure is obtained independently of the wiring size (width, length, and density) by combining three steps for fabricating an SiO2 insulator layer: bias-sputtering, chemical mechanical polishing, and etching with a reversal mask. Fabricated three-level wiring structures, consisting of 200- or 300-nm-thick Nb and SiO2 layers, had excellent layer flatness, and the leakage current (< 0.1 µA/cm2) between the Nb layers was sufficiently low. Two hundred chains of stepwise and stacked contacts yielded a sufficiently large critical current, typically more than 10 mA at 4.2 K.

We have designed a 44 Banyan switch using SFQ logic circuits. The switch is composed of three parts; one is an input buffer, the second is a contention solver which checks packet contention in a distribution network, and the third is a packet distribution network which distributes contention-free packets to their destination address. The packet distribution network is composed of Batcher-Banyan switch with the input buffer. The contention solver decides to send a data packet to the distribution network, using only internal routing tags which are added to packets in the switch. As the circuit is composed of two parts, the contention solver and the packet distribution network, the transfer rate is raised because it doesn't need to wait any more while a data packet passes through the distribution network. Simulation results using JSIM show that the switch circuit can operate at a clock frequency of 40 GHz.

We have designed a demultiplexer (DMUX) with a simple structure, high-speed operation circuits and large bias margins. By using a binary-tree architecture and clock-driven circuits, multi-channel DMUXs can be constructed easily from the same elemental circuits, i.e., 1-to-2 DMUX, consisting of a T-FF and a 1-to-2 switch. By applying cell-level optimization and Monte Carlo simulation, bias margins and operation frequency of the circuits were enlarged. Logical operations of the 1-to-2 DMUX and a multi-channel DMUX, e.g., a 1-to-4 DMUX were experimentally confirmed. It was also confirmed that the large margins, 33% of the DMUX (1-to-2 switch) was kept up regardless the degree of integration, and that the 1-to-2 DMUX can operate up to 46 GHz by using measure of average voltages across Josephson junctions.

We have fabricated a prototype of interface devices between SFQ and CMOS circuits using HTS quasi-particle injection devices. By the injection of quasi-particles, the bridge area becomes resistive and high voltage appears at the drain electrode. As a test of device operation, we applied the signal of a function generator to the gate electrode and observed that the device successfully repeated on/off operation. We also succeeded in explaining the device characteristics by considering the thermal effects.

We present a design framework of a high-end server based on Single-Flux-Quantum (SFQ) circuit technologies. The server proposed here has multiple microprocessors and memories, which are mounted on a single board or package and are connected each other by SFQ interconnection switches. The extremely large bandwidth up to 100 Gbps/channel in the interconnection will be realized because of high throughput nature of the SFQ circuits. SFQ memories or Josephson-CMOS hybrid memories are employed as the shared memory of the multiprocessor. The SFQ microprocessors are constructed based on the complexity-reduced (CORE) architecture, in which complexity of the system is eased in exchange for using a high clock rate of the SFQ circuits. The processor is so-called Java-processor that directly executes the Java Byte Codes. Assuming a proper advancement of the Nb/AlOx/Nb integrated circuit process technology, we have estimated that the power consumption of the server system including a cryocooler is reduced by a factor of twenty as compared to the future CMOS system with the same processor performance, while the SFQ system has 100 times of magnitude larger memory-processor bandwidth.

High-end telecommunication systems in the larger nationwide networks of the next decade will require routers having a packet switching throughput capacity of over 10 Tbps. In such future high-end routers, the packet switch, which is the biggest bottleneck of the router, will need higher processing speeds than semiconductor devices. We propose a high-end router system architecture using single flux quantum (SFQ) technology. This system consists of semiconductor line card units and an SFQ switch card unit. The features of this switch card architecture are (1) using internal speedup architecture to reduce effective loads in the network, (2) using a packet switch scheduler to attain non-blocking characteristics. This architecture can expand the switching capacity to a level greater than tens of Tbps scale, keeping with non-blocking characteristics.

We have designed the Half Adder (HA) circuit and the Carry Save Serial Adder (CSSA) circuit based on pipeline architecture. Our HA has the structure of a two-stage pipeline and consists of 160 Josephson Junctions (JJs). Our CSSA has the structure of a four-stage pipeline with a feedback loop and consists of 360 JJs. These circuits were fabricated by the NEC standard process. There are two issues which should be considered in the design. One is parameter spreads generated by the fabrication process and the other is leakage currents between the gates. We have introduced a parameter optimization method to deal with the parameter spreads. We have also inserted three stages of JTLs to reduce leakage currents. We have experimentally confirmed the correct operations of these circuits. The obtained bias margins were 33.1% for the HA and 24.6% for the CSSA.

We have proposed a top-down design methodology for the RSFQ logic circuits based on the Binary Decision Diagram (BDD). In order to show the effectiveness of the methodology, we have designed a small RSFQ microprocessor based on simple architecture. We have compared the performance of the 8-bit RSFQ microprocessor with its CMOS version. It was found that the RSFQ system is superior in terms of the operating speed though it requires extremely large area. We have also implemented and tested a 1-bit ALU that is one of the important components of the microprocessor and confirmed its correct operation.

We are developing a superconducting analog-to-digital converter (ADC) as a readout for high-resolution X-ray detectors based on a superconducting tunnel junction (STJ). The ADC has a sensitive front end which consists of a DC superconducting quantum interference device (SQUID). A signal current is digitized by this front end without using any preamplifiers. A single-flux-quantum (SFQ) pulse train whose frequency is proportional to the input current is launched by the front end, and integrated by a digital counter. The counter has a 10-bit resolution, and the integrated value is scanned and transferred to room-temperature processing modules with a frequency of 40 MHz. In this paper, the design of the ADC is described, and the preliminary results of the ADC performance test are shown. The performance of the STJ accompanied by the ADC is discussed in terms of the X-ray energy resolution.

We fabricated ramp-edge junctions with barriers by modifying surface and integrating ground-planes. The fabricated junctions had current-voltage characteristics consistent with the resistive shunted-junction model. We also obtained a 1-sigma spread in the critical current of 7.9% for 100 junctions at 4.2 K. The ground-plane reduced the sheet inductance of a stripline by a factor of 3. The quality of the ground-plane was improved by using an anneal in oxygen atmosphere after fabrication. The sheet inductance of a counter-electrode with a ground-plane was 1.0 pH per square at 4.2 K.

In this paper, we describe our SFQ circuit design and measurement carried out in SRL-ISTEC. We are studying an oversampling sigma-delta modulator and a counter-type decimation filter with multistage structure for developing AD converters for software-defined radio application. We are also developing a superconducting memory, whose peripheral circuits are constructed with SFQ circuits.

We report recent achievements in interfacing Josephson junction circuits with superconductor MicroStrip Lines (MSLs). We studied basic techniques that allow satisfactory operation of different devices with MSLs. Successful operation of the interfaces with very low error rate has been demonstrated even at the MSL resonant frequency.

Within the next few decades, high-end telecommunication systems on the larger nationwide network will require a switching capacity of over 5 Tbps. Advanced optical transmission technologies, such as wavelength division multiplexing (WDM) will support optical-fiber data transmission at such speeds. However, semiconductors may not be capable of high-throughput data switching because of the limitations by power consumption and operating speed, and pin count. Superconducting single flux quantum (SFQ) technology is a promising approach for overcoming these problems. This paper proposed an optical-electrical-SFQ hybrid switching system and a novel switch architecture. This architecture uses time-shifted internal speedup, shuffle and grouping exchange and a Batcher-Banyan switch. Our proposed switch consists of an interface circuit with small buffers, a Batcher sorter, a time-shift-speedup buffer (TSSB), a Banyan switch, and a slowdown buffer. Simulations showed good scalability up to 100 Tbps, which no router could ever offer such features.

This paper reviews the recent development of the Boolean Single Flux Quantum (BSFQ) circuits. BSFQ circuits perform Boolean operation based on the superconducting flux level, and let digital bits propagate in the form of 'set' and 'reset' pulses using dual-rail Josephson transmission line (JTL). Just the same as CMOS circuits BSFQ circuits do not require any local clock system for the operation gates, and thus are delay insensitive, and comparably simple in terms of the number of Josephson junctions. Implementation of basic BSFQ circuits, namely 'NOT,' 'AND,' 'OR,' 'XOR' gate, is described. These circuits have been experimentally tested, and their workability has been proven.