A generalization of compression via substring enumeration (CSE) for k-th order Markov sources with a finite alphabet is proposed, and an upper bound of the codeword length of the proposed method is presented. We analyze the worst case maximum redundancy of CSE for k-th order Markov sources with a finite alphabet. The compression ratio of the proposed method asymptotically converges to the optimal one for k-th order Markov sources with a finite alphabet if the length n of a source string tends to infinity.

SUMMARY This paper proposes a power-supply-noise-aware timing analysis and test pattern regeneration framework suitable for testing 3D IC. The proposed framework analyzes timing with reasonable accuracy at much faster speed than existing tools. This technique is very scalable because it is based on analytical functions, instead of solving nonlinear equations. The experimental results show, for small circuits, the error is less than 2% compared with SPICE. For large circuits, we achieved 272 times speed up compared with a commercial tool. For a large benchmark circuit (638K gates), we identified 88 risky patterns out of 31K test patterns. We propose a test pattern regeneration flow to replace those risky patterns with very little (or even no) penalty in fault coverage. Our test sets are shorter than commercial power-aware ATPG while the fault coverage is almost the same as power-unaware ATPG.

Peer-to-peer (P2P) networks have attracted increasing attention in the distribution of large-volume and frequently accessed content. In this paper, we mainly consider the problem of key leakage in secure P2P content distribution. In secure content distribution, content is encrypted so that only legitimate users can access the content. Usually, users (peers) cannot be fully trusted in a P2P network because malicious ones might leak their decryption keys. If the redistribution of decryption keys occurs, copyright holders may incur great losses caused by free riders who access content without purchasing it. To decrease the damage caused by the key leakage, the individualization of encrypted content is necessary. The individualization means that a different (set of) decryption key(s) is required for each user to access content. In this paper, we propose a P2P content distribution scheme resilient to the key leakage that achieves the individualization of encrypted content. We show the feasibility of our scheme by conducting a large-scale P2P experiment in a real network.

In this paper, we will present analysis on the fault erasure BP decoders based on the density evolution. In the fault BP decoder, the messages exchanged in a BP process are stochastically corrupted due to unreliable logic gates and flip-flops; i.e., we assume circuit components with transient faults. We derived a set of the density evolution equations for the fault erasure BP processes. Our density evolution analysis reveals the asymptotic behaviors of the estimation error probability of the fault erasure BP decoders. In contrast to the fault free cases, it is observed that the error probabilities of the fault erasure BP decoder converge to positive values, and that there exists a discontinuity in an error curve corresponding to the fault BP threshold. It is also shown that an message encoding technique provides higher fault BP thresholds than those of the original decoders at the cost of increased circuit size.

Faster-than-Nyquist (FTN) signaling is investigated for quasi-static flat fading massive multiple-input multiple-output (MIMO) systems. In FTN signaling, pulse trains are sent at a symbol rate higher than the Nyquist rate to increase the transmission rate. As a result, inter-symbol interference occurs inevitably for flat fading channels. This paper assesses the information-theoretically achievable rate of MIMO FTN signaling based on the optimum joint equalization and multiuser detection. The replica method developed in statistical physics is used to evaluate the achievable rate in the large-system limit, where the dimensions of input and output signals tend to infinity at the same rate. An analytical expression of the achievable rate is derived for general modulation schemes in the large-system limit. It is shown that FTN signaling does not improve the channel capacity of massive MIMO systems, and that FTN signaling with quadrature phase-shift keying achieves the channel capacity for all signal-to-noise ratios as the symbol period tends to zero.

As the increasing complexity of chip design, reducing both power consumption and clock skew becomes a crucial research topic in clock network synthesis. Among various clock network synthesis approaches, clock tree has less power consumption in comparison with clock mesh structure. In contrast, clock mesh has a higher tolerance of process variation and hence is easier to satisfy the clock skew constraint. To reduce the power consumption of clock mesh network, an effective way is to minimize the wire capacitance of stub wires. In addition, integration of clock gating and register clustering techniques on clock mesh network can further reduce dynamic power consumption. In this paper, under both enable timing constraint and clock skew constraint, we propose a methodology to reduce the switching capacitance by non-uniform clock mesh synthesis, clock gate insertion and register clustering. In comparison with clock mesh synthesis and clock gating technique individually, experimental results show that our methodology can improve both the clock skew and switching capacitance efficiently.

A Field Programmable Gate Array (FPGA) with fine-grained body biasing shows satisfactory static power reduction. Contrarily, the FPGA incurs high overhead because additional body bias selectors and electrical isolation regions are needed to program the threshold voltage (Vt) of elemental circuits such as MUX, buffer and LUT in the FPGA. In this paper, low overhead design of FPGA with fine-grained body biasing is described. The FPGA is designed and fabricated on 65-nm SOTB CMOS technology. By not only adopting a customized design rule specifying that reliability is verified by TEGs but downsizing a body bias selector, the FPGA tile area becomes small by 39% compared with the conventional design, resulting in 900 FPGA tiles with 4,4000 programmable Vt regions. In addition, the chip performance is evaluated by implementing 32-bit binary counter in the supply voltage range of 0.5V from 1.2V. The counter circuit operates at a frequency of 72MHz and 14MHz with the supply voltage of 1.2V and 0.5V respectively. The static power saving of 80% in elemental circuits of the FPGA at 0.5-V supply voltage and 0.5-V reverse body bias voltage is achieved in the best case. In the whole chip including configuration memory and body bias selector in addition to elemental circuits, effective static power reduction around 30% is maintained by applying 0.3-V reverse body bias voltage at each supply voltage.

The key escrow problem and high computational cost are the two major problems that hinder the wider adoption of hierarchical identity-based signature (HIBS) scheme. HIBS schemes with either escrow-free (EF) or online/offline (OO) model have been proved secure in our previous work. However, there is no much EF or OO scheme that has been evaluated experimentally. In this letter, several EF/OO HIBS schemes are considered. We study the algorithmic complexity of the schemes both theoretically and experimentally. Scheme performance and practicability of EF and OO models are discussed.

Current signature-based antivirus solutions have three limitations such as the large volume of signature database, privacy preservation, and computation overheads of signature matching. In this paper, we propose LigeroAV, a light-weight, performance-enhanced antivirus, suitable for pervasive environments such as mobile phones. LigeroAV focuses on detecting MD5 signatures which are more than 90% of signatures. LigeroAV offloads matching computation in the cloud server with up-to-dated signature database while preserving privacy level using the Bloom filter.

The design and performance evaluation is presented of a partially adaptive array that suppresses clutter from low elevation angles in atmospheric radar observations. The norm-constrained and directionally constrained minimization of power (NC-DCMP) algorithm has been widely used to suppress clutter in atmospheric radars, because it can limit the signal-to-noise ratio (SNR) loss to a designated amount, which is the most important design factor for atmospheric radars. To suppress clutter from low elevation angles, adding supplemental antennas that have high response to the incoming directions of clutter has been considered to be more efficient than to divide uniformly the high-gain main array. However, the proper handling of the gain differences of main and sub-arrays has not been well studied. We performed numerical simulations to show that using the proper gain weighting, the sub-array configuration has better clutter suppression capability per unit SNR loss than the uniformly divided arrays of the same size. The method developed is also applied to an actual observation dataset from the MU radar at Shigaraki, Japan. The properly gain-weighted NC-DCMP algorithm suppresses the ground clutter sufficiently with an average SNR loss of about 1 dB less than that of the uniform-gain configuration.

Reliable wireless communication often requires accurate knowledge of the underlying multipath channels. Numerous measurement campaigns have shown that physical multipath channels tend to exhibit a sparse structure. Conventional blind channel identification (BCI) strategies such as the least squares, which are known to be optimal under the assumption of rich multipath channels, are ill-suited to exploiting the inherent sparse nature of multipath channels. Recently, l1-norm regularized least-squares-type approaches have been proposed to address this problem with a single parameter governing all coefficients, which is equivalent to maximum a posteriori probability estimation with a Laplacian prior for the channel coefficients. Since Laplace prior is not conjugate to the Gaussian likelihood, no closed form of Bayesian inference is possible. Following a different approach, this paper deals with blind channel identification of a single-input multiple-output (SIMO) system based on sparse Bayesian learning (SBL). The inherent sparse nature of wireless multipath channels is exploited by incorporating a transformative cross relation formulation into a general Bayesian framework, in which the filter coefficients are governed by independent scalar parameters. A fast iterative Bayesian inference method is then applied to the proposed model for obtaining sparse solutions, which completely eliminates the need for computationally costly parameter fine tuning, which is necessary in the l1-norm regularization method. Simulation results are provided to demonstrate the superior effectiveness of the proposed channel estimation algorithm over the conventional least squares (LS) scheme as well as the l1-norm regularization method. It is shown that the proposed algorithm exhibits superior estimation performance compared to both LS and l1-norm regularization methods.

The time taken for processor simulation can be drastically reduced by selecting simulation points, which are dynamic sections obtained from the simulation result of processors. The overall behavior of the program can be estimated by simulating only these sections. The existing methods to select simulation points, such as SimPoint, used for selecting simulation points are deductive and based on the idea that dynamic sections executing the same static section of the program are of the same phase. However, there are counterexamples for this idea. This paper proposes an inductive method, which selects simulation points from the results obtained by pre-simulating several processors with distinctive microarchitectures, based on assumption that sections in which all the distinctive processors have similar istructions per cycle (IPC) values are of the same phase. We evaluated the first 100G instructions of SPEC 2006 programs. Our method achieved an IPC estimation error of approximately 0.1% by simulating approximately 0.05% of the 100G instructions.

This letter investigates the physical layer security for a buffer-aided underlay cooperative cognitive radio network in the presence of an eavesdropper, wherein, the relay is equipped with a buffer so that it can store packets received from the secondary source. To improve the secure performance of cognitive radio networks, we propose a novel cognitive secure link selection scheme which incorporates the instantaneous strength of the wireless links as well as the status of relay's buffer, the proposed scheme adapts the link selection decision on the strongest available link by dynamically switching between relay reception and transmission. Closed-form expressions of secrecy outage probability (SOP) for cognitive radio network is obtained based on the Markov chain. Numerical results demonstrate that the proposed scheme can significantly enhance the secure performance compared to the conventional relay selection scheme.

This paper presents a novel non-native speech synthesis technique that preserves the individuality of a non-native speaker. Cross-lingual speech synthesis based on voice conversion or Hidden Markov Model (HMM)-based speech synthesis is a technique to synthesize foreign language speech using a target speaker's natural speech uttered in his/her mother tongue. Although the technique holds promise to improve a wide variety of applications, it tends to cause degradation of target speaker's individuality in synthetic speech compared to intra-lingual speech synthesis. This paper proposes a new approach to speech synthesis that preserves speaker individuality by using non-native speech spoken by the target speaker. Although the use of non-native speech makes it possible to preserve the speaker individuality in the synthesized target speech, naturalness is significantly degraded as the synthesized speech waveform is directly affected by unnatural prosody and pronunciation often caused by differences in the linguistic systems of the source and target languages. To improve naturalness while preserving speaker individuality, we propose (1) a prosody correction method based on model adaptation, and (2) a phonetic correction method based on spectrum replacement for unvoiced consonants. The experimental results using English speech uttered by native Japanese speakers demonstrate that (1) the proposed methods are capable of significantly improving naturalness while preserving the speaker individuality in synthetic speech, and (2) the proposed methods also improve intelligibility as confirmed by a dictation test.

The main contribution of this paper is to present a work-optimal parallel algorithm for LZW decompression and to implement it in a CUDA-enabled GPU. Since sequential LZW decompression creates a dictionary table by reading codes in a compressed file one by one, it is not easy to parallelize it. We first present a work-optimal parallel LZW decompression algorithm on the CREW-PRAM (Concurrent-Read Exclusive-Write Parallel Random Access Machine), which is a standard theoretical parallel computing model with a shared memory. We then go on to present an efficient implementation of this parallel algorithm on a GPU. The experimental results show that our GPU implementation performs LZW decompression in 1.15 milliseconds for a gray scale TIFF image with 4096×3072 pixels stored in the global memory of GeForce GTX 980. On the other hand, sequential LZW decompression for the same image stored in the main memory of Intel Core i7 CPU takes 50.1 milliseconds. Thus, our parallel LZW decompression on the global memory of the GPU is 43.6 times faster than a sequential LZW decompression on the main memory of the CPU for this image. To show the applicability of our GPU implementation for LZW decompression, we evaluated the SSD-GPU data loading time for three scenarios. The experimental results show that the scenario using our LZW decompression on the GPU is faster than the others.

This paper presents a scheme that digitally cancels the unwanted phase components generated by the transmitter's laser and the receiver's local oscillator laser; such components place a substantial limit on the performance of coherent transceivers monolithically integrated with lasers in a photonic integrated circuit (PIC). Our cancellation proposal adopts the orthogonal polarization approach to provide a reference that is uncorrelated with the data signal. We elaborate on the principle of our proposal and its digital signal processing (DSP) algorithm. Experiments on a VCSEL with a linewidth of approximately 300MHz verify that our proposal can overcome the inherent phase noise limitations indicated by simulations and experiments. Our cancellation algorithm in conjunction with CMA-based polarization control is demonstrated and evaluated to confirm the feasibility of our proposal. The achievement of greatly relaxed laser linewidth will offer a significant benefit in offsetting the technical and cost requirements of coherent transceiver PICs with lasers. Therefore, our cancellation proposal is an enabling technology for the successful deployment of future coherent-based passive optical network (PON) systems.

In this study, we develop a new algorithm for decoding binary linear codes for symbol-pair read channels. The symbol-pair read channel was recently introduced by Cassuto and Blaum to model channels with higher write resolutions than read resolutions. The proposed decoding algorithm is based on linear programming (LP). For LDPC codes, the proposed algorithm runs in time polynomial in the codeword length. It is proved that the proposed LP decoder has the maximum-likelihood (ML) certificate property, i.e., the output of the decoder is guaranteed to be the ML codeword when it is integral. We also introduce the fractional pair distance dfp of the code, which is a lower bound on the minimum pair distance. It is proved that the proposed LP decoder corrects up to ⌈dfp/2⌉-1 errors.

nMOS-type and pMOS-type silicon avalanche photodiodes (APDs) were fabricated by standard 0.18µm CMOS process, and the current-voltage characteristic and the frequency response of the APDs with and without guard ring structure were measured. The role of the guard ring is cancellation of photo-generated carriers in a deep layer and a substrate. The bandwidth of the APD is enhanced with the guard ring structure at a sacrifice of the responsivity. Based on comparison of nMOS-type and pMOS-type APDs, the nMOS-type APD is more suitable for high-speed operation. The bandwidth is enhanced with decreasing the spacing of interdigital electrodes due to decreased carrier transit time and with decreasing the detection area and the PAD size for RF probing due to decreased device capacitance. The maximum bandwidth was achieved with the avalanche gain of about 10. Finally, we fabricated a nMOS-type APD with the electrode spacing of 0.84µm, the detection area of 10×10µm2, the PAD size for RF probing of 30×30µm2, and with the guard ring structure. The maximum bandwidth of 8.4GHz was achieved along with the gain-bandwidth product of 280GHz.

Ordinal classification is a class of special tasks in machine learning and pattern recognition. As to ordinal classification, there is an ordinal structure among different decision values. The monotonicity constraint between features and decision should be taken into account as the fundamental assumption. However, in real-world applications, this assumption may be not true. Only some candidate features, instead of all, are monotonic with decision. So the existing feature selection algorithms which are designed for nominal classification or monotonic classification are not suitable for ordinal classification. In this paper, we propose a feature selection algorithm for ordinal classification based on considering the non-monotonic and monotonic features separately. We first introduce an assumption of hybrid monotonic classification consistency and define a feature evaluation function to calculate the relevance between the features and decision for ordinal classification. Then, we combine the reported measure and genetic algorithm (GA) to search the optimal feature subset. A collection of numerical experiments are implemented to show that the proposed approach can effectively reduce the feature size and improve the classification performance.

This paper proposes a low power single-ended successive approximation register (SAR) analog-to-digital converter (ADC) to replace the only analog active circuit, the comparator, with a digital circuit, which is an inverter-based comparator. The replacement helps possible design automation. The inverter threshold voltage variation impact is minimal because an SAR ADC has only one comparator, and many applications are either insensitive to the resulting ADC offset or easily corrected digitally. The proposed resetting approach mitigates leakage when the input is close to the threshold voltage. As an intrinsic headroom-free, and thus low-rail-voltage, friendly structure, an inverter-based comparator also occupies a small area. Furthermore, an 11-bit ADC was designed and manufactured through a 0.35-µm CMOS process by adopting a low-power switching procedure. The ADC achieves an FOM of 181fJ/Conv.-step at a 25kS/s sampling rate when the supply voltage VDD is 1.2V.