We propose a low cost and stand-alone platform-based SoC for H.264/AVC decoder, whose target is practical mobile applications such as a handheld video player. Both low cost and stand-alone solutions are particularly emphasized. The SoC, consisting of RISC core and decoder core, has advantages in terms of flexibility, testability and various I/O interfaces. For decoder core design, the proposed H.264/AVC coprocessor in the SoC employs a new block pipelining scheme instead of a conventional macroblock or a hybrid one, which greatly contribute to reducing drastically the size of the core and its pipelining buffer. In addition, the decoder schedule is optimized to block level which is easy to be programmed. Actually, the core size is reduced to 138 KGate with 3.5 kbyte memory. In our practical development, a single external SDRAM is sufficient for both reference frame buffer and display buffer. Various peripheral interfaces such as a compact flash, a digital broadcast receiver and a LCD driver are also provided on a chip.

The present paper describes a method for the construction of a zero-correlation zone sequence set from a perfect sequence. Both the cross-correlation function and the side-lobe of the auto-correlation function of the proposed sequence sets are zero for phase shifts within the zero-correlation zone. These sets can be generated from an arbitrary perfect sequence, the length of which is the product of a pair of odd integers ((2n+1)(2k+1) for k ≥ 1 and n ≥ 0). The proposed sequence construction method can generate an optimal zero-correlation zone sequence set that achieves the theoretical bounds of the sequence member size given the size of the zero-correlation zone and the sequence period. The peak in the out-of-phase correlation function of the constructed sequences is restricted to be lower than the half of the power of the sequence itself. The proposed sequence sets could successfully provide CDMA communication without co-channel interference, or, in an ultrasonic synthetic aperture imaging system, improve the signal-to-noise ratio of the acquired image.

Random variations in Id-Vg characteristics of MOS transistors in an LSI chip are shown to be concisely characterized by using only 3 transistor parameters (Vth, β0, vSAT) in the MOS level 3 SPICE model. Statistical analyses of the transistor parameters show that not only the threshold voltage variation, ΔVth, but also the current factor variation, Δβ0, independently induces Id-variation, and that Δβ0 is negatively correlated with the saturation velocity variation, ΔvSAT. Using these results, we have proposed a simple method that effectively takes the correlation between parameters into consideration when creating statistical model parameters for designing a circuit. Furthermore, we have proposed a sensitivity analysis methodology for estimating the process window of SRAM cell operation taking transistor variability into account. By applying the concise statistical model parameters to the sensitivity analysis, we are able to obtain valid process windows without the large volume of data-processing and long turnaround time associated with the Monte Carlo simulation. The process window was limited not only by ΔVth, but also by Δβ0 which enhanced the failure region in the process window by 20%.

This paper proposes a novel Behavioral Synthesis method that tries to reduce the number of clock cycles under clock cycle time and total functional unit area constraints using special functional units efficiently. Special functional units are designed to have shorter delay and/or smaller area than the cascaded basic functional units for specific operation patterns. For example, a Multiply-Accumulator is one of them. However, special functional units may have less flexibility for resource sharing because intermediate operation results may not be able to be obtained. Hence, almost all conventional methods can not handle special functional units efficiently for the reduction of clock cycles in practical time, especially under a tight area constraint. The proposed method makes it possible to solve module selection, scheduling, and functional unit allocation problems using special functional units in practical time with some heuristics. Experimental results show that the proposed method has achieved maximally 33% reduction of the cycles for a small application and 14% reduction for a realistic application in practical time.

Bone Mineral Density (BMD) is an indicator of osteoporosis that is an increasingly serious disease, particularly for the elderly. To calculate BMD, we need to measure the volume of the femur in a noninvasive way. In this paper, we propose a noninvasive bone volume measurement method using x-ray attenuation on radiography and medical knowledge. The absolute thickness at one reference pixel and the relative thickness at all pixels of the bone in the x-ray image are used to calculate the volume and the BMD. First, the absolute bone thickness of one particular pixel is estimated by the known geometric shape of a specific bone part as medical knowledge. The relative bone thicknesses of all pixels are then calculated by x-ray attenuation of each pixel. Finally, given the absolute bone thickness of the reference pixel, the absolute bone thickness of all pixels is mapped. To evaluate the performance of the proposed method, experiments on 300 subjects were performed. We found that the method provides good estimations of real BMD values of femur bone. Estimates shows a high linear correlation of 0.96 between the volume Bone Mineral Density (vBMD) of CT-SCAN and computed vBMD (all P<0.001). The BMD results reveal 3.23% difference in volume from the BMD of CT-SCAN.

This paper proposes an on-chip loop gain variation compensation architecture for a clock and data recovery (CDR) LSI. The CDR LSI using the proposed architecture can meet the jitter specifications recommended in ITU-T G.958 under wide variation of temperature and supply voltage. The relation between the jitter specifications and the loop gain is derived theoretically. Gain-variation characteristics of component circuits are studied by circuit simulation. The proposed architecture uses voltage controllers to reduce the gain variation of the LC voltage controlled oscillator (LC-VCO) circuit and charge-pump circuit. The voltage controllers are designed to have a first-order positive coefficient to temperature, which is found by an analysis of the gain variation characteristics. An STM-16 CDR with the proposed architecture is implemented in 0.20-µm fully depleted CMOS/SOI. The CDR shows a wide capture range of 140 MHz and meets both the jitter transfer and the jitter tolerance specifications in the ambient temperature range from -40 to 85 and with the supply voltage variation of 6%.

This work presents an ultra-low-voltage ultra-low-power weak inversion composite MOS transistor. The steady state power consumption and the linear swing signal of the composite transistor are comparable to a single transistor, whereas presenting very high output impedance. This work also presents two interesting applications for the composite transistor; a 1:1 current mirror and an extremely low power temperature sensor, a thermistor. Both implementations are verified in a standard 0.35-µm TSMC CMOS process. The current mirror presents high output impedance, comparable to the cascode configuration, which is highly desirable to improve gain and PSRR of amplifiers circuits, and mirroring relation in current mirrors.

Space-time block codes (STBCs) from coordinate interleaved orthogonal designs (CIODs) have attracted a great deal of attention due to their full-diversity and linear maximum likelihood (ML) decodability. In this letter, we propose a simple detection technique, particularly for full-rate STBCs from CIODs to overcome the performance degradation caused by time-selective fading channels. Furthermore, we evaluate the effects of time-selective fading channels and imperfect channel estimation on STBCs from CIODs by using a newly-introduced index, the results of which demonstrate that full-rate STBCs from CIODs are more robust against time-selective fading channels than conventional full-rate STBCs.

This paper deals with a TM plane wave reflection and transmission from a one-dimensional random slab with stratified fluctuation by means of the stochastic functional approach. Based on a previous manner [IEICE Trans. Electron. E88-C, 4, pp.713-720, 2005], an explicit form of the random wavefield is obtained in terms of a Wiener-Hermite expansion with approximate expansion coefficients (Wiener kernels) under small fluctuation. The optical theorem and coherent reflection coefficient are illustrated in figures for several physical parameters. It is then found that the optical theorem by use of the first two or three order Wiener kernels holds with good accuracy and a shift of Brewster's angle appears in the coherent reflection.

To precisely model the time dependency of features is one of the important issues for speech recognition. Segmental unit input HMM with a dimensionality reduction method has been widely used to address this issue. Linear discriminant analysis (LDA) and heteroscedastic extensions, e.g., heteroscedastic linear discriminant analysis (HLDA) or heteroscedastic discriminant analysis (HDA), are popular approaches to reduce dimensionality. However, it is difficult to find one particular criterion suitable for any kind of data set in carrying out dimensionality reduction while preserving discriminative information. In this paper, we propose a new framework which we call power linear discriminant analysis (PLDA). PLDA can be used to describe various criteria including LDA, HLDA, and HDA with one control parameter. In addition, we provide an efficient selection method using a control parameter without training HMMs nor testing recognition performance on a development data set. Experimental results show that the PLDA is more effective than conventional methods for various data sets.

In this paper, signal processing techniques which can be applied to automatic speech recognition to improve its robustness are reviewed. The choice of signal processing techniques is strongly dependent on the scenario of the applications. The analysis of scenario and the choice of suitable signal processing techniques are shown through two examples.

Complex speech analysis for an analytic speech signal can accurately estimate the spectrum in low frequencies since the analytic signal provides spectrum only over positive frequencies. The remarkable feature makes it possible to realize more accurate F0 estimation using complex residual signal extracted by complex-valued speech analysis. We have already proposed F0 estimation using complex LPC residual, in which the autocorrelation function weighted by AMDF was adopted as the criterion. The method adopted MMSE-based complex LPC analysis and it has been reported that it can estimate more accurate F0 for IRS filtered speech corrupted by white Gauss noise although it can not work better for the IRS filtered speech corrupted by pink noise. In this paper, robust complex speech analysis based on ELS (Extended Least Square) method is introduced in order to overcome the drawback. The experimental results for additive white Gauss or pink noise demonstrate that the proposed algorithm based on robust ELS-based complex AR analysis can perform better than other methods.

This study proposes a method to decompose a signal into a set of periodic signals. The proposed decomposition method imposes a penalty on the resultant periodic subsignals in order to improve the sparsity of decomposition and avoid the overestimation of periods. This penalty is defined as the weighted sum of the l2 norms of the resultant periodic subsignals. This decomposition is approximated by an unconstrained minimization problem. In order to solve this problem, a relaxation algorithm is applied. In the experiments, decomposition results are presented to demonstrate the simultaneous detection of periods and waveforms hidden in signal mixtures.

In this paper, we propose a recursive filtering algorithm to restore monochromatic images which are corrupted by general dependent additive noise. It is assumed that the equation which describes the image field is not available and a filtering algorithm is obtained using the information provided by the covariance functions of the signal, noise that affects the measurement equation, and the fourth-order moments of the signal. The proposed algorithm is obtained by an innovation approach which provides a simple derivation of the least mean-squared error linear estimators. The estimation of the grey level in each spatial coordinate is made taking into account the information provided by the grey levels located on the row of the pixel to be estimated. The proposed filtering algorithm is applied to restore images which are affected by general signal-dependent additive noise.

We developed test data compression scheme for scan-based BIST, aiming to compress test stimuli and responses by more than 100 times. As scan-BIST architecture, we adopt BIST-Aided Scan Test (BAST), and combines four techniques: the invert-and-shift operation, run-length compression, scan address partitioning, and LFSR pre-shifting. Our scheme achieved a 100x compression rate in environments where Xs do not occur without reducing the fault coverage of the original ATPG vectors. Furthermore, we enhanced the masking logic to reduce data for X-masking so that test data is still compressed to 1/100 in a practical environment where Xs occur. We applied our scheme to five real VLSI chips, and the technique compressed the test data by 100x for scan-based BIST.

This paper proposes an approach to cope with temporal power/ground voltage fluctuation for static timing analysis. The proposed approach replaces temporal noise with an equivalent power/ground voltage. This replacement reduces complexity that comes from the variety in noise waveform shape, and improves compatibility of power/ground noise aware timing analysis with conventional timing analysis framework. Experimental results show that the proposed approach can compute gate propagation delay considering temporal noise within 10% error in maximum and 0.5% in average.

By utilizing the second and fourth order linear prediction errors, a novel estimator for a single noisy sinusoid is devised. The frequency estimate is obtained from a solving a cubic equation and a simple root selection procedure is provided. Asymptotical variance of the estimated frequency is derived and confirmed by computer simulations. It is demonstrated that the proposed estimator is superior to the reformed Pisarenko harmonic decomposer, which is the improved version of Pisarenko harmonic decomposer.

Error concealment at a decoder is an efficient method to reduce the degradation of visual quality caused by channel errors. In this paper, we propose a novel spatio-temporal error concealment algorithm based on the spatial-temporal fading (STF) scheme which has been recently introduced. Although STF achieves good performance for the error concealment, several drawbacks including blurring still remain in the concealed blocks. To alleviate these drawbacks, in the proposed method, hybrid approaches with adaptive weights are proposed. First, the boundary matching algorithm and the decoder motion vector estimation which are well-known temporal error concealment methods are adaptively combined to compensate for the defect of each other. Then, an edge preserved method is utilized to reduce the blurring effects caused by the bilinear interpolation for spatial error concealment. Finally, two concealed results obtained by the hybrid spatial and temporal error concealment are pixel-wisely blended with adaptive weights. Experimental results exhibit that the proposed method outperforms conventional methods including STF in terms of the PSNR performance as well as subjective visual quality, and the computational complexity of the proposed method is similar to that of STF.

In general, we do not know which fault model can explain the cause of the faulty values at the primary outputs in a circuit under test before starting diagnosis. Moreover, under Built-In Self Test (BIST) environment, it is difficult to know which primary output has a faulty value on the application of a failing test pattern. In this paper, we propose an effective diagnosis method on multiple fault models, based on only pass/fail information on the applied test patterns. The proposed method deduces both the fault model and the fault location based on the number of detections for the single stuck-at fault at each line, by performing single stuck-at fault simulation with both passing and failing test patterns. To improve the ability of fault diagnosis, our method uses the logic values of lines and the condition whether the stuck-at faults at the lines are detected or not by passing and failing test patterns. Experimental results show that our method can accurately identify the fault models (stuck-at fault model, AND/OR bridging fault model, dominance bridging fault model, or open fault model) for 90% faulty circuits and that the faulty sites are located within two candidate faults.

We investigate the MIMO broadcast channels with imperfect channel knowledge due to estimation error and much more users than transmit antennas to exploit multiuser diversity. The channel estimation error causes the interference among users, resulting in the sum-rate loss. A tight upper bound of this sum-rate loss based on zeroforcing beamforming is derived theoretically. This bound only depends on the channel estimation quality and transmit antenna number, but not on the user number. Based on this upper bound, we show this system maintains full multiuser diversity, and always benefits from the increasing transmit power.