In this paper we present a rigorous vector 3D lithography simulator METROPOLE-3D which is designed to run moderately fast on conventional engineering workstations. METROPOLE-3D solves Maxwell's equations rigorously in three dimensions to model how the non-vertically incident light is scattered and transmitted in non-planar structures. METROPOLE-3D consists of several simulation modules: photomask simulator, exposure simulator, post-exposure baking module and 3D development module. This simulator has been applied to a wide range of pressing engineering problems encountered in state-of-the-art VLSI fabrication processes, such as layout printability/manufacturability analysis including reflective notching problems and optimization of an anti-reflective coating (ARC) layer. Finally, a 3D contamination to defect transformation study was successfully performed using our rigorous simulator.

In this paper, a novel variable-rate vector quantizer (VQ) design algorithm using fuzzy clustering technique is presented. The algorithm, termed fuzzy entropy-constrained VQ (FECVQ) design algorithm, has a better rate-distortion performance than that of the usual entropy-constrained VQ (ECVQ) algorithm for variable-rate VQ design. When performing the fuzzy clustering, the FECVQ algorithm considers both the usual squared-distance measure, and the length of channel index associated with each codeword so that the average rate of the VQ can be controlled. In addition, the membership function for achieving the optimal clustering for the design of FECVQ are derived. Simulation results demonstrate that the FECVQ can be an effective alternative for the design of variable-rate VQs.

We introduce an extended EZW coder that uses flexible zerotree coding of wavelet coefficients. A flexible parent-child relationship is defined so as to exploit spatial dependencies within a subband as well as hierarchical dependencies among multi-scale subbands. The new relationship is based on a particular statistics that a large coefficient is more likely to have large coefficients in its neighborhood in terms of space and scale. In the flexible relationship, a parent coefficient in a subband relates to four child coefficients in the next finer subband in the same orientation. If each of the children is larger than a given threshold, the parent extends its parentship to the neighbors close to its conventional children. A probing bit is introduced to indicate whether a significant parent has significant children to be scanned. This enables us to avoid excessive scan of insignificant coefficients. Also, produced symbols are re-symbolized into simple variable-length binary codes to remove some redundancy according to a pre-defined rule. As a result, the wavelet coefficients can be described with a small number of binary symbols. This binary symbol stream gives a competitive performance without an additional entropy coding and thus a fast encoding/decoding is possible. Moreover, the binary symbols can be more compressed by an adaptive arithmetic coding. Our experimental results are given in both binary-coded mode and arithmetic-coded mode. Also, these results are compared with those of the EZW coder.

In this paper, quasi-Gaussian filter, quasi-median filter and locally adaptive filters are introduced. A new adaptive vector filter based on noise estimate is proposed to suppress Gaussian and/or impulse noise. To estimate the type and degree of noise corruption, a noise detector and an edge detector are introduced, and two key parameters are obtained to characterize noise in color image. After globally estimating the type and degree of noise corruption, different locally adaptive filters are properly chosen for image enhancement. All noisy images, used to test filters in experiments, are generated by PaintShopPro and Photoshop software. Experimental results show that the new adaptive filter performs better in suppressing noise and preserving details than the filter in Photoshop software and other filters.

As wireless communication is penetrating every corner of the globe, the optimum design and accurate analysis of RF, power semiconductor devices become one of the biggest challenges in EDA and TCAD (Technology CAD) tool development. The performance gauge for these devices is quite different from that for either digital or analog devices aimed at small-signal applications in that the power gain, efficiency, and distortion (or the range of linearity) are the utmost design concerns. In this article, the methodology and mathematical foundation for numerical analysis of large signal distortion at the device simulation level are discussed. Although the harmonic balance (HB) method has long been used in circuit simulation for large signal distortion analysis, the implementation of the same method in device simulation faces daunting challenges, among which are the tremendous computational cost and memory storage management. But the benefits from conducting such a device level simulation are also obvious--for the first time, the impact of technology and structural variation of device on large signal performance can directly be assessed. The necessary steps to make the HB analysis feasible in device simulation are outlined and algorithmic improvement to ease the computation/storage burden is discussed. The applications of the device simulator for various RF power devices, including GaAs MESFETs and silicon LDMOS (lateral diffusion MOS) are presented, and the insight gained from such an analysis is provided.

A complex modular process flow was developed for PRISM technology to permit increased system integration. In order to combine the required functions--submicron CMOS Logic, Nonvolatile Memories, Precision Linear, and Power Drivers--on a monolithic silicon chip, a highly structured, systematic approach to process synthesis was developed. TCAD tools were used extensively for process design and verification. The 60 V LDMOS power transistor and the Flash memory cell built in the technology will be described to illustrate the process synthesis methodology.

A device simulator that simulates device performance in the cyclic bias steady state was developed, and it was applied to GaAs hetero-junction FET (HJFET) pulse pattern effect. Although there is a large time-constant difference between the pulse signals and deep trap reactions, the simulator searches the cyclic bias steady states at about 30 iterations. A non-linear shift in the drain current level with the mark ratio was confirmed, which has been estimated from the rate equation of electron capture and emission based on Shockley-Read-Hall statistics for deep traps.

In this paper, by making good use of the parallel-transit-evaluation algorithm and sparsity of the connection between neurons, a pipeline structure is successfully introduced to the sequential Boltzmann machine processor. The novel structure speeds up nine times faster than the previous one, with only the 12% rise in hardware resources under 10,000 neurons. The performance is confirmed by designing it using 1.2 µm CMOS process standard cells and analyzing the probability of state-change.

Existing multimedia processors having millions of transistors are not suitable for portable multimedia services and existing fixed-point DSP chips having fixed data formats are not appropriate for multimedia applications. This paper proposes a multimedia fixed-point DSP (MDSP) chip for portable multimedia services and its chip implementation. MDSP employs parallel processing techniques, such as SIMD, vector processing, and DSP techniques. MDSP can handle 8-, 16-, 32- or 40-bit data and can perform two MAC operations in parallel. In addition, MDSP can complete two vector operations with two data movements in a cycle. With these features, MDSP can handle both 2-D video signal processing and 1-D signal processing. The prototype MDSP chip has 68,831 gates, has been fabricated, and is running at 30 MHz.

In this paper, near real time digital radiography system was implemented for the automatic verification of local errors between simulation plan and radiation therapy. Portal image could be acquired through video camera, image board and PC after therapy radiation was converted into light by a metal/fluorescent screen. Considering the divergence according to the distance between the source and the plate, we made a 340 340 12 cm3 basis point plate on which five rods of 4 cm height and 8 mm diameter lead (Pb) were built to display reference points on the simulator and the portal image. We converted the portal image into the binary image using the optimal threshold value which was gotten through the histogram analysis of the acquired portal image using the basis point plate. we got the location information of the iso-center and basis points from the binary image, and removed the systematic errors which were from the differences between the simulation plan and the portal image. Field size which was measured automatically by optimal threshold portal image, was verified with simulation plan. Anatomic errors were automatically detected and verified with the normalized simulation and the portal image by pattern matching method after irradiating a part of the radiation. Therapy efficiency was improved and radiation side effects were reduced by these techniques, so exact radiation treatment are expected.

This paper presents a new data path synthesis algorithm which takes into account simultaneously three important design criteria: testability, design area, and total execution time. We define a goodness measure on the testability of a circuit based on three rules of thumb introduced in prior work on synthesis for testability. We then develop a stepwise refinement synthesis algorithm which carries out the scheduling and allocation tasks in an integrated fashion. Experimental results for benchmark and other circuit examples show that we were able to enhance the testability of circuits significantly with very little overheads on design area and execution time.

Secret information stored in a tamperfree device is revealed during the decryption or signature generation processes due to fault-based attack. In this paper, based on the coding approach, we propose a new fault-resistant system which enables any fault existing in modular multiplication and exponentiation computations to be detected with a very high probability. The proposed method can be used to implement all crypto-schemes whose basic operations are modular multiplications for resisting both memory and computational fault-based attacks with a very low computational overhead.

The full liquid crystal display (LCD) simulation with real transistors and other active components is unrealistic. Because a flat panel display (FPD) includes thin-film-transistors (TFT's) whose number is, at least, the number of total pixels. It hits the simulation limit of SPICE if the number of transistors are more than 0.5 million. This paper demonstrates a new, fast, and effective simulation method for a full LCD panel. The method makes it possible to simulate large LCD panels whereas the conventional method cannot handle. The simulation circuit consists of a-Si TFT model presented earlier, the liquid crystal, the pixel macro models, and interconnects. We show the model parameter extraction and the pixel macro modeling process associated with the simulation results. Using the simulation method presented here some larger LCD panels can be accurately simulated in less than a minute on a workstation.

Equipment simulation can provide valuable support in reactor design and process optimization. This article describes the physical and chemical models used in this technique and the current state of the art of the available software tools is reviewed. Moreover, the potential of equipment simulation will be highlighted by means of three recent examples from advanced quarter micron silicon process development. These include a vertical batch reactor for LPCVD of arsenic doped silicon oxide, a multi station tungsten CVD reactor, and a plasma reactor for silicon etching.

We have improved the mechanical reliability of deep-submicron semiconductor devices by applying a simulation technique. Typical kinds of damages that reduce the reliability are dislocations in silicon substrates, delamination or cracking of thin films, and deterioration of electronic characteristics of devices. The mechanical stress that develops in device structures is caused by not only mismatches in thermal expansion coefficients among thin film materials but also intrinsic stress of thin films such as poly-silicon and silicides. Fine patterning by dry etching makes sharp edges and they also cause stress concentration and thus high stress. The manufacturing processes in which stress mainly develops are isolation, gate formation, and interconnect formation. We have developed methods for reducing the stress in each of the above-mentioned process. This stress reduction is very effective for highly reliable manufacturing. Finally, we clarify the effect of the residual stress in transistor structures on shift in the electronic characteristics of MOS transistors.

A new practical coherent detection scheme for biorthogonal signals, which uses multi-symbol observation interval, is proposed and its performances are analyzed and simulated. The technique jointly estimates both the demodulated data and the channel from received signal only while reducing computation complexity by an approximate maximum-likelihood sequence estimation rather than symbol-by-symbol detection as in previous noncoherent detection. The scheme achieves performance close to that of ideal coherent detection with perfect channel estimates when select the appropriate observation symbol interval N in the given symbol alphabet size M. What is particularly interesting is that the required average signal-to-noise ratio per bit γb can be reduced by as much as 1.4 dB and the capacity can be increased by as much as 38% when we use this system in the CDMA cellular reverse link.

Design concepts and backgrounds of a 3-dimensional semiconductor process simulator are presented. It is designed to become a basis of developing semiconductor process models. An input language is designed to realize flexibly controlling simulation sequence, and its interpreter program is designed to accept external software to be controlled and to be integrated into a system. To realize data-exchanges between the process simulator and other software, a self-describing data-file format is designed and related program libraries are developed. A C++ class for solving drift-diffusion type partial-differential-equation in a three-dimensional space is developed.

A new concept of "an imperfect singular solution" is defined as an approximate solution which becomes a singular solution by adding a suitable small perturbation to the original equations. A numerical method is presented for proving the existence of imperfect singular solutions of nonlinear equations with guaranteed accuracy. A few numerical examples are also presented for illustration.

This paper describes a defect detection method which automatically extracts defect information from complicated background LSI patterns. Based on a scanning electron microscope (SEM) image, the defects on the wafer are characterized in terms of their locations, sizes and the shape of defects. For this purpose, two image processing techniques, the Hough transform and wavelet transform, have been employed. Especially, the Hough Transform for circles is applied to non-circular defects for estimating the shapes of defects. By experiments, it has been demonstrated that the system is very effective in defect identification and will be used as an integral part in future automatic defect pattern classification systems.

This paper outlines the modeling requirements of integrated circuit (IC) fabrication processes that have lead to and sustained the development of computer-aided design of technology (i. e. TCAD). Over a period spanning more than two decades the importance of TCAD modeling and the complexity of required models has grown steadily. The paper also illustrates typical applications where TCAD has been powerful and strategic to IC scaling of processes. Finally, the future issues of atomic-scale modeling and the need for an hierarchical approach to capture and use such detailed information at higher levels of simulation are discussed.