This paper describes a defect detection method which automatically extracts defect information from complicated background LSI patterns. Based on a scanning electron microscope (SEM) image, the defects on the wafer are characterized in terms of their locations, sizes and the shape of defects. For this purpose, two image processing techniques, the Hough transform and wavelet transform, have been employed. Especially, the Hough Transform for circles is applied to non-circular defects for estimating the shapes of defects. By experiments, it has been demonstrated that the system is very effective in defect identification and will be used as an integral part in future automatic defect pattern classification systems.

We have improved the mechanical reliability of deep-submicron semiconductor devices by applying a simulation technique. Typical kinds of damages that reduce the reliability are dislocations in silicon substrates, delamination or cracking of thin films, and deterioration of electronic characteristics of devices. The mechanical stress that develops in device structures is caused by not only mismatches in thermal expansion coefficients among thin film materials but also intrinsic stress of thin films such as poly-silicon and silicides. Fine patterning by dry etching makes sharp edges and they also cause stress concentration and thus high stress. The manufacturing processes in which stress mainly develops are isolation, gate formation, and interconnect formation. We have developed methods for reducing the stress in each of the above-mentioned process. This stress reduction is very effective for highly reliable manufacturing. Finally, we clarify the effect of the residual stress in transistor structures on shift in the electronic characteristics of MOS transistors.

Future cellular systems are envisioned to support mixed traffic, and ultimately multimedia services. However, a mixture of voice and data requires novel service mechanisms that can guarantee quality of service. In order to transfer high-speed data, multislot channel allocation is seen as a favoured solution to the present systems with the least compromise to circuit- switched services. This paper evaluates the performance of narrowband voice calls and multislot data packet transmission in such integrated systems by using a matrix-analytic approach. This method achieves quadratic convergence compared to the conventional spectral methods. Mobility is also considered in a prioritized cellular environment where frequent handoff has the potential of degrading data performance. The voice call distribution, data packets throughput, delay and waiting time distribution are derived. Moreover, a new multiple priority-based distributed control algorithm and a voice rate control scheme are enforced to mitigate the queuing congestion of data packets. The numerical results derived from this study show that larger data packets incur longer latency and the use of these flexible schemes can improve the overall performance.

This paper outlines the modeling requirements of integrated circuit (IC) fabrication processes that have lead to and sustained the development of computer-aided design of technology (i. e. TCAD). Over a period spanning more than two decades the importance of TCAD modeling and the complexity of required models has grown steadily. The paper also illustrates typical applications where TCAD has been powerful and strategic to IC scaling of processes. Finally, the future issues of atomic-scale modeling and the need for an hierarchical approach to capture and use such detailed information at higher levels of simulation are discussed.

This paper discusses the classification of targets buried in the underground by radar polarimetry. The subsurface radar is used for the detection of objects buried beneath the ground surface, such as gas pipes, cables and cavities, or in archeological exploration operation. In addition to target echo, the subsurface radar receives various other echoes, because the underground is inhomogeneous medium. Therefore, the subsurface radar needs to distinguish these echoes. In order to enhance the discrimination capability, we first applied the polarization anisotropy coefficient to distinguish echoes from isotropic targets (plate, sphere) versus anisotropic targets (wire, pipe). It is straightforward to find the man-made target buried in the underground using the polarization anisotropy coefficient. Second, we tried to classify targets using the polarimetric signature approach, in which the characteristic polarization state provides the orientation angle of an anisotropic target. All of these values contribute to the classification of a target. Field experiments using an ultra-wideband (250 MHz to 1 GHz) FM-CW polarimetric radar system were carried out to show the usefulness of radar polarimetry. In this paper, several detection and classification results are demonstrated. It is shown that these techniques improve the detection capability of buried target considerably.

This paper presents a method of calculating an interval including a bifurcation point. Turning points, simple bifurcation points, symmetry breaking bifurcation points and hysteresis points are calculated with guaranteed accuracy by the extended systems for them and by the Krawczyk-based interval validation method. Taking several examples, the results of validation are also presented.

The full liquid crystal display (LCD) simulation with real transistors and other active components is unrealistic. Because a flat panel display (FPD) includes thin-film-transistors (TFT's) whose number is, at least, the number of total pixels. It hits the simulation limit of SPICE if the number of transistors are more than 0.5 million. This paper demonstrates a new, fast, and effective simulation method for a full LCD panel. The method makes it possible to simulate large LCD panels whereas the conventional method cannot handle. The simulation circuit consists of a-Si TFT model presented earlier, the liquid crystal, the pixel macro models, and interconnects. We show the model parameter extraction and the pixel macro modeling process associated with the simulation results. Using the simulation method presented here some larger LCD panels can be accurately simulated in less than a minute on a workstation.

In this paper we present a rigorous vector 3D lithography simulator METROPOLE-3D which is designed to run moderately fast on conventional engineering workstations. METROPOLE-3D solves Maxwell's equations rigorously in three dimensions to model how the non-vertically incident light is scattered and transmitted in non-planar structures. METROPOLE-3D consists of several simulation modules: photomask simulator, exposure simulator, post-exposure baking module and 3D development module. This simulator has been applied to a wide range of pressing engineering problems encountered in state-of-the-art VLSI fabrication processes, such as layout printability/manufacturability analysis including reflective notching problems and optimization of an anti-reflective coating (ARC) layer. Finally, a 3D contamination to defect transformation study was successfully performed using our rigorous simulator.

A new concept of "an imperfect singular solution" is defined as an approximate solution which becomes a singular solution by adding a suitable small perturbation to the original equations. A numerical method is presented for proving the existence of imperfect singular solutions of nonlinear equations with guaranteed accuracy. A few numerical examples are also presented for illustration.

Electro-thermal characteristics of the Si MOSFET in transient state are reported using a non-isothermal device simulator where both the transistor's self-heating and the thermal influence of its neighboring devices are duly taken into account. The thermal influence is estimated using a three-dimensional thermal simulator. Based on this set-up, we predict time-dependent electro-thermal characteristics of the Si MOSFET at gate switching and its drain breakdown conditions. We show that the time delay between the electrical response and the lattice temperature rise, is significant and thus can not be neglected. In addition, we found that avalanche and thermal breakdown characteristics largely depend on the slope of the drain input voltage.

This paper describes a 10-bit 40-MS/s pipelined A/D converter implemented in a 0.8-µm double-poly, double-metal CMOS process. This A/D converter achieves low power dissipation of 36-mW at 5-V power supply. A 1.5-bit/stage pipelined architecture allows large correction range for comparator offset, and performs fast interstage signal processing. For high speed and low power operation, the sample-and-hold amplifier is designed using op-amp sharing technique and dynamic comparator. In addition, fully-differential folded-cascode op amp with gain-boosting stage is designed by an automatic design tool. When 10-MHz input signal is applied, SNDR is 55.0 dB, and SNR is 56.7 dB. The DNL and INL exhibit 0.6 LSB, +1/-0.75 LSB respectively.

The characteristics of the decision feedback carrier recovery loop (DFL) for conventional QPSK signaling is evaluated experimentally through measurements of the carrier-to-noise ratio of the regenerated carrier, lock range, acquisition waveforms and bit error rates. The results show that the DFL hardly exhibits inferiority to the ideal synchronization by designing the loop natural frequency adequately small. The DFL is shown superb in carrier tracking.

The transfer function of IIR all-pass filters is a rational function of ω. However, the optimization of such a rational function using the successive projections method, which has a wider range of application than the Remez algorithm, has not been presented. In this paper, we propose designing IIR all-pass filters using the successive projections method.

A new design hierarchy in TCAD is discussed with emphasis on a design of IC interconnects and gate patterns. Two design methodologies for gate patterns at a CMOS cell level and multilevel interconnect scheme at a chip level are proposed. This approach generates the layout design rules of gate patterns, considering the fabrication process and pattern layout dependency, and allows a design of multilevel interconnect scheme at the initial phase of technology development.

From our previous studies, we derived the worst case cell delay within an ATM switch and thus can find the worst case end-to-end delay for a set of real-time connections. We observed that these delays are sensitive to the priority assignment of the connections. With a better priority assignment scheme within the switch, the worst case delay can be reduced and provide a better network performance. We extend our previous work on the closed form analysis to conduct more experimental study of how different priority assignments and system parameters may affect the performance. Furthermore, from our worst case delay analysis on a regulated ATM switch, network traffic can be smoothed by a leaky bucket at the output controller for each connection. With the appropriate setting on the leaky bucket parameter, the burstiness of the network traffic can be reduced without increasing the delay in the switch. Therefore, fewer buffers will be required for each active connection within the switch. In this paper, our experimental results have shown that the buffer requirement can be reduced up to 5.75% for each connection, which could be significant, when hundreds of connections are passing through the switches within a regulated ATM network.

In a multisystem data sharing environment (MDSE), the computing nodes are locally coupled via a high-speed network and share a common database at the disk level. To reduce the amount of expensive and slow disk I/O, each node caches database pages in its main memory buffer. This paper focuses on the MDSE that uses record-level locking as a concurrency control. While the record-level locking can guarantee higher concurrency than page-level locking, it may result in heavy message traffic. In this paper, we first propose a cache coherency scheme that can reduce the message traffic in the standard locking. Then the scheme is extended to the context where lock caching and lock de-escalation are adopted. Using a distributed database simulation model, we evaluate the performance of the proposed schemes under a wide variety of database workloads.

Fluctuations of three device parameters (Tox, Nsub, ΔL) based on process fluctuations are taken as cause of device/circuit performances. In-line measured device parameters are approximated by Gaussian functions, and their 2σ values are assigned as boundaries of the performance fluctuations. Measured distributions both for device and curcuit performances are successfully reproduced.

A new IC interconnect transmission line parameter determination methodology and a novel fast simulation technique for non-uniform transmission lines are presented and verified. The capacitance parameter is a strong function of a shielding effect between the layers, while silicon substrate has a substantial effect on inductance parameter. Thus, they are taken into account to determine the parameters. Then the virtual straight-line-based per unit length parameters are determined in order to perform the fast transient simulation of the non-uniform transmission lines. It was shown that not only the inductance effect due to a silicon substrate but also the shielding effect between the layers are too significant to be neglected. Further, a model order reduction technique is integrated into Berkeley SPICE in order to demonstrate that the virtual straight-line-based per-unit-length parameters can be efficiently employed for the fast transient response simulation of the complicated multi-layer interconnect structures. Since the methodology is very efficient as well as accurate, it can be usefully employed for IC CAD tools of high-performance VLSI circuit design.

In order to investigate the dynamic behavior of quantized interconnection neural networks on neuro-chips, we have designed and fabricated hardware neural networks according to design rule of a 1.2 µm CMOS technology. To this end, we have developed programmable synaptic weights for the interconnection with three values of 1 and 0. We have tested the chip and verified the dynamic behavior of the networks in a circuit level. As a result of our study, we can provide the most straightforward application of networks for a dynamic pattern classifier. The proposed network is advantageous in that it does not need extra exemplar to classify shifted or reversed patterns.

We have developed a practical 3-D integrated process simulator (3-D MIPS) based on the orthogonal grid. 3-D MIPS has a 3-D topography simulator (3-D MULSS) and 3-D impurity simulator which simulates the processes of ion implantation, impurity diffusion and oxidation. In particular, its diffusion and segregation model is new and practical. It assumes the continuity of impurity concentration at the material boundary in order to coordinate with the topography simulator (3-D MULSS) with cells in which two or more kinds of materials exist. And then, we introduced a time-step control method using the Dufort-Frankel method of diffusion analysis for stable calculation, and a selective oxidation model to apply to more general structures than LOCOS structure. After that, the 3-D MIPS diffusion model is evaluated compared with experimental data. Finally, the 3-D MIPS is applied to 3-D simulations of the nMOS Tr. structure with LOCOS isolation, wiring interconnect and pn-junction capacitances, and DRAM storage node area.