Since manufacturing processes inherently fluctuate, LSI chips which are produced from the same design have different propagation delays. However, the difference in delays caused by the process fluctuation has rarely been considered in most of existing high-level synthesis systems. This paper presents a new approach to module selection in high-level synthesis, which exploits the difference in functional unit delays. First, a module library model which assumes the probabilistic nature of functional unit delays is presented. Then, we propose a module selection problem and an algorithm which minimizes the cost per faultless chip. Experimental results demonstrate that the proposed algorithm finds optimal module selections which would not have been explored without manufacturing information.

A zerotree image-coding scheme is introduced that effectively exploits the inter-scale self-similarities found in the octave decomposition by a wavelet transform. A zerotree is useful for efficiently coding wavelet coefficients; its efficiency was proved by Shapiro's EZW. In the EZW coder, wavelet coefficients are symbolized, then entropy-coded for further compression. In this paper, we analyze the symbols produced by the EZW coder and discuss the entropy for a symbol. We modify the procedure used for symbol-stream generation to produce lower entropy. First, we modify the fixed relation between a parent and children used in the EZW coder to raise the probability that a significant parent has significant children. The modified relation is flexibly modified again based on the observation that a significant coefficient is more likely to have significant coefficients in its neighborhood. The three relations are compared in terms of the number of symbols they produce.

A novel cumulant based MUSIC like DOA estimation algorithm for multicarrier modulation has been proposed in this paper. While the conventional MUSIC algorithm is not applicable to a correlation matrix calculated from received signals transmitted over the different carriers, the proposed algorithm can estimate the DOA of the signals with multicarrier modulation. The proposed algorithm does not require the sensor array responses for the frequency range of the interest and the initial phases of the carriers. With the proposed algorithm the number of signals whose DOA are estimated can be increased and the accuracy of the DOA estimation can be improved by employing larger number of carriers.

This paper proposes a novel signal transmission scheme for helicopter satellite communications. The proposed scheme is based on time diversity, and combined with a novel algorithm to suppress an influence of carrier phase slip. In the proposed scheme, carrier phase slip is detected in cross correlation processing of the received signal, and is effectively suppressed. The proposed scheme thus makes it possible to employ coherent phase shift keying modulation to achieve bit error rate performance superior to that of differential phase shift keying modulation even in the low carrier-to-noise power ratio environment.

Full-wave FD-TD analysis has been carried out for coaxial probes inserted into waveguides. Both single and symmetrically placed paired coaxial probe structures have been discussed and we have revealed the relation between equivalent circuit parameters and structural parameters of the coaxial probes including cases for large diameter and extension length, which is useful for practical waveguide circuit design. The equivalent circuit parameters calculated from the scattering parameters agreed well with corresponding measured data. From the calculated field in a waveguide, field concentration at sharp edges of probe sole or base, which ought to be taken into account for high power application design has been also discussed. Besides, amplitudes of higher order modes in waveguides excited by coaxial probes or pairs of coaxial probes has been calculated so as to estimate the range beyond which higher order modes decay sufficiently. This estimation is necessary for simple and easy design of probe using circuit theory.

The software requirements specification process consists of three steps; requirements capture and analysis, requirements definition and specification, and requirements validation. At the beginning of the second step which this paper focuses on, there have been several types of massive documents generated in the first step. Since the developers and the clients/users of the new software system may not have common knowledge in the field which the system deals with, it is difficult for the developers to produce correct requirements specification by using these documents. There has been few research work to solve this problem. The authors have developed a support tool to produce correct requirements specification by arranging and restructuring those documents into clearly understandable forms. In the second step, the developers must specify the functions and their constraints of the new system from those documents. Analyzing the developers' real activities for designing the support tool, the authors propose a model of this step as the following four activities. To specify the functions of the new system, the developers must collect the sentences which may suggest the functions scattering those documents. To define the details of each function, the developers must gather the paragraphs including the descriptions of the functions. To verify the correctness of each function, the developers must survey all related documents. To perform above activities successfully, the developers must manage various versions of those documents correctly. According to these four types of activities, the authors propose the effective ways to support the developers by arranging those documents. This paper shows algorithms based on this model by using the structures of the documents and keywords which may suggest the functions or constraints. To examine the feasibility of their proposal, the authors implemented a prototype tool. Their tool extracts complete information scattering those documents. The effectiveness of their proposal is demonstrated by their experiments.

The datapath width of a core processor has a strong effect on cost, power consumption, and performance of an embedded system integrated with memories into a single-chip. However, it is difficult for designers to appropriately determine the datapath width for each application because of the limited reusability of software and the lack of compilation techniques. The purpose of this paper is to clarify supports required from software for the optimal datapath width determination. As a solution, an embedded programming language, called Valen-C, and a retargetable Valen-C compiler are proposed. In this paper, the syntax and semantics of Valen-C along with the mechanism of the Valen-C retargetable compiler and how to preserve the accuracy of computation of programs in relation to various datapath widths are also described. Experiments with practical applications show that the total cost of the system including a core processor, ROM, and RAM is drastically reduced with little performance loss by reducing the datapath width.

This paper reports on an Intelligent CASE tool, applicable in a structured programming phase, or from detailed design to coding. This is automation of the bottom level in the hierarchical design process of detailed design and coding, where the largest man-hours are consumed. The main idea is that human designers use a CASE tool for the initial design of a software system, and the design knowledge is automatically acquired from the structured charts and stored in the knowledge base. The acquired design knowledge may be reused in designs. By reusing it, a similar software system may be designed automatically. It has been shown that knowledge acquired in this way has a Logarithmic Learning Effect. Based on this, a quantitative evaluation of productivity is made. By accumulating design experiences (e. g. 10 times), more than 80% of the detailing designs are performed automatically, and productivity increases by up to 4 times. This tool features universality, an essentially zero start-up cost for automatic design, and a substantial increase in software productivity after enough experiences have been accumulated. This paper proposes a new basic idea and its implementation, a quantitative evaluation applying techniques from Industrial Engineering, which proves the effectiveness of the proposed system.

A method of visualization of multimodal images by one monochromatic image is presented on the basis of the projection pursuit approach of the inverse process of the anisotropic diffusion which is a method of image restoration enhancing contrasts at edges. The extension of the projection from a linear one to nonlinear sigmoidal functions enhances the contrast further. The deterministic annealing technique is also incorporated into the optimization process for improving the contrast enhancement ability of the projection. An application of this method to a pair of MRI images of brains reveals its promising performance of superior visualization of tissues.

A Pragmatic Trellis Coded MPSK on a Rayleigh fading channel is analyzed. This scheme allows bandwidth expansion ratio to be varied aiming at an optimization between complexity of the system design and improvement of coding gain. In order to vary the bandwidth expansion ratio, a punctured convolutional code is used. The performance of the proposed TC-2mPSK on a Rayleigh fading channel is theoretically analyzed. In the test examples, the BER performances of TC-QPSK and TC-8PSK are evaluated by theoretical analyses and computer simulations at the encoder parameters of K3 and r3/4. The results show that the proposed scheme can attain better performance not only over the uncoded scheme but over the conventional Pragmatic TCM.

In this paper, we describe a routing method for path on SDH Network with digital cross-connect control, which is implemented in an automated path provisioning function. Excessive concentration of assigned time slots at particular links results in longer restoration time, which is needed to switch or reroute paths on failure link. We propose an optimization method to provision the shortest route considering deconcentration of time slots assigned on each link. After defining LP-based formulation for path routing, we carried out computer simulation study for restoration performance on sample networks, assuming each restoration process for paths on failure link is executed one after another. Mean restoration time by our proposed method has reduced to a great extent compared to a basic routing method. It has been proven that the proposed method can realize effective use of resources and faster restoration time, and can be utilized in commercial systems.

Hardware software codesign using various hardware and software implementation possibilities requires a cosimulation environment which has both flexibility and efficiency. In this paper, a hardware software cosimulation environment is developed using the backplane approach and optimized synchronization. To seamlessly integrate a new simulator, this paper defines and implements the backplane protocol for communication and synchronization between client simulators. Automatic interface generation facility is also devised for more effective cosimulation environment. To enhance the performance of cosimulation backplane, a series of optimized hardware software synchronization methods are introduced. Efforts are focused on reducing control packets between simulators as well as concurrent execution of simulators without roll-back. The environment is implemented based on Ptolemy and validated with a QAM example run on different configurations. With optimized synchronization method, we have achieved about 7 times speed-up compared with the lock-step synchronization.

Providing various assistances for design modifications on HDL source codes is important for design reuse and quick design cycle in VLSI CAD. Program slicing is a software-engineering technique for analyzing, abstracting, and transforming programs. We show algorithms for extracting/removing behaviors of specified signals in VHDL descriptions. We also describe a VHDL slicing system and show experimental results of efficiently extracting components from VHDL descriptions.

A major topic in the field of network and telecommunications is doing business on the World Wide Web (WWW), which is called Electronic Commerce (EC). Another major topic is blending Artificial Intelligence (AL) techniques with the WWW. In the Ex-W-Pert Project we have proposed an agent model for EC components that blends the traditional expert systems' reasoning engine with a multi-layer knowledge base, communication and documentation engines. In this project, EC is viewed as a society of software agents, such as customer, search, catalog, manufacturer, dealer, delivery and banker agents, interacting and negotiating with each other. Each agent has a knowledge-base and a reasoning engine, a communication engine and a documentation engine. The knowledge-base is organized in three layers: skill layer, rule layer and knowledge layer (S-R-K layers). In this project, for each EC agent, we identify the class of problems to be solved and build the knowledge base gradually for each layer. We believe that using this multi-layer knowledge base system will speed up the reasoning and ultimately reduce the operation costs.

The productivity of developing software for switching systems and the effects of using advanced software development methods were evaluated and analyzed. Productivity was found to be improved by using automatic code generation, simulator debugging, a hierarchical object-oriented software structure, and software-development-support tools. The evaluation showed that the total productivity was improved by about 20%, compared with a case where these efforts were not introduced. It also showed each effect of these methods and tools by evaluating their manpower saving ratios. These results are expected to benefit the development of various types of communication-switching and multimedia service systems. Also, our development-support tools and methods are expected to be the basis for attaining higher software development productivity.

A novel image improving algorithm for compressed image sequence by merging a reference image is presented. A high quality still image of the same scene is used as a reference image. The degraded images are improved by merging reference image with them. Merging amount is controlled by the resemblance between the reference image and compressed image after applying motion compensation. Experiments conducted on sequences of JPEG images are given. This technique does not need a prior knowledge of compression technique so it can be applied to other techniques as well.

We have analyzed a very short channel tunneling field effect transistor which uses new heterostructures (CoSi2/Si/CdF2/CaF2) lattice-matched to the Si substrate. In device operation, the drain current from source (CoSi2) to drain (CoSi2) through tunnel barriers (Si) and the channel (CdF2) is controlled by a gate electric field applied to the barrier between the source and the channel through the gate insulator (CaF2). Theoretical analysis shows that this transistor has characteristics similar to those of conventional metal-oxide-semiconductor field effect transistors even with channel lengths as short as 5 nm. In addition, we have estimated the theoretical response time of this transistor and showed the possibility of subpicosecond response.

This paper describes a new approach to analyze nonlinear characteristics of propagating waves in a ferrite material. As to the formulation of the wave in a ferrite medium, the analysis in this paper is not taken under the assumption of a sinusoidal steady state using Polder tensor permeability, but taken by directly differentiating the gyromagnetic equation in time domain without any linear approximations. Then it is combined with Maxwell equation in FDTD procedure. As a result, intensity-dependent nonlinear responses of the propagating wave are confirmed, and the nonlinearity is seen in only the right-hand polarization wave. It is also found that an effect of the damping term in the equation of the motion of the magnetization has nonlinear characteristics for wave propagation.

This paper presents a timing-driven global routing algorithm based on coarse pin assignment, block reshaping, and positioning for VLSI building block layout. As opposed to conventional approaches, we combine pin assignment and global routing problems into one problem. The proposed algorithm determines global routes, coarse pin assignments, and block shapes and positions so as to minimize the chip area and total wire length of nets under the given timing constraints. It is based on an iterative improvement paradigm and performs rip-up and rerouting, block reshaping, and positioning in the manner of simulated evolution taking shapes of soft blocks and routing congestion into consideration until the solution is not further improved. The Elmore delay model is adopted for the interconnection delay model. Experimental results show the effectiveness of the proposed algorithm.

This paper presents a new binding algorithm for a retargetable compiler which can deal with diverse architectures of application specific embedded processors. The architectural diversity includes a "non-orthogonal" datapath configuration where all the registers are not equally accessible by all the functional units. Under this assumption, binding becomes a hard task because inadvertent assignment of an operation to a functional unit may rule out possible assignment of other operations due to unreachability among datapath resources. We propose a new BDD-based algorithm to solve this problem. While most of the conventional methods are based on the covering of expression trees obtained by decomposing DFGs, our algorithm works directly on the DFGs so as to avoid infeasible bindings. In the experiments, a feasible binding which satisfies the reachability is found or the deficiency of datapath is detected within a few seconds.