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[Keyword] SI(16314hit)

13781-13800hit(16314hit)

  • Relaxation-Based Transient Analysis of Lossy Coupled Transmission Lines Circuits Using Delay Evaluation Technique

    Takayuki WATANABE  Atsushi KAMO  Hideki ASAI  

     
    PAPER-Modeling and Simulation

      Vol:
    E81-A No:6
      Page(s):
    1055-1062

    This paper describes an efficient method to simulate lossy coupled transmission lines based on the delay evaluation technique. First, we review the previous methods, and refer to several problems concerned with these methods. Next, a novel waveform relaxation-based simulation method is proposed, which uses the delay evaluation technique. This method enables to obtain the accurate transient waveforms using smaller number of moments than the other moment methods use, and is modified for acceleration by the generalized line delay window partitioning (GLDW) technique. Finally, this method is implemented in the waveform relaxation-based circuit simulator DESIRE3T+, and the performance is estimated.

  • A Recursive Algorithm for Estimating the Internal Charge Sharing Effect in RC Tree Circuits

    Molin CHANG  Wu-Shiung FENG  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E81-A No:5
      Page(s):
    913-923

    BTS (Binary-tree Timing Simulator) is a waveform-based switch-level timing simulator for VLSI circuits and the primary goal is to obtain an accurate waveform during the transient period. To achieve high accuracy, the internal charge effect should be considered because the delay behavior of a CMOS gate is dramatically influenced by internal charges stored in the internal nodes. However, the delay estimation will become a difficult problem when the charge sharing effect is considered. Therefore, this paper presents a recursive algorithm based on Modified Threaded Binary (MTB) tree for efficiently performing the internal-charge-delay estimation in transistor groups using the switch-level delay model. The algorithm CSEE (Charge Sharing Effect Estimation) can determine the charge distribution among the internal nodes, and then increases the accuracy of the waveform approximate technique used in BTS.

  • A Linear Time Algorithm for Constructing Proper-Path-Decomposition of Width Two

    Akira MATSUBAYASHI  Shuichi UENO  

     
    PAPER

      Vol:
    E81-A No:5
      Page(s):
    729-737

    The problem of constructing the proper-path-decomposition of width at most 2 has an application to the efficient graph layout into ladders. In this paper, we give a linear time algorithm which, for a given graph with maximum vertex degree at most 3, determines whether the proper-pathwidth of the graph is at most 2, and if so, constructs a proper-path-decomposition of width at most 2.

  • Polling-Based Real-Time Software for MPEG2 System Protocol LSIs

    Jiro NAGANUMA  Makoto ENDO  

     
    PAPER

      Vol:
    E81-C No:5
      Page(s):
    695-701

    This paper proposes polling-based real-time software for MPEG2 System protocol LSIs, which is a typical embedded and real-time system on a chip, and demonstrates its performance and usefulness. The polling-based real-time software is designed and optimized by analyzing application specific function requirements and deciding scheduling intervals and the execution cycles of each task. It requires neither hardware for multiple interrupt handling nor software for heavy context switching. The polling-based approach provides sufficient performance without any hardware and software overhead for a real-time application like the MPEG2 System protocol.

  • Future Directions of Media Processors

    Shunichi ISHIWATA  Takayasu SAKURAI  

     
    INVITED PAPER-Multimedia

      Vol:
    E81-C No:5
      Page(s):
    629-635

    Media processors have emerged so that a single LSI can realize multiple multimedia functions, such as graphics, video, audio and telecommunication with effectively shared hardware and flexible software. First, the difference between media processors and general-purpose microprocessors with multimedia extensions is clarified. Features for processes and data in the multimedia applications are summarized and are followed by the multimedia enhancements that the recent general-purpose microprocessors use. The architecture for media processors reflects the further optimized utilization of these features and realizes better price-performance ratio than the general-purpose microprocessors. Finally, the future directions of media processors are estimated, based on the performance, the power dissipation and the die size of the present microprocessors with multimedia extensions and the present media processors. The demand to improve the price-performance ratio for the whole system and to reduce the power consumption makes the media processor evolve into a system processor, which integrates not only the media processor but also the function of a general-purpose microprocessor, various interfaces and DRAMs.

  • MCD Analysis of Reflection Characteristics on Nonuniform Transmission Lines

    Kazuhito MURAKAMI  Junya ISHII  

     
    PAPER-Microwave and Millimeter Wave Technology

      Vol:
    E81-C No:5
      Page(s):
    781-787

    In this paper, a new simulation approach to the analysis of the reflection characteristics on nonuniform transmission lines (NTLs) is presented. The input and output responses in the time domain and the reflection coefficients in the frequency domain are effectively obtained by using the modified central difference (MCD) simulation and the fast Fourier transform (FFT) technique for Gaussian pulse responses. The simulated results for the reflection characteristics of the NTL transformers are in excellent agreements with the theoretical values. By representing both the reflected voltage and the reflection coefficient, it is shown that this approach is useful to analyze for various types of tapered and stepped NTLs.

  • An LSI for Low Bit-Rate Image Compression Using Vector Quantization

    Kazutoshi KOBAYASHI  Noritsugu NAKAMURA  Kazuhiko TERADA  Hidetoshi ONODERA  Keikichi TAMARU  

     
    PAPER

      Vol:
    E81-C No:5
      Page(s):
    718-724

    We have developed and fabricated an LSI called the FMPP-VQ64. The LSI is a memory-based shared-bus SIMD parallel processor containing 64 PEs, intended for low bit-rate image compression using vector quantization. It accelerates the nearest neighbor search (NNS) during vector quantization. The computation time does not depend on the number of code vectors. The FMPP-VQ64 performs 53,000 NNSs per second, while its power dissipation is 20 mW. It can be applied to the mobile telecommunication system.

  • A VLSI Architecture for Motion Estimation Core Dedicated to H. 263 Video Coding

    Gen FUJITA  Takao ONOYE  Isao SHIRAKAWA  

     
    PAPER

      Vol:
    E81-C No:5
      Page(s):
    702-707

    A VLSI architecture of a motion estimator is described dedicatedly for the H. 263 low bitrate video coding. Adopting an efficient hierarchical search algorithm, a new motion estimator yields high quality vectors with small area occupancy and at a low operation frequency. A one-dimensional PE (Processing Element) array is devised to be tuned to the H. 263 encoding, which treats both the advanced prediction mode and the PB-frame mode. The proposed motion estimation core is integrated in 1. 55 mm2 by using 0. 35 µm CMOS 3LM technology, which operates at 15 MHz, and hence enables the realtime motion estimation of QCIF pictures.

  • Multimedia Technology Trend in MPEG4

    Takanori SENOH  Takuyo KOGURE  

     
    INVITED PAPER-Multimedia

      Vol:
    E81-C No:5
      Page(s):
    642-650

    A multimedia coding standard, MPEG4 has frozen its Committee Draft (CD) as the MPEG4 version 1 CD, last October. It defines Audio-Visual (AV) coding Algorithms and their System Multiplex/Composition formats. Founding on Object-base concept, Video part adopts Shape Coding technology in addition to conventional Texture Coding skills. Audio part consists of voice coding tools (HVXC and CELP core) and audio coding tools (HILN and MPEG2 AAC or Twin VQ). Error resilience technologies and Synthetic and Natural Hybrid Coding (SNHC) technologies are the MPEG4 specific features. System part defines flexible Multiplexing of audio-visual bitstreams and Scene Composition for user-interactive re-construction of the scenes at decoder side. The version 1 standardization will be finalized in 1998, with some possible minute changes. The expected application areas are real-time communication, mobile multimedia, internet/intranet accessing, broadcasting, storage media, surveillance, and so on.

  • Knowledge-Based Enhancement of Low Spatial Resolution Images

    Xiao-Zheng LI  Mineichi KUDO  Jun TOYAMA  Masaru SHIMBO  

     
    PAPER-Image Processing,Computer Graphics and Pattern Recognition

      Vol:
    E81-D No:5
      Page(s):
    457-463

    Many image-processing techniques are based on texture features or gradation features of the image. However, Landsat images are complex; they also include physical features of reflection radiation and heat radiation from land cover. In this paper, we describe a method of constructing a super-resolution image of Band 6 of the Landsat TM sensor, oriented to analysis of an agricultural area, by combining information (texture features, gradation features, physical features) from other bands. In this method, a knowledge-based hierarchical classifier is first used to identify land cover in each pixel and then the least-squares approach is applied to estimate the mean temperature of each type of land cover. By reassigning the mean temperature to each pixel, a finer spatial resolution is obtained in Band 6. Computational results show the efficiency of this method.

  • Active Sensor Fusion for Collision Avoidance in Behaviour-Based Mobile Robots

    Terence Chek Hion HENG  Yoshinori KUNO  Yoshiaki SHIRAI  

     
    PAPER-Image Processing,Computer Graphics and Pattern Recognition

      Vol:
    E81-D No:5
      Page(s):
    448-456

    Presently, mobile robots are navigated by means of a number of methods, using navigating systems such as the sonar-sensing system or the visual-sensing system. These systems each have their strengths and weaknesses. For example, although the visual system enables a rich input of data from the surrounding environment, allowing an accurate perception of the area, processing of the images invariably takes time. The sonar system, on the other hand, though quicker in response, is limited in terms of quality, accuracy and range of data. Therefore, any navigation methods that involves only any one system as the primary source for navigation, will result in the incompetency of the robot to navigate efficiently in a foreign, slightly-more-complicated-than-usual surrounding. Of course, this is not acceptable if robots are to work harmoniously with humans in a normal office/laboratory environment. Thus, to fully utilise the strengths of both the sonar and visual sensing systems, this paper proposes a fusion of navigating methods involving both the sonar and visual systems as primary sources to produce a fast, efficient and reliable obstacle-avoiding and navigating system. Furthermore, to further enhance a better perception of the surroundings and to improve the navigation capabilities of the mobile robot, active sensing modules are also included. The result is an active sensor fusion system for the collision avoiding behaviour of mobile robots. This behaviour can then be incorporated into other purposive behaviours (eg. Goal Seeking, Path Finding, etc. ). The validity of this system is also shown in real robot experiments.

  • Computer Simulation of Feedback Induced Noise in Semiconductor Lasers Operating with Self-Sustained Pulsation

    Minoru YAMADA  

     
    PAPER-Quantum Electronics

      Vol:
    E81-C No:5
      Page(s):
    768-780

    Theoretical calculations of the pulsing operation and the intensity noise under the optical feedback are demonstrated for operation of the self-sustained pulsation lasers. Two alternative models for the optical feedback effect, namely the time delayed injection model and the external cavity model, are applied in a combined manner to analyze the phenomena. The calculation starts by supposing the geometrical structure of the laser and the material parameters, and are ended by evaluating the noise. Characteristics of the feedback induced noise for variations of the operating parameters, such as the injection current, the feedback distance and the feedback ratio, are examined. A comparison to experimental data is also given to ensure accuracy of the calculation.

  • A Chip Set for Programmable Real-Time MPEG2 MP@ML Video Encoder

    Tetsuya MATSUMURA  Hiroshi SEGAWA  Satoshi KUMAKI  Yoshinori MATSUURA  Atsuo HANAMI  Kazuya ISHIHARA  Shin-ichi NAKAGAWA  Tadashi KASEZAWA  Yoshihide AJIOKA  Atsushi MAEDA  Masahiko YOSHIMOTO  Tadashi SUMI  

     
    PAPER

      Vol:
    E81-C No:5
      Page(s):
    680-694

    This paper describes a chip set architecture and its implementation for programmable MPEG2 MP@ML (main profile at main level) video encoder. The chip set features a functional partitioning architecture based on the MPEG2 layer structure. Using this partitioning scheme, an optimized system configuration with double bus structure is proposed. In addition, a hybrid architecture with dual video-oriented on-chip RISC processors and dedicated hardware and a hierarchical pipeline scheme covering all layers are newly introduced to realize flexibility. Also, effective motion estimation is achieved by a scalable solution for high picture quality. Adopting these features, three kinds of VLSI have been developed using 0. 5 micron double metal CMOS technology. The chip set consists of a controller-LSI (C-LSI), a macroblock level pixel processor-LSI (P-LSI) and a motion estimation-LSI (ME-LSI). The chip set combined with synchronous DRAMs (SDRAM) supports all the layer processing including rate-control and realizes real-time encoding for ITU-R-601 resolution video (720480 pixels at 30 frames/s) with glue less logic. The exhaustive motion estimation capability is scalable up to 63. 5 and 15. 5 in the horizontal and vertical directions respectively. This chip set solution realizes a low cost MPEG2 video encoder system with excellent video quality on a single PC extension board. The evaluation system and application development environment is also introduced.

  • Low Bit-rate Video Coding Using a DSP for Consumer Applications

    Hisashi INOUE  Shiro IWASAKI  Takashi KATSURA  Hitoshi FUJIMOTO  Shun-ichi KUROHMARU  Masatoshi MATSUO  Yasuo KOHASHI  Masayoshi TOUJIMA  Tomonori YONEZAWA  Kiyoshi OKAMOTO  Yasuo IIZUKA  Hiromasa NAKAJIMA  Junji MICHIYAMA  

     
    PAPER

      Vol:
    E81-C No:5
      Page(s):
    708-717

    We have developed a low bit-rate video coding using a video digital signal processor (DSP) called VDSP1χ, which performs real-time encoding and decoding for discrete cosine transform-(DCT-) based algorithms, such as ITU-T H. 261, H. 263 and wavelet-based subband encoding algorithms. This LSI features a processing unit which implements wavelet filters at high speeds, a compact DCT circuit, and a fast, flexible DRAM interface for low-cost systems. This system is capable of processing quarter common intermediate format (QCIF)(176144 pixels) size pictures at a rate greater than 15 frames/s.

  • 2-D Curved Shape Recognition Using a Local Curve Descriptor and Projective Refinement

    Kyoung Sig ROH  In So KWEON  

     
    PAPER-Image Processing,Computer Graphics and Pattern Recognition

      Vol:
    E81-D No:5
      Page(s):
    441-447

    In this paper, we propose a descriptor as a shape signature and the projective refinement as a verification method for recognizing 2D curved objects with occlusions from their partial views. For an extracted curve segment, we compute a series of the geometric invariance of equally spaced five co-planar points on the curve. Thus the resulting descriptor is invariant only under rotation, translation, and scale, but sufficient similarity is preserved even under large distortions. It is more stable and robust since it does not need derivatives. We use this transformation-invariant descriptor to index a hash table. We show the efficiency of the method through experiments using seriously distorted images of 2-D curved objects with occlusions.

  • 5. 4 GOPS, 81 GB/s Linear Array Architecture DSP

    Akihiko HASHIGUCHI  Masuyoshi KUROKAWA  Ken'ichiro NAKAMURA  Hiroshi OKUDA  Koji AOYAMA  Mitsuharu OHKI  Katsunori SENO  Ichiro KUMATA  Masatoshi AIKAWA  Hirokazu HANAKI  Takao YAMAZAKI  Mitsuo SONEDA  Seiichiro IWASE  

     
    PAPER

      Vol:
    E81-C No:5
      Page(s):
    661-668

    A programmable DSP with linear array architecture for real-time video processing is reported. It achieves a processing rate of 5. 4 GOPS and 81GB/s memory bandwidth using Dual Sense Amplifier architecture. A low-power-supply pipeline decreases power consumption and a time shared bit-line reduces chip area. It has 4320 processor elements and a 1. 1 Mbit 3-port memory. The DSP can be applied to HDTV signals with its 75 MHz peak I/O rate. Sufficient programmability is provided to execute video format conversion such as image size conversion and Y/C separation, and picture quality improvement such as noise reduction and image enhancement. The chip was fabricated using 0. 4 µm CMOS triple metal technology with a 15. 12 mm 14. 95 mm die. It operates at 50 MHz and consumes 0. 53 W/GOPS at 3. 3 V.

  • A VLIW Geometry Processor with Software Bypass Mechanism

    Yasunori KIMURA  Akira ASATO  Toshihiro OZAWA  Hiroshi NAKAYAMA  

     
    PAPER

      Vol:
    E81-C No:5
      Page(s):
    669-679

    This paper describes the 'Procyon' processor which is to be used for geometry processing. The objective of this processor is to provide a high performance geometry processor to support next generation 3D graphics such as game and CAD applications. The Procyon processor is a four parallel VLIW processor which makes hardware logic simple. We are pursuing performance improvement by compiler optimization. Procyon has a unique feature called 'Software bypass' as well as special hardware to support 3D graphics processing. Software bypass enables the compiler to make accesses to data on hardware bypass lines. By using this information, the compiler can schedule instructions much more freely and generates efficient VLIW code. Other features of Procyon are multiply-add-accumulate instruction, SIMD instructions and clipping instructions. Procyon VLIW code is held in compacted form, which improves memory performance. A program development environment, such as a pipeline simulator and an assembly code parallelizer, is also prepared for system and application programmers. Preliminary simulation results demonstrate that a performance of 2. 6 M polygons per second at 125 MHz Procyon is attained.

  • Exact Expected Test Length Generated by LFSRs for Circuits Containing Hard Random-Pattern-Resistant Faults

    Kazuhiko IWASAKI  Hiroyuki GOTO  

     
    LETTER

      Vol:
    E81-A No:5
      Page(s):
    885-888

    The exact expected test lengths of pseudo-random patterns that are generated by LFSRs are theoretically analyzed for a CUT containing hard random-pattern-resistant faults. The exact expected test lengths are also analyzed when more than one primitive polynomials are selected.

  • A Channel Assignment Scheme for Integrated Services in DS-CDMA Cellular Systems

    SooKun KWON  HyoungGoo JEON  KyungRok CHO  

     
    LETTER-Mobile Communication

      Vol:
    E81-B No:5
      Page(s):
    1126-1130

    A novel channel assignment scheme in DS-CDMA cellular systems is proposed, which overcomes the handoff interruptions of delay sensitive services by increasing the probability that soft handoff occurs in handoff for them. For that purpose, the priority of using the frequency channels served by all of cells is given to delay sensitive services over delay insensitive ones.

  • A Multiscale Antidiffusion and Restoration Approach for Gaussian Blurred Images

    Qiang LI  Yasuo YOSHIDA  Nobuyuki NAKAMORI  

     
    PAPER-Digital Signal Processing

      Vol:
    E81-A No:5
      Page(s):
    895-903

    Antidiffusion is a process running the diffusion equation reversely in the time domain. Though extremely important for image restoration of the Gaussian blur, it is a horribly ill-posed problem, since minor noise leads to very erroneous results. To solve this ill-posed problem stably, in this paper we first apply a multiscale method to decompose images into various scale components using the Gaussian and Laplacian of Gaussian (LOG) filters. We then show that the restored images can be reconstructed from the components using shrunk Gaussian and LOG filters. Our algorithm has a closed form solution, and is robust to noise because it is performed by the integration computation (convolution), contrasting with the differential computation required by direct discretization of the antidiffusion equation. The antidiffusion algorithm is also computationally efficient since the convolution is row and column separable. Finally, a comparison between the algorithm and the well-known Wiener filter is conducted. Experiments show that our algorithm is really stable and images can be restored satisfactorily.

13781-13800hit(16314hit)