Two families of rapidly synchronizable spreading codes are compared using the same component codes. The influence of component code choice is also discussed. It is concluded that correlation, code-division multiple-access (CDMA) and information security (measured by the value of linear complexity) properties of Kronecker sequences are considerably better than those of Combination sequences. Combination sequences cannot be recommended for CDMA use unless the number of active users is few. CDMA performance of Kronecker sequences is almost comparable with that of linear pseudonoise (PN) code families of equal length when a Gold or Kasami code is used as the innermost code and the Barker code is used as the outermost code to guarantee satisfactory correlation and CDMA properties. Kronecker sequences possess a considerably higher value of linear complexity than those of the corresponding non-linear Geffe and majority logic type combination sequences. This implies they are highly non-linear codes due to the Kronecker product construction method. It is also observed that the Geffe type Boolean combiner resulted in better correlation and CDMA performance than with majority logic. The use of the purely linear exclusive-or combiner for considerable reduction of code synchronization time is not found recommendable although it results in good CDMA performance.

The required building blocks of CMOS fuzzy chips capable of performing as adaptive fuzzy systems are described in this paper. The building blocks are designed with mixed-signal current-mode cells that contain low-resolution A/D and D/A converters based on current mirrors. These cells provide the chip with an analog-digital programming interface. They also perform as computing elements of the fuzzy inference engine that calculate the output signal in either analog or digital formats, thus easing communication of the chip with digital processing environments and analog actuators. Experimental results of a 9-rule prototype integrated in a 2. 4-µm CMOS process are included. It has a digital interface to program the antecedents and consequents and a mixed-signal output interface. The proposed design approach enables the CMOS realization of low-cost and high-inference fuzzy systems able to cope with complex processes through adaptation. This is illustrated with simulated results of an application to the on-line identification of a nonlinear dynamical plant.

Simplification orderings, like the recursive path ordering and the improved recursive decomposition ordering, are widely used for proving the termination property of term rewriting systems. The improved recursive decomposition ordering is known as the most powerful simplification ordering. Recently Jouannaud and Rubio extended the recursive path ordering to higher-order rewrite systems by introducing an ordering on type structure. In this paper we extend the improved recursive decomposition ordering for proving termination of higher-order rewrite systems. The key idea of our ordering is a new concept of pseudo-terminal occurrences.

This paper describes a new architecture-based DSP processor, which consists of n n mesh multiprocessor for digital signal processing. A prototype chip, RCDSP9701 has been designed and implemented using a CMOS 0. 6 µm process. This architecture has better performance compare to the traditional microprocessor solution to Digital Signal Processing. The proposed method poses remarkable flexibility compare to ASIC (Application Specified Integrated Circuits) approach for Digital Signal Processing applications. In addition, the proposed architecture is fault tolerant and suitable for parallel computing applications. In this paper, an implementation into a silicon chip of the new architecture is presented to give a better understanding of our work.

This paper presents Power-Pro architecture (Programmable Power Management Architecture), a novel processor architecture for power reduction. The Power-Pro architecture has two key functionalities: (i) Supply voltage and clock frequency of a microprocessor can be dynamically varied, and (ii) active datapath width can be dynamically adjusted to the precision of each operation. The most unique point of this architecture is that software programmers can directly specify the requirements of applications such as real-time constraints and precision of the operations. To make programmable power management possible, Power-Pro architecture equips special instructions. Programmers can vary the supply voltage, the clock frequency and the active datapath width dynamically by the instructions. Experimental results show that power consumption for a variety of applications are dramatically reduced by the Power-Pro architecture.

In the design of nonlinear reliable controllers, one major issue is to solve for the solutions of the Hamilton-Jacobi inequality. In general, it is hard to obtain a closed form solutions due to the nonlinear nature of the inequality. In this paper, we seek for the existence conditions of quadratic type positive semidefinite solutions of Hamilton-Jacobi inequality. This is achieved by taking Taylor's series expansion of system dynamics and investigating the negative definiteness of the associated Hamilton up to fourth order. An algorithm is proposed to seek for possible solutions. The candidate of solution is firstly determined from the associated algebraic Riccati inequality. The solution is then obtained from the candidate which makes the truncated fourth order polynomial of the inequality to be locally negative definite. Existence conditions of the solution are explicitly attained for the cases of which system linearization possesses one uncontrollable zero eigenvalue and a pair of pure imaginary uncontrollable eigenvalues. An example is given to demonstrate the application to reliable control design problem.

This paper describes methods of tracking of moving objects in a cluttered background by integrating optical flow, depth data, and/or uniform brightness regions. First, a basic method is introduced which extracts a region with uniform optical flow as the target region. Then an extended method is described in which optical flow and depth are fused. A target region is extracted by Baysian inference in term of optical flow, depth and the predicted target location. This method works only for textured objects because optical flow or depth are extracted for textured objects. In order to solve this problem, uniform regions in addition to the optical flow are used for tracking. Realtime human tracking is realized for real image sequences by using a real time processor with multiple DSPs.

In this study, a coupled chaotic circuits network is realized by real circuit elements. By using a simple circuit converting generating spatial patterns to digital signal, irregular self-switching phenomenon of the appearing patterns can be observed as real physical phenomenon.

This letter presents a new algorithm for improving the Signal to Noise Ratio (SNR) of complex sinusoidal signals contaminated by additive Gaussian noises using sum of Higher-Order Statistics (HOS). We conduct some computer simulations to show that the proposed algorithm can improve the SNR more than 7 dB compared with the conventional coherent integration when the SNR of the input signal is -10 dB.

This paper proposes a dual port color palette SRAM using a single bit line cell. Since the single bit line cell consists of fewer bit lines and transistors than standard dual port cells, it is able to reduce the area. However, the cell has had a problem in writing a high level. The port swap architecture solves the problem without any special mechanism such as a boot strap. In the architecture, each of two bit lines is assigned to the read/write MPU port and the read only pixel port, respectively. When writing a low level, the MPU port uses pre-assigned bit line. On the other hand, when writing a high level, the MPU port uses the bit line assigned to the pixel port by a swap operation. During the swapping, the pixel port continues the read operation by using the bit line assigned to the MPU port. A color palette using this architecture is fabricated with a 0. 5 µm CMOS process technology. The memory cell size reduces by up to 43% compared with standard dual port cells. The color palette is able to supply the pixel data at 300 MHz at the supply voltage of 3.3 V. This speed is enough to support the practical highest resolution monitors in the world.

This paper proposes a new method for dynamically controlling the clock speed of a processor in order to reduce power consumption without decreasing system performance. It automatically tunes the processor's speed by monitoring its activities and avoiding useless work so as not to exhaust the battery energy. Experiments with performance bottlenecks caused by disk activities show that the proposed method is very effective in comparison with the traditional one, in which the processor's speed is fixed.

We demonstrate a very simple and compact optical transceiver diode module using a passive alignment on a silicon bench with a V-groove. The excess loss caused by the passive alignment of an optical transceiver diode and a flat-end optical fiber is only 0. 6 dB. A high coupling efficiency of -4. 3 dB is obtained. This results in a high responsivity with a wavelength- and polarization-independence of 0. 5 dB over a 70 nm wavelength range and in good laser performance.

In this paper, experimental results of evaluating dialogue strategies of confirmation with a noisy channel are presented. First, the types of errors in task-oriented dialogues are investigated and classified as communication, dialogue, knowledge, problem solving, or objective errors. Since the errors are of different levels, the methods for recovering from errors must be examined separately. We have investigated that the dialogue and knowledge errors generated by communication errors can be recovered through system confirmation with the user. In addition, we examined that the manner in which a system initiates dialogue, namely, dialogue strategies, might influence the cooperativity of their interactions depending on the frequency of confirmations and the amount of information conveyed. Furthermore, the choice of dialogue strategies will be influenced by the rate of occurrence of communication errors in a communication channel and related to the properties of the task, for example, the difficulty in achieving a goal or the frequency of the movement of initiatives. To verify these hypotheses, we prepared a testbed task, the Group Scheduling Task, and examined it through a computer-to-computer dialogue simulation in which one system took the part of a scheduling system and the other system acted as a user. In this simulation, erroneous input for the scheduling system was also developed. The user system was designed to act randomly so that it could simulate a real human user, while the scheduling system was devised to strictly follow a particular dialogue strategy of confirmation. The experimental results showed that a certain amount of confirmation was required to overcome errors when the rate of occurrence of communication errors was high, but that excessive confirmation did not serve to resolve errors, depending on the task involved.

An elastic-Vt CMOS circuit is proposed which facilitates both high speed and low power consumption at low supply voltages. This circuit permits fine-grain power control on each multiple circuit block composing a chip, and it is not sensitive to design factors as device-parameter deviations or operating-environment variations. It also does not require any such additional fabrication technology as triple-well structure or multi-threshold voltage. The effectiveness of the circuits design was confirmed in applying it to specially fabricated 16-bit adders and 4-kb SRAMs based on 1. 5-V, 0. 35- µm CMOS technology.

This paper proposes a new processor architecture for manipulating the protocols of digital signal transport systems. In order to offer various kinds of telecommunication services, flexibility as well as high performance is required of digital signal transport systems. To realize such systems, this architecture consists of a core CPU, memories, and dedicated application-specific hardware. Software on the core CPU offers flexibility, while the dedicated hardware provides performance. A computer simulation confirms the efficiency of the architecture.

Merged DRAM/logic LSIs could provide high on-chip memory bandwidth by interconnecting logic portions and DRAM with wider on-chip buses. For merged DRAM/logic LSIs with the memory hierarchy including cache memory, we can exploit such high on-chip memory bandwidth by means of replacing a whole cache line (or cache block) at a time on cache misses. This approach tends to increase the cache-line size if we attempt to improve the attainable memory bandwidth. Larger cache lines, however, might worsen the system performance if programs running on the LSIs do not have enough spatial locality of references and cache misses frequently take place. This paper describes a novel cache architecture suitable for merged DRAM/logic LSIs, called variable line-size cache or VLS cache, for resolving the above-mentioned dilemma. The VLS cache can make good use of the high on-chip memory bandwidth by means of larger cache lines and, at the same time, alleviate the negative effects of larger cache-line size by partitioning each large cache line into multiple sub-lines and allowing every sub-line to work as an independent cache line. The number of sub-lines involved when a cache replacement occurs can be determined depending on the characteristics of programs. This paper also evaluates the cost/performance improvements attainable by the VLS cache and compares it with those of conventional cache architectures. As a result, it is observed that a VLS cache reduces the average memory-access time by 16. 4% while it increases the hardware cost by only 13%, compared to a conventional direct-mapped cache with fixed 32-byte lines.

In this paper we describe the pipeline design and enhanced hardware for fast message handling in a RICA-1 processor, a processing element (PE) in the RWC-1 multiprocessor. The RWC-1 is based on the reduced inter-processor communication architecture (RICA), in which communications are combined with computation in the processor pipeline. The pipeline is enhanced with hardware mechanisms to support fine-grain parallel execution. The data paths of the RICA-1 super-scalar processor are commonly used for communication as well as instruction execution to minimize its implementation cost. A 128-PE system has been built on January 1998, and it is currently used for hardware debugging, software development and performance evaluation.

In merged DRAM/logic LSIs, the DRAM portion could suffer from shorter data retention time because of heat and noise caused by the logic portion. In order to reconsider the DRAM data retention characteristics, this paper formulates and evaluates the performance degradation due to conflicts between normal DRAM accesses and refresh operations. Next, this paper proposes a new DRAM refresh architecture which intends to reduce unnecessary refreshes. This architecture exploits multiple refresh periods. Each row is refreshed with the most appropriate period of them. Reducing the number of refreshes improves the accessibility to DRAM. It is shown that the method reduces the number of refreshes and the degree of the performance degradation of the logic portion.

In merged DRAM/logic LSIs, it is necessary to reduce the number of DRAM refreshes because of higher heat dissipation caused by the logic portion on the same chip. In order to overcome this problem, we propose several DRAM refresh architectures. The basic is to eliminate unnecessary DRAM refreshes. In addition to this, we propose a method for reducing the number of DRAM refreshes by relocating data. In order to evaluate these architectures and method, we have estimated the DRAM refresh count in executing benchmark programs under several models which simulate each combination of them. As a result, in the most effective combination, we have obtained more than 80% reduction against a conventional DRAM refresh architecture for most of benchmark programs. In addition to it, we have taken normal DRAM access into account, even then we have obtained more than 50% reduction for several benchmarks.

In this paper we propose a method to aid a visually impaired person in the operation of a computer running a graphical user interface (GUI). It is based on image processing techniques, using images taken by a color camera placed over a Braille display. The shape of the user's hand is extracted from the image by analyzing the hue and saturation histograms. The orientation of the hand, given by an angle θ with the vertical axis, is calculated based on central moments. The image of the hand is then rotated to a normalized position. The number of pixels in each column of the normalized image is counted, and the result is put in a histogram. By analyzing the coefficient of asymmetry of this histogram, it can be determined whether the thumb is positioned along the pointing finger, or whether it is far from the other fingers. These two positions define two states that correspond to a mouse button up or down. In this way, by rotating the hand and moving the thumb, we can emulate the acts of moving a scroll bar and depressing a mouse button, respectively. These operations can be used to perform tasks in a GUI, such as cut-and-paste, for example. Experimental results show that this method is fast and efficient for the proposed application.