This paper describes our recent developments of ASICs for automotive multiplexing and data communications to implement in-vehicle networks. With the advancement of automotive electronics, there are ever growing needs for in-vehicle networks. One need is associated with solving the problem of an increasing number of electrical signal wires that inevitably accompany the increasing applications of automotive electronics. Another kind of need is concerned with sharing vehicle control data among several electronic control units such as engine, brake, suspension, and steering electronic control units to achieve an integrated vehicle control system for the purpose of obtaining higher performances in vehicle dynamics. In order to reduce the number of signal wires and share the control data, in-vehicle networks based on multiplexing and data communications are required. In this paper, two original communication protocols are presented to respectively cover low- and highi-speed multiplexing and data communications that are two most needed communication speed areas in our present and future automobiles. ASICs for the presented communication protoclos were designed and fabricated, using 2 µm COMS process. They have the chip size of 3.2 mm2.7 mm with 5,000 transistors and 6.9 mm4.9 mm with 18,000 transistors respectively for low- and high-speed multiplexing and data communications. An elaborate bus driver/receiver ASIC required for high-speed multiplexing and data communications was also designed and fabricated, using 35 V DC bipolar process. As one of its distinctive features, it can greatly suppress radio frequency noise radiated from a communication bus. It has the chip size of 4.8 mm3.8 mm that contains 570 device elements. The features of the protocols are given in detail with the descriptions of the developed ASICs.

This paper presents an equation capable of briefly evaluating the length of white noise sequence to be sent as a training signal. The equation is formulated by utilizing the formula describing the convergence property, which has been derived from the IIR filter expression of the NLMS algorithm. The result revealed that the length is directly proportional to I/[K(2-K)] where K is a step gain and I is the number of the adaptive filter taps.

MultiWave data compression algorithm is based on the multiresolution wavelet techniqu for decomposing Electrocardiogram (ECG) signals into their coarse and successively more detailed components. At each successive resolution, or scale, the data are convolved with appropriate filters and then the alternate samples are discarded. This procedure results in a data compression rate that increased on a dyadic scale with successive wavelet resolutions. ECG signals recorded from patients with normal sinus rhythm, supraventricular tachycardia, and ventriular tachycardia are analyzed. The data compression rates and the percentage distortion levels at each resolution are obtained. The performance of the MultiWave data compression algorithm is shown to be superior to another algorithm (the Turning Point algorithm) that also carries out data reduction on a dyadic scale.

This paper gives a model to explain one phenomenon found in the process of creative concept formation, i.e. the phenomenon that people often get trapped in some state where the mental world remains nebulous and sometimes suddenly make a jump to a new concept. This phenomenon has been qualitatively explained mainly by the philosophers but there have not been models for explaining it quantitatively. Such model is necessary in a new research field to study the systems for aiding human creative activities. So far, the work on creation aid has not had theoretical background and the systems have been built based only on trial and error. The model given in this paper explains some aspects of the phenomena found in creative activities and give some suggestions for the future systems for aiding creative concept formation.

The ray-tracing algorithm can synthesize very realistic images. However, the ray tracing is very time consuming. To solve this problem, a load balancing strategy using temporal coherence between images in an animation is presented for balancing computational loads among processing elements of a parallel processng system. Our parallel processing model is based on a space subdivision method for the ray-tracing algorithm. A subdivided object space is distributed among processing elements of the parallel system. To clarify the effectiveness of the load balancing strategy, we examine the system performance by computer simulation.

The emerging discipline of responsive systems demands fault-tolerant and real-time performance in uniprocessor, parallel, and distributed computing environments. The new proposal for responsiveness measure is presented, followed by an introduction of a model for responsive computing. The model, called CONCORDS (CONsensus/COmputation for Responsive Distributed Systems), is based on the integration of various forms of consensus and computation (progress or recovery). The consensus tasks include clock synchronization, diagnosis, checkpointing scheduling and resource allocation.

The design of a high speed self-routing network switch module is described. Clock distribution and timing design to achieve high-speed operation are considered. A 88-port self-routing Benes network switch prototype on multi-chip module is fabricated using 44-port space division switch LSIs. The switch module achieves a maximum measured clock frequency of 750MHz under switching operation. Resultant total throughput of the switch module is 12Gbit/s.

Responsive protocols are communication protocols which ensure timely and reliable recovery when error events occur. Protocol synthesis for design of responsive protocols is to derive a protocol specification based on a service specification. In the previous methods, if the service specification includes simultaneous transmission of primitives from a high layer to a low layer through different service access points, then the derived protocol specification includes protocol errors of unspecified reception caused by message collisions. Also, they only includes a recovery function such as retransmission of messages. This is not enough for recovery from abnormal states due to coordination loss. This paper extends a class of derived protocol specifications to include message collisions which usually occur in real communication protocols. Furthermore, this paper proposes a new method for synthesis of a responsive protocal specification derived from a service specification such that the derived protocol specification is free from protocol erros of unspecified receptions caused by message collisions and includes two recovery functions: message retransmission and checkpoint restart functions.

A responsive network architecture is essential in future open distributed systems. In this paper, a framework that provides the foundations for a responsive network architecture for an internetworking environment is proposed. It is called the Virtually Separated Link (VSL) model. By incorporating this framework, communication of both data and control information can be completed in bounded time. Consequently, a protocol can initiate a recovery mechanism in bounded time, or allow an application to do the same. Its functionalities augment existing resource reservation protocols that support multimedia communication. An overview of a real-time network protocol that is based on this framework is also presented.

Space-time tradeoff is a very fundamental issue to design a fault-tolerant real-time (called responsive) system. Routing a message in large computer networks is efficient when each node knows the full topology of the whole network. However, in the hierarchical routing schemes, no node knows the full topology. In this paper, a tradeoff between an optimality of path length (message delay: time) and the amount of topology information (routing table size: space) in each node is presented. The schemes to be analyzed include K-scheme (by Kamoun and Kleinrock), G-scheme (by Garcia and Shacham), and I-scheme (by authors). The analysis is performed by simulation experiments. The results show that, with respect to average path length, I-scheme is superior to both K-scheme and G-scheme, and that K-scheme is better than G-scheme. Additionally, an average path length in I-scheme is about 20% longer than the optimal path length. On the other hand, for the routing table size, three schemes are ranked in reverse direction. However, with respect to the order of size of routing table, the schemes have the same complexity O (log n) where n is the number of nodes in a network.

A stored channel simulator for digital mobile radio enviroments is proposed, which enables the field tests in the laboratory under identical conditions, since it can reproduce the actual multipath radio channels by using the channel impulse responses (CIR's) measured in the field. Linear interpolation of CIR is introduced to simplify the structure of the proposed simulator. The performance of the proposed simulator is confirmed by the laboratory tests.

This paper proposes a new method of phoneme power control for speech synthesis by rule. The innovation of this method lies in its use of the phoneme environment and the relationship between speech power and pitch frequency. First, the permissible threshold (PT) for power modification is measured by subjective experiments using power manipulated speech material. As a result, it is concluded that the PT of power modification is 4.1 dB. This experimental result is significant when discussing power control and gives a criterion for power control accuracy. Next, the relationship between speech power and pitch frequency is analyzed using a very large speech data base. The results show that the relationship between phoneme power and pitch frequency is affected by the kind of phoneme, the adjoining phonemes, rising or falling pitch, and initial or final position in the sentence. Finally, we propose that the phoneme power should be controlled by pitch frequency and phoneme environment. This proposal is implemented in a waveform concatenation type text-to-speech synthesizer. This new method yields an averaged root mean square error between real and estimated speech power of 2.17 dB. This value indicates that 94% of the estimated power values are within the permissible threshold of human perception.

This paper presents a method for verifying safety property of a communication protocol modeled as two extended communicating finite-state machines with two unbounded FIFO channels connecting them. In this method, four types of atomic formulae specifying a condition on a machine and a condition on a sequence of messages in a channel are introduced. A human verifier describes a logical formula which expresses conditions expected to be satisfied by all reachable global states, and a verification system proves that the formula is indeed satisfied by such states (i.e. the formula is an invariant) by induction. If the invariant is never satisfied in any unsafe state, it can be concluded that the protocol it safe. To show the effectiveness of this method, a sample protocol extracted from the data transfer phase of the OSI session protocol was verified by using the verification system.

Multiplication-accumulation is the basic computation required for image filtering operations. For real-time image filtering, very high throughput computation is essential. This work proposes a hardware algorithm for an application-specific VLSI architecture which realizes an area-efficient high throughput multiplier-accumulator. The proposed algorithm utilizes a priori knowledge of filter mask coefficients and optimizes number of basic hardware components (e.g., full adders, pipeline latches, etc.). This results in the minimum area VLSI architecture under certain input/output constraints.

Material research on capacitor dielectrics for DRAM applications is reviewed. The state of the art technologies to prepare Si3N4,Ta2O5, and SrTiO3 thin films for capacitors are described. The down-scaling limits for Si3N4 and Ta2O5 capacitors seem to be 3.5 and 1.5 nm SiO2 equivalent thickness, respectively. Combined with a rugged polysilicon electrode surface,Si3N4 and Ta2O5 based-capacitors are available for 256 Mbit and 1 Gbit DRAMs. At the present time, the minimum SiO2 equivalent thickness for high permittivity materials is around 1 nm with the leakage current density of 10-7 A/cm2. Among the great variety of ferroelectrics, two families of materials,i.e., Pb (Zr, Ti) O3 and (Ba, Sr) TiO3 have emerged as the most promising candidates for 1 Gbit DRAMs and beyond. If the chemical vapor deposition technology can be established for these materials, capacitor dielectrics should not be a limiting issue for Gbit DRAMs.

The paper indicates the importance of suitability assesment in speech synthesis applications. Human factors involved in the use of a synthetic speech are first discussed on the basis of an example of a newspaper company where synthetic speech is extensively used as an aid for proofreading a manuscript. Some findings obtained from perceptual experiments on the subjects' preference for paralinguistic properties of synthetic speech are then described, focusing primarily on the suitability of pitch characteristics, speaker's gender, and speaking rates in the task where subjects are asked to proofread a printed text while listening to the speech. The paper finally claims the need for a flexibile speech synthesis system which helps the users create their own synthetic speech.

The semiconductor technology has been progressing with a rate of 4 times per every 3 years, and the semiconductor industry has been expanding with the annual growth rate of around 14% in average. Recently, however, the situation seems to be somewhat changing. This paper investigates the trends in the past of VLSI technologies and performances of VLSI chips, of the R & D and equipment investments, and of the production and design costs. By extrapolating these trends, the future prospects for VLSIs are given in both the technology and the economics. According to these prospects, (1) 1 Gbit DRAMs and 50 M transistor system VLSIs would be realized before 2000, (2) investments for R & D and production equipments will steeply increase up to the unreasonable value, and (3) the delay in demand will become longer, which will make the return on investment difficult. As some of the key issues for overcoming these difficulties, the reduction in the investment and the cost,the alliance, and the market creation are discussed.

New memory-macrocell architecture has been developed to obtain high-performance macrocells with a short design Turn-Around-Time (TAT) in ASIC design. The authors propose row- and column-sliceable macrocell architecture in which only nine kinds of rectangular-functional cells, called leaf-cells, are abutted to form macrocells of any sizes. The row-sliceable structure of peripheral circuits is possible due to a newly-developed channel-embedded address decoder combined with via-hole programming. Macrocell performance, especially access time, is kept at a high level by the distributed driver configuration. Zero address-setup time during write operation is actualized by delaying internal write timing with a new delay circuit. A short design TAT of 30 minutes is accomplished due to the simplicity of both macrocell generation and the checking procedure. The macrocells are designed with gate-array and full-custom style, and fabricated with 0.5 µm CMOS technology.

This paper describes automatic generation of speech synthesis rules which predict a stress level for each bunsetsu in long noun phrases. The rules are inductively inferred from a lot of speech data by using two kinds of tree-based methods, the conventional decision tree and the SBR-tree methods. The rule sets automatically generated by two methods have almost the same performance and decrease the prediction error to about 14 Hz from 23 Hz of the accent component value. The rate of the correct reproduction of the change for adjacent bunsetsu pairs is also used as a measure for evaluating the generated rule sets and they correctly reproduce the change of about 80%. The effectiveness of the rule sets is verified through the listening test. And, with regard to the comprehensiveness of the generated rules, the rules by the SBR-tree methods are very compact and easy to human experts to interpret and matches the former studies.

This paper presents a high-density multiple-valued content-addressable memory (MVCAM) based on a floating-gate MOS device. In the proposed CAM, a basic operation performed in each cell is a threshold function that is a kind of inverter whose threshold value is programmable. Various multiple-valued operations for data retrieval can be easily performed using threshold functions. Moreover, each cell circuit in the MVCAM can be implemented using only a single floating-gate MOS transistor. As a result, the cell area of the four-valued CAM are reduced to 37% in comparison with that of the conventional dynamic CAM cell.