This paper presents a delivery mechanism using a spectrum delivery switch (SDS) in a microcell system. In our fiber-optic microcell systems, modulators, demodulators and spectrum delivery switches are installed in a central station. A spectrum delivery switch controls provide flexible dynamic channel assignment and functions as a hand over algorithm. This control method employs a TDMA time slot switch and a MODEM connection switch. The relation between blocking probability and offered traffic are described and computer simulation results are shown. The results indicate an improvement in this blocking probability over conventional systems.

An optical receiver for hybrid SCM video distribution systems that distribute AM, QAM (quadrature amplitude modulation) and FM TV signals simultaneously is investigated. We propose a novel receiver configuration called the Frequency Division type Receiver (FDR) with consists of a photo detector, filter, and multiple preamplifiers. The receiver is compared with existing receivers in terms of optical sensitivity, distortion characteristics, and configuration simplicity. We clarify that the newly developed FDR type receiver is most suitable for hybrid SCM video distribution systems.

We introduce automatic procedures for generating and verifying sufficient correctness properties of synchronous processors. The targeted circuits are synchronous array processors designed from localized, highly regular data dependency graphs (DDGs). The specification, in the form of a DDG, is viewed as a maximally parallel circuit. The implementation, on the other hand, is a (partially) serialized circuit. Since these circuits are not equivalent from an automata-theoretic viewpoint, we define the correctness of the implementation against the specification to mean that a certain relation (called the β-relation) holds between the two. We use a compositional approach to decouple the verification of the control circuitry from that of the data path, thereby gaining efficiency. An array processor in isolation may not have a definite flow of control, because control may reside in the data stream. Therefore, for the purpose of verification, we construct an auxiliary machine, which keeps a timing reference and generates control signals abstracted from a typical data stream. Sufficient correctness conditions are expressed as past-tense computation tree logic (CTL) formulae and verified by CTL model-checking procedures. Experimental results of the verification of a matrix multiplication array and a Gaussian elimination array are presented.

Test pattern generation is getting much harder as the circuit size becomes larger. One problem is that it tends to take much time and another one is that it is difficult to detect redundant faults. Aiming to cope with these problem, an enhanced unique sensitization technique is proposed in this paper. This powerful global implication reduces the number of backtracks with reasonable computational time. And a fast test pattern generator featuring this unique sensitization demonstrates its performance using large benchmark circuits with over ten thousands of gates. It takes only a minute to detect all testable faults and to identify all redundant faults of 20,000 gates circuit on a workstation.

In this paper, a new method of synthesizing multi-level logic circuits directly from binary decision diagrams (BDDs) is proposed. In the simple multiplexer implementation, the depth of the synthesized circuit was always O (n), where n is the number of input variables. The new synthesis method attempts to reduce the depth of circuits. The depth of the synthesized circuits is O (log n log w) where w is the maximum width of given BDDs. The synthesized circuits are 2-rail-input 2-rail-output logic circuits. The circuits have good testability; it is proved that the circuits are robustly path-delay fault testable and also totally self-checking for single stuck-at faults.

Acceleration techniques have been incorporated into the generalized method of characteristics (GMC) to perform transient analysis of uniform transmission lines, for the special case when the transmission lines are driven by digital signals. These techinques have been proved to improve the simulation speed to a great extent when the analysis is carried out using iterative waveform relaxation method. It has been identified that the load impedance connected to the transmission line has a bearing on the efficiency of one of these acceleration techniques. Examples of an RLCG line terminated with linear loads as well as nonlinear loads are given to illustrate the advantage of incorporating these acceleration techniques.

Reducing communication complexity is a viable approach to multilevel logic synthesis. A communication complexity based approach was proposed previously. In the previous works, only disjoint input decomposition was considered. However, for certain types of circuits, the circuit size can be reduced by using overlapped decomposition. In this paper, we consider overlapped decompositions. Some design issues for overlapped decompositions such as detecting globals" and deriving subfunctions are addressed. Moreover, the Decomposition Don't Cares (DDC) is considered for improving the decomposed results. By using these techniques together, the area and delay of circuits can be further minimized.

This paper presents a description and an analysis of three standard" hardware description languages (HDLs): Very High Speed Integrated Circuit HDL (VHDL), Verilog-HDL, and Unified Design Language for Integrated Circuits (UDL/I), Kyoto University Education Chip (KUE-Chip) is used as a design benchmark to compare the features and syntax of VHDL, Verilog-HDL, and UDL/I.

System and chip synthesis must evaluate candidate Register-Transfer (RT) architectures with respect to finished physical designs. Current RT level cost measures, however, are highly simplified and do not reflect the real physical disign. Complete physical design, on the other hand, is quite costly, and infeasible to be iterated many times. In order to establish a more realistic assessment of layout effects, we propose a new layout model which efficiently accounts for the effects of wiring and floorplanning on the area and performance of RT level designs, before the physical design process. Benchmarking has shown that our model is quite accurate.

A new applicative design language is proposed for developing generators of data-path modules from hardware algorithms. The language includes a set of primitives that represent placement operations, parameterized cells, routing patterns and a set of transformation rules specifying modifications of the module topology without changing its functionality. Using the language, a hardware algorithm designer can easily define both the topological and geometrical specifications of module generation directly at the functional level without engaged in the layout details. A sketch of the language and an example of module design with the language is presented.

In this study, an expression of the regression relationship with less information loss is concretely derived in the form suitable to the existence of amplitude constraint of the observed data and the prediction of response probability distribution. The effectiveness of the proposed method is confirmed experimentally by applying it to the actual acoustic data.

This paper shows that coherent optimization strategies for multilevel systhesis should rely on a good link between the factorization, the technology mapping and the netlist optimization. Factorization options are shown to play a key role. The technology mapping should optimize both area and critical path and only netlist structure preserving" optimization techniques (buffer insertion, gate replication) should be applied first to preserve the factorization decision. Only in a last step resynthesis of critical areas based on a local view is applied. The approach has been experimented on a set of large combinational benchmarks.

This paper reports performance improvement in an optical fiber feeder for microcellular mobile radio systems. A low noise optical receiver using a transformer resonant circuit is described. With this receiver, CNR degradation due to receiver noise is suppressed to less than 0.9dB. Furthermore, two novel techniques, the use of a multiple-LD transmitter and automatic LD input level control, are proposed. The multiple-LD transmitter increases transmitter output power and reduces the transmitter noise. With a dual-LD transmitter, it is possible to increase the optical loss margin by 3.1dB, which corresponds to transmission length expansion of 6.2km, or to improve the received CNR by 2.8dB, which enables communication range expansion. Automatic LD input level control, which optimizes LD input level according to the received radio power, can expand the actual dynamic range of the up link.

In this paper, we investigate various technology aspects in fiber-to-the-microcell systems. Background studies on radio propagation environment and system operations are provided first. The fundamental linearity characteristics of a directly and externally modulated optical links are analyzed next. An overall comparison between the two types of optical links, and system requirements among all types of wireless systems (from macrocells to picocells) are presented. Future research and development directions are also suggested.

Recently, a family of 4-phase sequences (alphabet {1,j,-1,-j}) was discovered having the same size 2r+1 and period 2r-1 as the family of binary (i.e., {+1, -1}) Gold sequences, but whose maximum nontrivial correlation is smaller by a factor of 2. In addition, the worst-case correlation magnitude remains the same for r odd or even, unlike in the case of Gold sequences. The family is asymptotically optimal with respect to the Welch lower bound on Cmax for complex-valued sequences and the sequences within the family are easily generated using shift registers. This paper aims to provide a more accessible description of these sequences.

A new trial of statistical evaluation for an output response of power linear type acoustic systems with nonstationary random input is proposed. The purpose of this study is to predict the output probability distribution function on the basis of a standard type pre-experiment in a laboratoty. The statistical properties like nonstationarity, non-Gamma distribution property and various type linear and non-linear correlations of input signal are reflected in the form of differential operation with respect to distribution parameters. More concretely, the pre-experiment is carried out for a power linear acoustic system excited only by the Gamma distribution type sandard random input. Considering the non-negative random property for the output response of a power linear system, the well-known statistical Laguerre expansion series type probability expression is first employed as the framework of basic probability distribution expression on the output power fluctuation. Then, the objective output probability distribution for a non-stationary case can be easily derived only by successively employing newly introduced differential operators to this basic probability distribution of statistical Laguerre expansion series type. As an application to the actual noise environment, the proposed method is employed for an evaluation problem on the stochastic response probability distribution for an acoustic sound insulation system excited by a nonstationary input noise.

In multidimensional signal sampling, the orthogonal sampling scheme is the simplest one and is employed in various applications, while a non-orthogonal sampling scheme is its alternative candidate. The latter sampling scheme is used mainly in application where the reduction of the sampling rate is important. In three-dimensional (3-D) signal processing, there are two typical sampling schemes which belong to the non-orthogonal samplings; one is face-centered cubic sampling (FCCS) and the other is body-centered cubic sampling (BCCS). This paper proposes a new design method for 3-D band-limiting FIR filters required for such non-orthogonal sampling schemes. The proposed method employs the McClellan transformation technique. Unlike the usual 3-D McClellan transformation, however, the proposed design method uses 2-D prototype filters and 2-D transformation filters to obtain 3-D FIR filters. First, 3-D general sampling theory is discussed and the two types of typical non-orthogonal sampling schemes, FCCS and BCCS, are explained. Then, the proposed design method of 3-D bandlimiting filters for these sampling schemes is explained and an effective implementation of the designed filters is discussed briefly. Finally, design examples are given and the proposed method is compared with other method to show the effectiveness of our methos.

This paper describes an adaptive sensing system with tracking and zooming a moving object in the stable environment. Both the close contour matching technique and the effective determination of zoom ratio by fuzzy control are proposed for achieving the sensing system. First, the estimation of object feature parameters, 2-dimensional velocity and size, is based on close contour matching. The correspondence problem is solved with cross-correlation in projections extracted from object contours in the specialized difference images. In the stable environment, these contours matching, capable of eliminating occluded contours or random noises as well as background, works well without heavy-cost optical flow calculation. Next, in order to zoom the tracked object in accordance with the state of its shape or movement practically, fuzzy control is approached first. Three sets of input membership function--the confidence of object shape, the variance of object velocity, and the object size--are evaluated with the simplified implementation. The optimal focal length is achieved of not only desired size but safe tracking in combination with fuzzy rule matrix constituted of membership functions. Experimental results show that the proposed system is robust and valid for numerous kind of moving object in real scene with system period 1.85 sec.

In this paper, we evaluate the sustained performance of the prototype SHD (Super High Definition) image processing system NOVI- HiPIPE, and discuss the requirements of a real-time SHD image processing system. NOVI- HiPIPE is a parallel DSP system with 128 PEs (Processing Elements), each containing one vector processor, and its peak performance is 15 GFLOPS. The measured performance of this system is at least 100 times higher than that of the Cray-2 (single CPU), but is still insufficient for real-time SHD image coding. When coding SHD moving images at 60 frames per second with the JPEG algorithm, the performance must be at least ten times faster than is now possible with NOVI- HiPIPE. To extract higher performance from a parallel processing system, the system architecture must be suitable for the implemented process. The advantages of NOVI- HiPIPE are its mesh network and high performance pipelined vector processor (VP), one of which is installed on each PE. When most basic SHD image coding techniques are implemented on NOVI- HiPIPE, intercommunication occurs only between directly connected PEs, and its cost is very low. Each VP can efficiently execute vector calculations. which occur frequently in image processing, and they increase the performance of NOVI- HiPIPE by a factor of from 20 to 100. In order to further improve the performance, the speed of memory access and bit operation must be increased. The next generation SHD image processing system must be built around the VP, an independent function block which controls memory access, and another block which executes bit operations. To support the input and output of SHD moving images and the inter-frame coding algorithms, the mesh network should be expanded into a 3D-cube.

This paper describes a new automated approach to generating the patterns of CMOS leaf cells from transistor-level connectivity data. This method can generate CMOS leaf cells that are configurable to a macro cell satisfying user-specified constraints. The user-specified constraints include the aspect ratio and port positions of the macro cell. We propose a top-down method for converting the macro cell level constratints to leaf cell level ones. Using this method, a variety of customized macro cells can be designed in a short turn-around time. The method consists of four processes--diffusion sharing, initial placement, placement improvement and routing--which culminate in the automatic generation of symbolic representations. Using a compactor, those symbolic representations can be converted to physical patterns which are gathered into a macro cell by a macro generator. We define various objective functions to improve unit pair placement. We also introduce five ways to optimize leaf cell area: 1) multi-row division, 2) gate division 3) rotation, 4) power line and diffusion overlapping and 5) reconstruction of hierarchical structure. The proposed approach has been applied to various kinds of CMOS leaf cells. Experimental results show that the generated cells have almost the same areas as those generated by conventional bottom-up approaches in leaf and macro cell layouts. This approach offers a further advantage in that the various-sized macro cells required by layout disigners can also be generated.