This paper proposes a new method for automatic improvement in image quality through adjusting the image sharpness. This method does not need prior knowledge about image blur. To improve image quality, the sharpness must be adjusted to an optimal value. This paper shows a new method to evaluate sharpness without MTF. It is considered that the human visual system judges image sharpness mainly based upon edge area features. Therefore, attention is paid to the high spatial frequency components in the edge area. The value is defined by the average intensity of the high spatial fequency components in the edge area. This is called the image edge sharpness" value. Using several images, edge sharpness values are compared with experimental results for subjective sharpness. According to the experiments, the calculated edge sharpness values show a good linear relation with subjective sharpness. Subjective image sharpness does not have a monotonic relation with subjective image quality. If the edge sharpness value is in a particular range, the image quality is judged to be good. According to the subjective experiments, an optimal edge sharpness value for image quality was obtained. This paper also shows an algorithm to alter an image into one which has another edge sharpness value. By altering the image, which achieves optimal edge sharpness using this algorithm, image sharpness can be optimally adjusted automatically. This new image improving method was applied to several images obtained by scanning photographs. The experimental results were quite good.

In the ISAR (Inverse Synthetic Aperture Radar), when a target is to be recognized by use of the radar image produced from the radar echoes, it is important first to estimate the scale of the target. To estimate the scale, the rotating motion of the target must be estimated. This paper describes a method for estimating the scale of the target from the information on the radar image by converting the target figure into a simple model and estimating the rotating motion of the target.

An efficient algorithm is presented for finding all solutions of piecewise-linear resistive circuits. In this algorithm, a simple sign test is performed to eliminate many linear regions that do not contain a solution. Therefore, the number of simultaneous linear equations to be solved is substantially decreased. This test, in its original form, requires O(Ln2) additions and comparisons in the worst case, where n is the number of variables and L is the number of linear regions. In this paper, an effective technique is proposed that reduces the computational complexity of the sign test to O(Ln). Some numerical examples are given, and it is shown that all solutions can be computed very efficiently. The proposed algorithm is simple and can be easily programmed by using recursive functions.

Recently, there has been a lot of research on solving combinatorial problems using Binary Decision Diagrams (BDDs), which are very efficient representations of Boolean functions. We have already developed a Boolean Expression Manipulator, which calculates and reduces Boolean expressions quickly based on BDD techniques. This greatly aids our works on developing VLSI CAD systems and solving combinatorial problems. Any combinatorial problem can be described in Boolean expressions; however, arithmetic operations, such as addition, subraction, multiplication, equality and inequality, are also used for describing many practical problems. Arithmetic operations provide simple descriptions of problems in many cases. In this paper, we present an arithmetic Boolean expression manipulator (BEM-), based on BDD techniques. BEM- calculates Boolean expressions containing arithmetic operations and then displays the results in various formats. It can solve problems represented by a set of equalities and inequalities, which are dealt with using 0-1 linear programming. We show the efficient data structure based on BDD representation, algorihms for manipulating Boolean expressions with arithmetic operations, and good formats for displaying the results. Finally we present the specification of BEM- and an example of application to the 8-Queens problem. BEM- is customizable to various applicationa. It has good computation performance in terms of the total time for programming and execution. We expect BEM- to be a helpful tool in research and development on digital systems.

In this paper, an exact algorithm for finding minimum test set which detects all testable stuck-at faults of a given combinational circit is presented. So far several heuristic algorithms for this problem are proposed, but no efficient exact algorithms are known. To solve this exactly, minimum test set problem is formalized as a minimum set covering problem, and then implicit manipulation technique using binary decision diagrams(BDDs) is applied. The algorithm presented in the paper has two contributions. One is utilization of maximal compatible fault set, which can drastically reduce the number of candidates for minimum test set. A new BDD based algorithm for extracting all maximal compatible fault sets is shown. The other is a new implicit manipulation technique handling with huge covering matrix. Actually, the algorithm using this technique can handle minimum set covrering problem with over ten thousand columns in a few minutes. Experiments using ISCAS benchmark circuits show that the algorithm is quite efficient for small(100-300 gates) circuits. A computational complexith of minimum test set problen is much higher than that of ordinary test pattern generation problem, so that practical signifcance of this method is not high. But the algorithm is still useful for evaluation of other heuristic algorithms. furthermore, this implicit manipulation technique can also be applied to other minimumset covering problems.

A fully focused Synthetic Aperture Radar (SAR) image can be obtained only if the raw data processing procedure takes into account the space-variance of the SAR system transfer function. This paper presents a nonconventional Fast Fourier Transform (FFT) algorithm which allows an efficient compensation of the space-variant effect. It is specially designed for the SAR data of the Japanese Earth Resources Satellite (JERS-1) but can be extended to different cases.

High performances of CMOS/SOI inverter by simulations of analytical model, reducing the poly-Si gate thickness (tm), and experiments are verified and proposed. It is shown that the tm and gate oxide thickness(tox) are correlated to gate fringing capacitance, which largely influences on the Propagation Delay Time(TPD). Contributions of gate fringing capacitance to CMOS/SIMOX inverter time delay in deep submicrometer gate devices are propounded. Measurements of the fifty-one stage ring oscillator's TPDs are completed for comparison with analytical model. Simulation results by the analytical model, including Time-Dependent Gate Capacitance (TDGC) model, agree well with the experimental results at the same conditions. Simulation results are also predicted that SOI technology is promising for speed enhancement by reducing the poly-Si gate thickness, while the tox remains constant. It is concluded that the TPDs by reducing the tm to zero are improved up to about two times faster than typically fabricated ring oscillator at 350 nm of the tm in deep-submicrometer gate CMOS/SIMOX inverters at room temperature.

The size and weight of marine pulse radar systems must be limited in order to mount them on board boats. However, the azimuthal resolution of a marine radar with a small antenna is degraded by the antenna beam width. It is desirable to use signal processing techniques to increase both the azimuthal resolution and the range resolution of such systems without changing their external configuration. This paper introduces a resolution enhancement method based on deconvolution, which is a kind of inversion. The frequency domain deconvolution method is described first. The effectiveness of the proposed method is shown by simulation. Then, an example of resolution enhancement processing is applied to a pulse radar. The results of practical experiments show that this method is a promising way of upgrading radars by simply processing the received signals.

The transient scattering of a half sine pulse wave by a conducting rectangular cylinder with an open sidewall is rigorously analyzed by using the point matching method (taking into account the edge condition exactly) combined with the fast inversion of Laplace transform. Numerical results are presented for back scattered and forward scattered responses of the far fields when a half sine pulse is incident on the open side and the closed side of the cylinder. The physical meaning of the transient responses is discussed in detail. The comparison of the responses with those by a perfect conducting rectangular cylinder is presented.

This paper presents a Reconfigurable Machine (RM). capable of efficiently implementing a wide range of computationlly complex algorithms. Its highly flexble architecture combining FPGA's with RAM's supports a wide range of applications. Since its "gate-level programmability" allows us to implement various kinds of parallel processing techniques, RM provides a perfomance comparable to exising "special-purpose" engines. The in-circuit reconfiguration capability of FPGA's is used to reload several kinds of configuration data during power on. Thus, RM behaves itself like a general-purpose computer applicable to various kinds of applications by loading programs. A Reconfigurable Machine-(RM-) has been built as the first prototype incorporating five FPGA's and four SRAM memory banks. RM- has been applied to a multiple-delay Logic Simulator (LSIM). Employing pipeline architecture, LSIM has achieved a perfomance of l million gate events per second at 4MHz. The concept of RM is the best solution to the trade-offs between general-purpose machines and special-purpose ones. RM will be a hardware platform accelerating a wide range of applications, also offering an interesting problem in high-level synthesis.

A modern architect can not design high performance computer architecture without thinking all factors of performance from hardware level (logic/layout design) to system level (application programs, operating systems, and compilers). For computer architecture design, there are few practical CAD tools, which support design activities of the architect. In this paper, we propose a CAD tool, called COACH, for computer architecture design. COACH supports architecture design from hardware level to system level. To make a high-performance general purpose computer system, the architect evaluates system performance as well as hardware level performance. To evaluate hardware level performance accurately, logic/layout synthesis tools and simulator are used for evaluation. Logic/layout synthesis tools translate the architecture design into logic circuits and layout pattern and simulator is used to get accurate information on hardware level performance which consists of clock frequency, the number of transistors, power consumption, and so on. To evaluate system level performance, a compiler generator is introducd. The compiler generator generates a compiler of a programming language from the desripition of architecture design. The designed architecture is simulated in the behavior level with programs compiled by the compiler, and the architect can get information on system level performance which consists of program execution steps, etc. From both hardware level performance and system level performance, the architect can evaluate and revise his/her architecture, considering the architecture from hardware level to system level. In this paper, we propose a new design methodology which uses () logic/layout synthesis tools and simulators as tools for architecture design and () a compiler generator for system level evaluation. COACH, a CAD system based on the methodology, is discussed and a prototype of COACH is implemented. Using the design methodology, two processors are designed. The result of the designs shows that the proposed design methodology are effective in architecture design.

This article discusses on PDM (Petri net based Development Methodology) which integrates approaches, modeling methods, design methods and analysis methods in a coherent manner. Although various development techniques based on Petri nets have demonstrated advantages over conventional techniques, those techniques are rather ad hoc and lack an overall picture on entire development process. PDM anticipates to provide a refernce process model to develop distributed systems with various Petri net based development methods. Behavioral properties of distrbuted systems can be an appropriate application domain of PDM.

In this paper, we show that Petri nets can be applied practically to design and analysis of concurrent, parallel and embedded mode systems such as a lift system that is familiar to our daily life. Modeling behavioral characteristics of the lift, we extend a standard Petri net by constant timed transition, faultable transition, stochastic transition and condition transition concepts. Likewise, we prsesnt some results of design and analysis of the system. This method can be applied to design and analysis of another concurrent systems.

The scattering of electromagnetic waves by a dielectric grating with planar slanted-fringe is analyzed using the improved Fourier series expansion method. In the analysis, the slanted grating region is divided into layers to make an assembly of stratified thin modulated index layers. This method can be applied to a wide range of periodic structures and is especially effective in the case of planar slanted grating, because the electromagnetic fields in the each layer can easily be obtained by shifting the solution in the first layer. In this paper, the numerical results are given for grating with rectangular and sinusoidal dielectric profiles, and for TM and TE cases of arbitrary incident angle. The diffraction efficiencies obtained by the presented method are compared with the results by the coupled-wave approach; the influences of the slant angle on the diffraction efficiencies at the Wood's anomaly and at the coupling resonance frequency are also discussed.

A global routing problem is formulated as a multi-commodity network flow problem. The formulation gives no restriction over the shape of a routing pattern and makes it possible to obtain the optimal solution by using a mathematical programming method. Moreover, it can be naturally extended to the problem even optimizing routing length objectives for net delay and clock skew perfomances by using the goal programming method. An approximation algorithm solving the multi-commodity network flow problem is proposed by adding a merge step of wires whose source-sink pairs are exactly the same and a step restricting an area for searching routes. Experimental results show that this global routing algorithm connected with a line-search detailed router can generate a complete routing for interblock routing problems with more than 2400 wires in two industrial chips. The total amount of procassing time for both problems is about 90 minutes on a mainframe computer.

A technique for reducing fiber four-wave mixing (FWM) in multichannel transmissions is proposed. Birefringent elements are inserted on the way of transmission lines. Due to the effect of birefringent elements on the polarization states, the effective crosstalk due to FWM is expected to be 3/16 of that in the worst case in conventional systems.

Most of actual environmental systems show a complicated fluctuation pattern of non-Gaussian type, owing to various kinds of factors. In the actual measurement, the fluctuation of random signal is usually contaminated by an external noise. Furthermore, it is very often that the reliable observation value can be obtained only within a definite fluctuating amplitude domain, because many of measuring equipments have their proper dynamic range and original random wave form is unreliable at the end of amplitude fluctuation. It becomes very important to establish a new signal detection method applicable to such an actual situation. This paper newly describes a dynamical state estimation algorithm for a successive observation contaminated by the external noise of an arbitrary distribution type, when the observation value is measured through a finite dynamic range of measurement. On the basis of the Bayes' theorem, this method is derived in the form of a wide sense digital filter, which is applicable to the non-Gaussian properties of the fluctuations, the actual observation in a finite amplitude domain and the existence of external noise. Differing from the well-known Kalman's filter and its improvement, the proposed state estimation method is newly derived especially by paying our attention to the statistical information on the observation value behind the saturation function instead of that on the resultant noisy observation. Finally, the proposed method is experimentally confirmed too by applying it to the actual problem for a reverberation time measurement from saturated noisy observations in room acoustics.

The Princeton University Behavioral Synthesis System (PUBSS) performs high-level synthesis on communicating processes. The compiler accepts models written in a subset of VHDL, but performs synthesis using a more specialized model, the behavior FSMs (BFSMs), for synthesis. The simulation semantics of VHDL presents challenges in describing behavior without overly constraining that behavior solely to make the simulation work. This paper describes mismatch between the simulation semantics provided by VHDL and the synthesis semantics required for high-level synthesis and describes how we solved these problems in PUBSS.

A model for a large network with an unidirectional linear respone (ULR) is proposed in this letter. This deterministic system has powerful computing properties in very close correspondence with earlier stochastic model based on McCulloch-Pitts neurons and graded neuron model based on sigmoid input-output relation. The exclusive OR problems and other digital computation properties of the earlier models also are present in the ULR model. Furthermore, many analog and continuous signal processing can also be performed using the simple ULR neural network. Several examples of the ULR neural networks for analog and continuous signal processing are presented and show extemely promising results in terms of performance, density and potential for analog and continuous signal processing. An algorithm for the ULR neural network is also developed and used to train the ULR network for many digital and analog as well as continuous problems successfully.

The small-signal negative resistance of QWITT (Quantum Well Transit-Time) diodes is calculated including the effect of field-dependent diffusion coefficient in the frequency range of 10 to 300 GHz. The drift velocity transient effect is also included. The result is compared with those obtained by using constant diffusion coefficients at average electric fields.