Various network resources, including wireless access services and multimedia appliances (device) are expected to be available in ubiquitous computing environments. Since resource availability can change when a user migrates from one place to another, functions to monitor the availability of resources in use and, if necessary, switch from obsolete resources to new ones are necessary for continuous service provision. This paper proposes adaptive terminal middleware called AMID that performs policy-based dynamic resource selection and host-based session management to ease network administrative tasks, and hide session failures and resource changes from applications and a user. AMID supports two kinds of mobility; session maintenance on vertical handoff and device handoff (service mobility). By AMID, a mobile host keeps entire handoff control and session state to eliminate the need for network-layer or intermediate-node mobility support, and mitigate responsibility of devices for session management. AMID realizes a Reliable Virtual Socket (RVS), on top of real sockets, which employs a seamless session handoff mechanism for resource changes, and a reliable session resume mechanism against unplanned disconnection of a wireless link. It achieves seamless session handoff through a proactive soft handoff method; to conceal setup and signaling latency, it initiates setup procedures with neighbor resources in advance of actual handoff and utilizes multiple wireless interfaces and devices redundantly. We implemented AMID and a follow-me audio application on top of it to evaluate the performance. Redirection of audio streams from built-in speakers to external ones, and handoff between 802.11b and Cellular are autonomously performed when a user migrates in the house. We confirmed that AMID achieved reliable session maintenance against wireless link failure, concealed latency of handoff management, and prevented packet loss during handoff.

In this paper, we propose new physical design techniques to reduce crosstalk noise and crosstalk-induced delay variations caused in a nanometer-scale system-on-a-chip (SoC). We have almost eliminated the coupling effect between signal wires by simply optimizing parameters for the automatic place and route methodology. Our approach consists of two techniques, (1) A 3-D optimization technique for tuning the routing grid configuration both in the horizontal and vertical directions. (2) A co-optimization technique for tuning the cell utilization ratio and the routing grid simultaneously. Experiments on the design of an image processing circuit fabricated in a 0.13 µm CMOS process with six layers of copper interconnect show that crosstalk noise is almost eliminated. From the results of a static timing analysis considering the worst-case crosstalk condition, the longest path delay is decreased by about 15% maximum if technique (1) is used, and by about 7% maximum if technique (2) is used. The 7-15% delay reduction has been achieved without process improvement, and this reduction corresponds to between 1/4 and 1/2 generation of process progress.

A fuzzy-like phenomenon in a dynamic neural network is demonstrated and analyzed. The network operates as a dynamic associative memory. Each neuron of the dynamic neural network has an all-or-none output and exponentially decaying refractoriness. When several related patterns are stored in the dynamic neural network and an external stimulus with a property shared by two of the stored patterns is applied to the neural network, the output of the neural network dynamically transits between the two stored patterns. The frequency ratio that the network visits the two stored patterns is dependent on the ratio of the Hamming distances between the external pattern and the two stored patterns. This phenomenon is similar to the human decision-making process, some of which characteristics can be described by fuzzy set theory. A framework for the analysis of this phenomenon is proposed, and is used to derive sufficient conditions which ensure the dynamical transition between the two stored patterns. The properties of the transition in the network are also discussed.

A fully integrated 2 V 2.4 GHz CMOS low-noise amplifier (LNA) is presented in this paper. A negative resistance circuit is used to reduce the parasitic resistors of the on-chip spiral inductor and increase the quality factor (Q). An inductor is added to the common-source and common-gate transistors of the cascode circuit to improve matching and increase power gain. The LNA is designed according to the tsmc 1P4M 0.35 µm process. The parasitic effect of the on-chip spiral inductor was considered. With a 2 V supply, the power gain of the LNA is 19.5 dB, the noise figure is 2.7 dB, and the power dissipation is 15.2 mW. The input third-order intercept point (IIP3) is 0 dBm. The input -1 dB compression point (P-1dB) is -13.9 dBm. The reverse isolation S12 is -44.1 dB.

The Quasi-Delay-Insensitive (QDI) model assumes that all the forks are isochronic. The isochronic-fork assumption requires uniform wire delays and uniform switching thresholds of the gates associated with the forking branches. This paper presents a method for determining such forks that do not have to satisfy the isochronic fork requirements, and presents experimental results that show many isochronic forks assumed for existing QDI circuits do not actually have to be "isochronic" or can be even ignored.

This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) Creation of custom wire load models for clock nets. (2) Use of layout information (actual net capacitance and input signal transition time). The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. Error is within 5% against a real chip, (the same level as that of the transistor-level power analysis), if technique (2) is used, and within 15% if technique (1) is used.

In this paper, an associative memory model with a forgetting process proposed by Mezard et al. is investigated as a means of storing sparsely encoded patterns by the SCSNA proposed by Shiino and Fukai. Similar to the case of storing non-sparse (non-biased) patterns as analyzed by Mezard et al., this sparsely encoded associative memory model is also free from a catastrophic deterioration of the memory caused by memory pattern overloading. We theoretically obtain a relationship between the storage capacity and the forgetting rate, and find that there is an optimal forgetting rate leading to the maximum storage capacity. We call this the optimal storage capacity rate. As the memory pattern firing rate decreases, the optimal storage capacity increases and the optimal forgetting rate decreases. Furthermore, we shown that the capacity rate (i.e. the ratio of the storage capacity for the conventional correlation learning rule to the optimal storage capacity) is almost constant with respect to the memory pattern firing rate.

As we move toward the transition to the IPv6 next generation network environment, it is necessary to realize heterogeneous communications between IPv6 and IPv4 terminals without sacrificing any convenience or frameworks of current communication methods. Mechanisms that satisfy such requirements are called translators. This paper categorizes various translator mechanisms and clarifies their characteristics. As a result of analyses, this paper proposes a SOCKS-based IPv6/IPv4 Translator, and describes its design and implementation. Compared with other translator mechanisms, the SOCKS-based translator have small constraints and good characteristics. For example, it can integrate DNS name resolving procedures, which is an important mechanism for the transition. The translator has already been implemented and it has been proved that it can support typical communication services such as telnet, ftp, http, mail without any problems.

This paper attempts to establish a theory for a general auto-associative memory model. We start by defining a new concept called supporting function to replace the concept of energy function. As known, the energy function relies on the assumption of symmetric interconnection weights, which is used in the conventional Hopfield auto-associative memory, but not evidenced in any biological memories. We then formulate the information retrieving process as a dynamic system by making use of the supporting function and derive the attraction or asymptotic stability condition and the condition for convergence of an arbitrary state to a desired state. The latter represents a key condition for associative memory to have a capability of learning from variant samples. Finally, we develop an algorithm to learn the asymptotic stability condition and an algorithm to train the system to recover desired states from their variant samples. The latter called sample learning algorithm is the first of its kind ever been discovered for associative memories. Both recalling and learning processes are of finite convergence, a must-have feature for associative memories by analogy to normal human memory. The effectiveness of the recalling and learning algorithms is experimentally demonstrated.

In a wireless home network, shadowing is frequently caused by human bodies or furniture. Therefore, relay transmission function is considered for the hub station in Wireless Homelink when the direct communication of terminals is obstructed. However, in relaying high rate isochronous data such as video streams, the bandwidth resource of Wireless Homelink may be crammed with those data. In this paper, we propose an efficient relay scheme--"Pipeline Repeater" for Wireless Homelink. The proposed scheme spatially multiplexes the relay transfer of the isochronous data using antenna directivity. The Pipeline Repeater can relay the isochronous packets as an efficient use of the limited frequency band, and it can be achieved to repeat the high rate data with delay of only one frame. To verify the proposed scheme, we conduct measurements in some actual home environments, and perform the numerical analyses and computer simulations based on the measurements. Our results confirm the efficiency of the Pipeline Repeater scheme.

BiCMOS provides the benefits of both bipolar and CMOS technologies and enables the integration of RF SOCs.

Associative memories composed of sparsely interconnected neural networks (SINNs) are suitable for analog hardware implementation. However, the sparsely interconnected structure also gives rise to a decrease in the capability of SINNs for associative memories. Although this problem can be solved by increasing the number of interconnections, the hardware cost goes up rapidly. Therefore, we propose associative memories consisting of multilayer perceptrons (MLPs) with 3-valued weights and SINNs. It is expected that such MLPs can be realized at a lower cost than increasing interconnections in SINNs and can give each neuron in SINNs the global information of an input pattern to improve the storage capacity. Finally, it is confirmed by simulations that our proposed associative memories have good performance.

This paper proposes a maneuvering target tracking algorithm using multiple model filters. This filtering algorithm is discussed in terms of tracking performance, tracking success rate and tracking accuracies for short sampling interval as compared with other conventional methodology. Through several simulations, validity of this algorithm has been confirmed.

A fuzzy-like phenomenon is observed in a chaotic neural network operating as dynamic autoassociative memory. When an external stimulation with properties shared by two stored patterns is applied to the chaotic neural network, the output of the network transits between the two patterns. The ratio of the network visiting two stored patterns is dependent on the ratio of the Hamming distances between the external stimulation and the two stored patterns. This phenomenon is similar to the human decision-making process, which can be described by fuzzy set theory. Here, we analyze the fuzzy-like phenomenon from the viewpoint of the fuzzy set theory.

Spatial dynamic pattern formations or trails by organisms attract us, which remind us chaos and fractal. They seem to show the emergence of co-operation, job separation, or division of territories when genetic programming controls the reproduction, mutation, crossing over of the organisms. Recent research in social insect behavior suggests that swarm intelligence comes from pheromone or chemical trails, and models based on self-organization can help explain how colony-level behavior emerges out of interactions among individual insects. We try to explain the co-operative behaviors of social insect by means of density of organisms and their interaction with environment in simple simulations. We also study that MDL-based fitness evaluation is effective for improvement of generalization of genetic programming. At last, interspecific and intraspecific mathematical models are examined to expand our research into interspecific evolution.

The implementation of conventional Multi-Code Code Division Multiple Access (MC-CDMA) system needs many orthogonal codes (OCs) compared to traditional Direct Sequence-CDMA (DS-CDMA) systems. To reduce the number of OCs in MC-CDMA for multi-media services, we propose a new scheme in which a sub-orthogonal code (SOC) technique is adopted. To clarify the validity of our proposed system, the computational simulations have performed.

The packaging hierarchy is not fixed structure. It can be changed depending on the packaging technology itself, and the number of hierarchy levels tends to decrease. In LSI-package technology including package-to-board interconnections, there were two evolutionary changes. The first evolution was from PTH to SMT, and the second evolution was from "Peripheral connections" to "Area-array connections. " These evolutions have been caused by ICs integration and application products requirements. Now, the third evolution appears to be in progress, which is from SCP to MCP or SIP. Although SoC has many remarkable features, it has been not applied for many systems contrary to expectations, and its limitations or issues have become clear. SIP is the answer for above SoC's issues. MCP can be considered to be primitive SIP. The purpose of MCP is making up the technology gap between SMT and SoC to address the issues. The targets of SIP are mainly the next two items. (1) Overcoming the interconnection crisis of SoC. (2) Opening new application fields in electronics. In order to achieve those targets, several consortiums in the world are doing research and developing core technologies.

The concept of stochastic association has originally been proposed in relation to single-electron devices having stochastic behavior due to quantum effects. Stochastic association is one of the promising concepts for future VLSI systems that exceed the conventional digital systems based on deterministic operation. This paper proposes a CMOS stochastic associative processor using PWM (pulse-width modulation) chaotic signals. The processor stochastically extracts one of the stored binary patterns depending on the order of similarity to the input. We confirms stochastic associative processing operation by experiments for digit pattern association using the CMOS test chip.

Partially depleted SOI technology with body-tied hybrid trench isolation was developed in order to counteract floating body effects which offers negative impact on the drive current of transistors and the stability of circuit operation while maintaining SOI's specific merits such as high speed operation and low power consumption. The feasibility of this technology and its superior soft error effects were demonstrated by a fully functional 4M-bit SRAM. Its radio frequency characteristics were also evaluated and it was verified that high-performance transistors and passive elements can be realized by the combination of the SOI structure and a high-resistivity substrate. Moreover, its application to a 2.5 GHz digital IC for optical communication was also demonstrated. Thus it was proven that the body-tied SOI devices with the hybrid trench isolation is suitable to realize intelligent and reliable high-speed system-on-a chip integrating various IP's.

The IEEE 1394 is a standard for the high performance serial bus interface. This standard has the isochronous transfer mode that is suitable for real-time applications and the asynchronous transfer mode for delay-insensitive applications. It can be used to construct a small-size local area network. We propose a queueing model for a network with this standard under some assumptions, and calculate the average waiting time of an asynchronous packet in the buffer in the steady state. We give some numerical results, along with validation by simulation, in order to evaluate its performance.