This letter presents a synchronizer and its handshake interface for bridging clock domains in SoC. The proposed scheme uses a double two-flop synchronizer operated at different clock edges respectively, based on a two-phase handshake protocol. Performance analysis shows that the proposed design reduces latency up to a clock cycle, while retaining its safety to a tolerable level.

In this paper, we propose a hardware architecture of real-time JPEG encoder for 1.4 mega pixels CMOS image sensor SoC which can be applied to mobile communication devices. The proposed architecture has an efficient interface scheme with CMOS image sensor and other peripherals for real-time encoding. The JPEG encoder supports the base-line JPEG mode, and processes motion images of which resolution is up to 1280960 (CCIR601 YCrCb 4:2:2,15 fps) by real-time processing. The JPEG encoder supports 8 types of resolution, and can serve the 4 levels of image quality through quantization matrix. The proposed JPEG encoder can transfer encoded motion pictures and raw image data from CMOS image sensor to external device through USB 2.0 and a compressed still image is stored at external pseudo SRAM through SRAM interface. And proposed core can communicate parameters of encoding type with other host by I2C. The proposed architecture was implemented with VHDL and verified for the functions with Synopsys and Modelsim. The encoder proposed in this paper was fabricated in process of 0.18 µ of Hynix semiconductor Inc.

The aim of this paper is to propose a modeling of corporate knowledge in cyberworlds. An enterprise is considered in the framework of multiagent methodology as a distributed computational system. The Agent-Oriented Abstraction paradigm was proposed earlier to describe in a fully generic way agents and societies of agents. In this paper, we are investigating the application of this paradigm to the abstract modeling of corporate knowledge, extending the scope of traditional knowledge management approaches. We show that such an abstraction mechanism leads to very practical applications for cyberworlds whether on the web or on any other medium. Our approach covers the broader possible scope of corporate knowledge, emphasizing the distributivity and autonomy of agents within cyber systems. This approach can be further used to better simulate and support knowledge management processes.

Cyberworlds are being formed in cyberspaces as computational spaces. Now cyberspaces are rapidly expanding on the Web either intentionally or spontaneously, with or without design. Widespread and intensive local activities are melting each other on the web globally to create cyberworlds. The major key players of cyberworlds include e-finance that trades a GDP-equivalent a day and e-manufacturing that is transforming industrial production into Web shopping of product components and assembly factories. Lacking proper theory and design, cyberworlds have continued to grow chaotic and are now out of human understanding and control. This research first presents a generic theoretical framework and design based on algebraic topology, and also provides an axiomatic approach to theorize the potentials of cyberworlds.

A GPS radio design for a complete single chip GPS receiver using 0.18-µm CMOS is presented. The complete single chip GPS receiver satisfies several key requirements for mobile applications, such as compactness, low power, and high sensitivity. The radio part, including the RF front end, the RF/IF PLLs, and IF functions, occupies 2.0 2.3 mm in a total chip area of 6.3 6.3 mm. It is fabricated using 0.18-µm CMOS technology utilizing MIM capacitors. The radio part operates within a 1.6 to 2.0 V supply voltage range and consumes 27 mW at 1.8 V. The whole GPS SoC consumes 57 mW for a fully functional chip and provides a high sensitivity of -152 dBm. The radio design features countermeasures against substrate coupling noise from the digital part.

To realize a high-density on-chip memory, the authors have proposed a novel logic-process-compatible memory cell. This cell consists of two logic transistors, and placing a planar MIM (metal insulator metal) capacitor on a copper wire above the transistors produces a memory area of 26 F2, which is approximately 60% smaller than a 6T SRAM cell. A suitable cell-bias design and a dual precharge scheme solve the coupling problem inherent in the cell and allow standard logic transistors to be used. This cell--applying the proposed schemes--can handle 10-ns cycle time at a bit-line voltage of 0.7 V. The random cycle is about three times faster than that of a conventional VBL precharge scheme. These results indicate that the umbrella cell is a strong candidate for providing a high-density memory for SOC applications.

This paper describes the access-timing control for an embedded SRAM core which operates in low and wide supply voltage (Vdd = 0.3-1.5 V). In the conventional SRAMs, a wiring-replica with replica-memory-cell (RMC) to trace the delay of memory core is used for this purpose. Introducing a wiring-replica control provides the better tracing capability in the wide range of Vdd above 0.5 V than those of using the control with logic-gate-delay. However, as Vdd is reduced below 0.5 V and gets close to the threshold voltage (Vth) of transistors, the access-timing fluctuation resulting from the variation in memory-cell-transistor-drain current (Id) is intolerably increased. As a result, the conventional control is no longer effective in such a low-voltage operation because the RMC can not replicate the variation in transistor-drain current (Id) and Vth of the memory-cells (MCs). Thus, to trace the access-timing fluctuation caused by the variation in Id and Vth is the prerequisite for the SRAM control in the range of Vdd = 0.3-1.5 V. To solve this issue, we have proposed new access-control scheme as follows; 1) a write-replica circuit with an asymmetrical memory cell (WRAM) making it possible to replicate the variation in Id and Vth for the write-access timing control, and 2) a source-level-adjusted direct-sense-amplifier (SLAD) to accelerate the read-access-timing even in low Vdd. These circuit techniques were implemented in a 32-Kbit SRAM in four-metal 130-nm CMOS process technology, and have been verified a low-voltage operation of 0.3 V which has not ever reported with 6.8 MHz. Moreover it operated in wide-voltage up to 1.5 V with 960 MHz. The required 27 MHz operation for mobile applications has been demonstrated at 0.4 V which is 6-times faster than the previous reports. The WRAM scheme enabled the write operation even at 0.3 V. And the access time which can be restricted by the slow tail bits of MCs has been accelerated by 73% to 140 nsec at 0.3 V by using SLAD scheme.

In this paper, we consider a data mining problem for semi-structured data. Modeling semi-structured data as labeled ordered trees, we present an efficient algorithm for discovering frequent substructures from a large collection of semi-structured data. By extending the enumeration technique developed by Bayardo (SIGMOD'98) for discovering long itemsets, our algorithm scales almost linearly in the total size of maximal tree patterns contained in an input collection depending mildly on the size of the longest pattern. We also developed several pruning techniques that significantly speed-up the search. Experiments on Web data show that our algorithm runs efficiently on real-life datasets combined with proposed pruning techniques in the wide range of parameters.

In this paper, a test architecture optimization for system-on-a-chip under floorplanning constraints is proposed. The models of previous test architecture optimizations were too ideal to be applied to industrial SOCs. To make matters worse, they couldn't treat topological locality of cores, that is, floorplanning constraints. The optimization proposed in this paper can avoid long wires for TAMs in consideration of floorplanning constraints and finish optimizing test architectures within reasonable computation time.

In this paper, we present a hierarchical multi-chip architecture which employs fully digital and word-parallel associative memories based on Hamming distance. High capacity scalability is critically important for associative memories since the required database capacity depends on the various applications. A multi-chip structure is most efficient for the capacity scalability as well as the standard memories, however, it is difficult for the conventional nearest-match associative memories. The present digital implementation is capable of detecting all the template data in order of the exact Hamming distance. Therefore, a hierarchical multi-chip structure is simply realized by using extra register buffers and an inter-chip pipelined priority decision circuit hierarchically embedded in multiple chips. It achieves fully chip- and word-parallel Hamming distance search with no throughput decrease, additional clock latency of O(log P), and inter-chip wires of O(P) in a P-chip structure. The feasibility of the architecture and circuit implementation has been demonstrated by post-layout simulations. The performance has been also estimated based on measurement results of a single-chip implementation.

The use of coplanar waveguide (CPW)-fed ultra-wideband antennas in applications of multi-system integration has been demonstrated in this paper. Spiral slot antennas and feeding structures were fabricated on the same plane of the substrate so that the circuit process and the position alignment could be simplified. A CPW-fed spiral slot antenna possessing the ultra-wideband characteristic is also suitable for integration with a monolithic microwave integrated circuit (MMIC) module. Variations of the measured initial resonant frequency due to substrate thickness, number of turns and slot width are discussed in this paper. In addition, two topologies of the CPW-fed spiral slot antenna were devised and measured to demonstrate the capability of lowering the initial resonant frequency by adding a circularly microstrip stub at the end of the feedline and placing a short pin to terminate the spiral slot and feedline. According to the measured results, the CPW-fed spiral slot antenna covered most of the commercial wireless communication and satellite communication systems in radio frequency (RF), microwave and millimeter-wave applications.

Circuit techniques to realize stable recall operation and virtually unlimited read/program cycle operations in ferroelectric memory based nonvolatile (NV) SRAM composed of six-transistor and four-ferroelectric capacitor cells have been developed. Unlimited program cycle operation independent of ferroelectric material characteristics is realized by proper control of plate lines. Reliability evaluation results show that the developed memory cell has sufficient operation margin after stresses of temperature, fatigue, DC bias. Application of NV-SRAM to programmable logic devices has been discussed with a prototype of dynamically programmable gate arrays.

The hardware implementation of a neural network model using stochastic logic has been able to integrate numerous neuron units on a chip. However, the limitation of applications occurred since the stochastic neurosystem could execute only discrete-time dynamics. We have contrived a neuron model with continuous-time dynamics by using stochastic calculations. In this paper, we propose the circuit design of a new neuron circuit, and show the fabricated neurochip comprising 64 neurons with experimental results. Furthermore, a new asynchronous updating method and a new activation function circuit are proposed. These improvements enhance the performance of the neurochip greatly.

This paper deals with the chaoticity and fractality analysis of price time series for artificial stock market generated by the multi-agent systems based on the co-evolutionary Genetic Programming (GP). By simulation studies, if the system parameters and the system construction are appropriately chosen, the system shows very monotonic behaviors or sometime chaotic time series. Therefore, it is necessary to show the relationship between the realizability (reproducibility) of the system and the system parameters. This paper describe the relation between the chaoticity of an artificial stock price and system parameters. We also show the condition for the fractality of a stock price. Although the Chaos and the Fractal are the signal which can be obtained from the system which is generally different, we show that those can be obtained from a single system. Cognitive behaviors of agents are modeled by using the GP to introduce social learning as well as individual learning. Assuming five types of agents, in which rational agents prefer forecast models (equations) or production rules to support their decision making, and irrational agents select decisions at random like a speculator. Rational agents usually use their own knowledge base, but some of them utilize their public (common) knowledge base to improve trading decisions. By assuming that agents with random behavior are excluded and each agent uses the forecast model or production rule with most highest fitness, those assumptions are derived a kind of chaoticity from stock price. It is also seen that the stock price becomes fractal time series if we utilize original framework for the multi-agent system and relax the restriction of systems for chaoticity.

This study was conducted to examine the relationship between technostress - techno-centered tendency- and antisocial behavior on computers. Questionnaire data of computer operators were analyzed by multivariate-analysis. The results of the analysis indicated that high techno-centered tendency has a strong relationship with antisocial behavior on computers. Among the component factors of techno-centered tendency, absorption in operating computers was proven to have the strongest association with antisocial behavior on computers.

In this paper, we describe how to exploit a machine-readable dictionary (MRD) and domain-specific text corpus in supporting the construction of domain ontologies that specify taxonomic and non-taxonomic relationships among given domain concepts. In building taxonomic relationships (hierarchical structure) of domain concepts, some hierarchical structure can be extracted from a MRD with marked subtrees that may be modified by a domain expert, using matching result analysis and trimmed result analysis. In building non-taxonomic relationships (specification templates) of domain concepts, we construct concept specification templates that come from pairs of concepts extracted from text corpus, using WordSpace and an association rule algorithm. A domain expert modifies taxonomic and non-taxonomic relationships later. Through case studies with "the Contracts for the International Sales of Goods (CISG)" and "XML Common Business Library (xCBL)", we make sure that our system can work to support the process of constructing domain ontologies with a MRD and text corpus.

In this study, a modeling method of the intermittency chaos using the Markov chain is proposed. The performances of the intermittency chaos and the Markov chain model are investigated when they are injected to the Hopfield Neural Network for a quadratic assignment problem or an associative memory. Computer simulated results show that the proposed modeling is good enough to gain similar performance of the intermittency chaos.

A power-aware interconnect circuit design--called µI/O architecture--has been developed to provide low-cost system solutions for System-on-Chip (SoC) and System-in-Package (SiP) technologies. The µI/O architecture provides a common interface throughout the module enabling hierarchical I/O design for SoC and SiP. The hierarchical I/O design allows the driver size to be optimized without increasing design complexity. Moreover, it includes a signal-level converter for integrating wide-voltage-range circuit blocks and a signal wall function for turning off each block independently--without invalid signal transmission--by using an internal power switch.

Mining generalized frequent patterns of generalized association rules is an important process in knowledge discovery system. In this paper, we propose a new approach for efficiently mining all frequent patterns using a novel set enumeration algorithm with two types of constraints on two generalized itemset relationships, called subset-superset and ancestor-descendant constraints. We also show a method to mine a smaller set of generalized closed frequent itemsets instead of mining a large set of conventional generalized frequent itemsets. To this end, we develop two algorithms called SET and cSET for mining generalized frequent itemsets and generalized closed frequent itemsets, respectively. By a number of experiments, the proposed algorithms outperform the previous well-known algorithms in both computational time and memory utilization. Furthermore, the experiments with real datasets indicate that mining generalized closed frequent itemsets gains more merit on computational costs since the number of generalized closed frequent itemsets is much more smaller than the number of generalized frequent itemsets.

As power consumption becoming a critical concern for System-On-a-Chip (SOC) design, accurate and efficient power analysis and estimation during the design phase at all levels of abstraction are becoming increasingly pressing in order to achieve low power without a costly redesign process. This paper surveys analysis and estimation techniques of dynamic power and leakage power for SOC design covering multiple design levels, which have been recently proposed, aiming to present a cohesive view of the power estimation techniques at all design levels of abstraction.