Let TBP be the server busy period of an M/G/1 queueing system characterized by arrival intensity λ and service time c.d.f. A(τ). In this paper, we investigate the regularity structure of the Laplace transform σBP(s)=E[] on the complex s-plane. It is shown, under certain broad conditions, that finite singular points of σBP(s) are all branch points. Furthermore the branch point s0 having the greatest real part is always purely negative and is of multiplicity two. The basic branch point s0 and the associated complex structure provide a basis for an asymptotic representation of various descriptive distributions of interest. For a natural relaxation time |s0|-1 of the M/G/1 system, some useful bounds are obtained and the asymptotic behavior as traffic intensity approaches one is also discussed. Detailed results of engineering value are provided for two important classes of service time distributions, the completely monotone class and the Erlang class.

Rate based control is a promising way to achieve an efficient packet transmission especially in high speed packet switching networks where round trip delay is much larger than packet transmission time. Although inappropriate tuning for the parameters, increasing and decreasing factors, of the rate control function causes the performance degradation, most of the previous works so far have not studied the effect of the parameters on the performance. In this paper, we investigate the effect of the rate control parameters on the throughput under the condition that the packet loss probability is kept below a specific value, say 10-6. For this purpose, we build a queueing model and carry out a transient analysis to examine the dynamic behavior of the queue length at an intermediate node in a high speed network suffering from large propagation delay. Numerical examples exploit the optimal value of the parameters when one or two source-destination pairs transmit packets. We also discuss the effect of the propagation delay on the performance. Our model can be applicable to investigate the performance of various kinds of rate-based congestion control when the relation between the congestion measure and the rate control mechanism is given explicitly.

There have been few studies on formal approaches to the specification and realization of asynchronous sequential circuits. For synchronous sequential circuits, an algebraic method is proposed as one of such approaches, but it cannot be applied to asynchronous ones directly. This paper describes an algebraic method of specifying the abstract behavior of asynchronous sequential circuits. We select an daisy chain arbiter as an example of them. In the arbiter, state transitions are caused by input changes, and all the modules do not always make state transitions simultaneously. These are main obstacles to specify it in the same way as sychronous sequential circuits. In order to remove them, we modify the meaning of input in specifications and introduce pseudo state transitions so that we can regard all the modules as if they make state transitions simultaneously. This method can be applied to most of the other asynchronous sequential circuits.

Rate-based congestion/flow control is a promising way to achieve high throughput in high speed packet-switching networks. We consider a rate-based congestion control to aim at obtaining high throughput and fair sharing of the communication resources. In the scheme, each intermediate node informs its congestion status to the source node. Two kinds of control packets are used for this mechanism. One (a choke packet) is to throttle the rate and another (a loosen packet) is to allow increase of the rate. The source node initiates transmission with a low rate and increases the rate slowly to avoid a rapid increase of the packet queueing at an intermediate node. When the source node receives a choke packet, it decreases the rate rapidly to relieve congestion as soon as possible. The source node upon receipt a loosen packet increases the rate slowly again. We develop a queueing model to investigate the parameter settings to provide a good performance via simulation. The increasing and decreasing parameters of the rate control function are first investigated in various load conditions. We next examine the effect of the queue-length threshold value for the indication of congestion at the intermediate node. The numerical results indicate that the threshold value should be small to obtain a good performance. We finally introduce a technique which accurately recognizes congestion and inhibits an acceptable queueing of the packets at intermediate nodes.

Existing solid models often contain redundant primitives and null blocks, which both slows down the rendering process and makes the process complex. There has been recent progress toward solving this problem, but existing modeling schemes cannot support eliminating all the redundancies, especially the null blocks, from the solid models. This paper proposed a technique that can eliminate redundancies. By dividing a primitive into some surface dispersed points, a new primitive representation is obtained. The sample segments of the primitive or the object are used to locate composition position to prevent the null primitives from being generated. By drawing out the geometric shape points set corresponding to a common acting area, the volume boundary of a primitive or an object is evaluated by only the Boolean set operations. The null blocks can be picked out in terms of the volume boundary. The resulting solid model generated in this way has no redundancies and is suitable for fast rendering of the image.

This paper describes a new timing calibration method for IC testers that uses a Timing Calibration Device (TCD). The TCD is a chip fabricated using the same process the device to be tested. Since the TCD has the same assignment pins as the LSI memory device under test (called the "MUT"), it enables an IC tester to evaluate the timing accuracy at the input/output terminal of MUT. The block-select-access time of a 1 K ECL RAM, which is less than 3.0 nanoseconds, has been accurately measured using this device. A timing-calibration subsystem is proposed for IC testers as an application of the TCD. Such a device would achieve precise measurement of high-speed LSI memory devices.

An integrated platform INTEGRAL has been developed for developing large complex communication software systems. At the heart of INTEGRAL, a pair of graphical and textual specification languages, DISCOL (DIStributed Communication-Oriented Language), has been developed based on Petri nets. Around DISCOL, a wide variety of design and analysis tools have been integrated in coherent manner so that a seamless support from design to verification and testing are made available along with software life-cycle. The platform has been applied to the development of a PBX simulator named UICPBX. In the development, some real communication services have been fully specified with DISCOL. Such experiences have revealed the effectiveness of the proposed techniques.

This paper describes a new 0.5-µm MOS current mode Logic (MCML) circuit that operates at 1.2 V, while maintaining high-speed performance, comparable with that of bipolar current mode circuits. An MCML circuit consists of differentially operating MOS transistors and a constant current source. Its performance at low voltage is compared with that of a CMOS circuit and bipolar current mode circuits. At 1.2 V, the MCML circuit has 90% the delay time of a CMOS circuit at 3.3 V. Delay times of CML and ECL circuits are 80% and 67% of that of the MCML circuit, respectively. Power of a 0.5-µm 500-MHz MCML circuit at 1.2 V, however, is 29%, 67% and 46%, of that of CMOS at 3.3 V, CML at 1.8 V and ECL at 2.6 V, respectively. Power-delay products of 500-MHz CMOS, CML and ECL circuits (normalized by the MCML circuit power-delay product) are 3.8, 1.2 and 1.5, respectively. MCML circuits can be used to construct any logic circuits. High-speed compact circuits are feasible, because MCML circuits output complementary signals. The delay time of an MCML full adder is only 200 ps. This is three times faster than that of a 3.3-V CMOS full adder. An MCML circuit has good characteristics and is widely applicable to logic circuits, so it is a useful circuit for producing sub-GHz processors.

This paper describes a high-performance, low-power, mixed-signal Digital Signal Processor (DSP) and its application to a single-chip Vector Sum Excited Linear Prediction (VSELP) speech codec. The DSP consists of a 25MIPS, 24bit floating point core-DSP; 13bit oversampling ADC/DAC; 6 KW data ROM; and 3.5 KW data RAM. The total transistor counts of the DSP is 1.3 million and its chip size is 11.0 mm15.8 mm. Unique design techniques are used to reduce the power dissipation, such as the programmable machine cycle time control and the clock supply control scheme in the core-DSP, the address detection for on-chip data ROM/RAM, and the shared-hardware design for digital filters of ADC and DAC. As an application of the DSP, the VSELP speech codec, which is the standard speech codec for the North American and Japanese digital cellular telephone system, has been implemented in a single-chip. Owing ti the salient architecture design and the program optimization techniques, sufficient quality was obtained in the codec at performance of 16.4 MIPS with low-power dissipation of 490 mW.

An improved array architecture to realize fast access, low power dissipation, and wide operating margin, for the 16 Mbit DRAM is proposed. A high speed access is obtained by the fully embedded sense drive scheme for the RAS access time (tRAC), and the special page mode with the hierarchical I/O data bus lines and multi-purpose-register (MPR) for the column address access time (tCAA). A low power dissipation and wide operating margin are obtained by the improved twisted-bit-line (TBL) architecture with double dummy canceling. The 16 Mb DRAM using these architectures has 38 ns tRAC, 14 ns tCAA and 75 mA power dissipation at the typical condition.

This paper describes a computer-aided service creation environment (CSCE) for the intelligent network which supports easier graphical specification description for service designers of various skill levels, and service logic program (SLP) generation. The CSCE design concept consists of stepwise service specification description and SLP generation, message sequence chart description language (LSDL: Layered Service Specification Description Language), computer-aided sophisticated interface (IEDs: Intelligent Editors), automatic specification verification and rapid service prototyping. Service specification is described by three steps and in LSDL or SDL, and SLPs are generated through three converters referring to two knowledge databases. Three tests are conducted on the specifications described. The effectiveness of the CSCE is demonstrated by the results that the amount of SLP descriptions for five new practical services using the CSCE is reduced to less than about 20% in LSDL description, compared to C language description.

In LOTOS, requirements for a distributed system are described as a service definition. On the protocol level, each node (protocol entity) must exchange some data values and synchronization messages to provide a service described in a service definition. The tuple of the specifications of all nodes in the system which provide the service is called as a protocol specification. In order to develop the communication programs satisfying a given service definition, it is very important to develop the correct protocol specification. For this purpose, the simulation of protocol specifications is useful and it is desirable that the designer can observe how a protocol specification is executed in parallel and how synchronization messages are exchanged among the nodes. Therefore, we have developed a new tool named PROSPEX. For a given pair of a service definition and a protocol specification, it executes the protocol specification in parallel and shows its execution process graphically on X Window System. If the protocol specification executes an event sequence which does not satisfy the service definition, then PROSPEX informs it to the designer. In this paper, the design and usefulness of PROSPEX are described.

This paper presents unique specification environments for LOTOS, which is one of FDTs (Formal Description Techniques) developed in ISO. We first discuss the large gap in terms of syntax and semantics between informal specifications at the early stage of specification design and formal specifications based on FDT such as LOTOS. This large gap has been bridged by human intelligent works thus far. In order to bridge the large gap, we have designed user-friendly specification environments for FDTs. The outlines of SEGL (Specification Environment for G-LOTOS), CBP (Concept-Based Programming environment) and MBP (Model-Based Programming environment) are described. The effectiveness of software development under such an environment is demonstrated using application examples from OSI and non-OSI protocols.

This paper describes a verification scheme for service specifications and presents verification results for prototype system. Verified specifications are described by information sequence charts, which describe the communicating states between users and the messages between a user and a network. The verification scheme consists of two steps: macro sequence verification, which treats rough transitions of states, and transition procedure verification, which treats procedure of all messages. A prototype verification system demonstrates that this scheme can detect about 90% of errors in a specification within 4.4 seconds.

This paper describes the performance evaluation of the Translation Look-aside Buffer (TLB) for highly integrated microprocessors, especially concerning the TLB in the SPARC Reference MMU specification. The analysis covers configurations, the number of entries, and replacement algorithms for the instruction TLB and the data TLB, which are assumed to be practically integrated on one die. We also present performance improvement using a Page Table Cache (PTC). We evaluate some types of TLB configurations with software simulation and excute the Systems Performance Evaluation Cooperative (SPEC) programs.

Net-Oriented Analysis and Design (NOAD) is defined as three items: (1) Various nets are utilized as an effective modeling method. (2) Inter-relationships among verious nets are determined. (3) Verification or analysis methods for nets are provided and they are implemented based on the mathematical theory, that is Net theory. Very few methods have been presented to satisfy these three items. For example, the Real-Time SA method covers item (1) only. The Object-Oriented Analysis and Design method (OOA/OOD) covers items (1) and (2). NOAD can be regarded as an extension to OOA/OOD. This paper discusses how effectively various nets have been used in actual software development support metnods and tools and evaluates such several methods and tools from the NOAD viewpoint.

The purpose of this paper is to propose a technique to simplify the communications software descriptions written in a procedural language in order to enhance their comprehensibility. Although such a technique was not much studied and discussed in the past, this technique is important to realize high productivity and high quality of the communications software by reducing the complexity of the software description. This paper firstly systematically presents various simplification methods with their principles for the descriptions of the communications software from the viewpoints of their layout, syntactical structures etc. Then, it describes a simplification support system based on these principles for the software specifications written in SDL. Lastly, this paper demonstrates the usefulness and effectiveness of the proposed simplification technique by analyzing the evaluation results of the simplification system.

In power line SS communication system, since available frequency range is limited from 10 kHz to 450 kHz by the law, we can't transmit any components of lower and higher frequency regions. In this paper, we propose a method for improving bit error rate by using the PN sequence coded by the new channel code, FM-V5 code, instead of PE code to have correlation property in the coded PN sequence. Correlation property in the coded PN sequence makes us effectively use Viterbi decoding technique on the receiving side. To enhance correlation property more, we also examine to apply additionally partial response (PR) system, so called PRML system, on the receiving side. The results of computer simulation show the improvement of about 4.5 dB on SNR at bit error rate 10-5 by using FM-V5 code without PR system compared with PE code. In the case of FM-V5 code with PR(1, -1) system, we get the further improvement of about 11 dB on SNR at the same bit error rate 10-5 compared with PE code. As a result, our method can attain SNR improvement about 20 dB compared with conventional simple PN sequence, that is the conventional Direct Sequence/Spread Spectrum (DS/SS), method.

In this paper, a new M-estimation technique for the linear prediction analysis of speech is proposed. Since in the conventional linear prediction (CLP) method the obtained estimates are very much affected by the large amplitude residual parts, in the proposed method we use a loss function which assigns large weighting factor for small amplitude residuals and small weighting factor for large amplitude residuals which is for instance caused by the pitch excitations. The loss function is based on the assumption that the residual signal has an independent and identical t-distribution t(α) with α degrees of freedom. The efficiency of this new estimator depends on α. When α=, we get the CLP method. When the proposed method with small α is applied to the problems of estimating the formant frequencies and bandwidths of the synthetic speech by finding the roots of the prediction polynomial, we can achieve a more accurate and a smaller standard deviation (SD) estimate than that with large α. When the signal is very spiky, the proposed method can ahieve more efficient and accurate estimates than that with robust linear prediction (RBLP) method. The loss function is modified in the similar manner as the autocorrelation method. The solution is calculated by the Newton-Raphson iteration technique. The simulation results show that only few iterations are needed to reach a stationary point, the stationary point is always a local minimum and the obtained prediction filter is always minimum phase. Preliminary experiments on the human speech data indicate that the obtained results are insensitive to the placement of the analysis window and a higher spectral resolution than the CLP and RBLP method can be achieved.

A specification formalism for business application software is presented. Our approach is to investigate specification documents which are actually used in development projects of business applications in banking, insurance, and government systems. Since the specification documents are prepared mainly for users' review for the developing software, the representation of the documents is designed to be easy to understand for users, only in business terminology without losing a certain level of formality. Also, to avoid redundancy of the specification, there are some implicit assumptions in the specification. We have analyzed some commonality of these assumptions hidden in specification documents and are trying to construct a language by formalizing the underlying system model.