The extraction of verb synonyms is a key technology to build a verb dictionary as a language resource. This paper presents a co-clustering-based verb synonym extraction approach that increases the number of extracted meanings of polysemous verbs from a large text corpus. For verb synonym extraction with a clustering approach dealing with polysemous verbs can be one problem issue because each polysemous verb should be categorized into different clusters depending on each meaning; thus there is a high possibility of failing to extract some of the meanings of polysemous verbs. Our proposed approach can extract the different meanings of polysemous verbs by recursively eliminating the extracted clusters from the initial data set. The experimental results of verb synonym extraction show that the proposed approach increases the correct verb clusters by about 50% with a 0.9% increase in precision and a 1.5% increase in recall over the previous approach.

An improved nonlinear circuit model for a GaAs Gunn diode in an oscillator is proposed based on the physical mechanism of the diode. This model interprets the nonlinear harmonic character on the Gunn diode. Its equivalent nonlinear circuit of which can assist in the design of the Gunn oscillator and help in the analysis of the fundamental and harmonic characteristics of the GaAs Gunn diode. The simulation prediction and the experiment of the Gunn oscillator show the feasibility of the nonlinear circuit model for the GaAs Gunn oscillator.

A three-dimensional semiconductor package structure with inter-chip connections was developed for broadband data transfer and low latency electrical communication between a high-capacity memory and a logic device interconnected by a feedthrough interposer (FTI) featuring a 10 µm scale fine-wiring pattern and ultra-fine-pitch through vias. This technology features co-existence of the wide-band memory accessibility of a system-on-chip (SoC) and the capability of memory capacity increasing of a system-in-package (SiP) that is made possible by the individual fabrication of memory and logic on independent chips. This technology can improve performance due to memory band widening and a reduction in the power consumed in inter-chip communications. This paper describes the concept, structure, process, and experimental results of prototypes of this package, called SMAFTI (SMAart chip connection with FeedThrough Interposer). This paper also reports the results of the fundamental reliability test of this novel inter-chip connection structure and board-level interconnectivity tests.

MOS capacitors with Si-implanted thermal oxide and CVD deposited oxide of 30 nm thickness were fabricated for applications of non-volatile memory and electroluminescence devices. Current-voltage (I-V) and I-V hysteresis characteristics were measured, and the hysteresis window (HW) and the integrated charge of HW (ICHW) extracted from the hysteresis data were discussed. The HW characteristics of high Si dose samples showed the asymmetrical double-peaks curves with the hump in both tails. The ICHW almost converged after the 4th cycle and had the voltage sweep speed dependence. All +ICHW and -ICHW characteristics were closely related to the static (+I)-(+VG) and (-I)-(-VG) curves, respectively. For the high Si dose samples, the clear hump currents in the static I-VG characteristics contribute to lower the rising voltage and to steepen the ICHW increase, which correspond to the large stored charge in the oxide.

This paper proposes a micro-code based Programmable Memory BIST (PMBIST) architecture that can support various kinds of test algorithms. The proposed Non-linear PMBIST (NPMBIST) guarantees high flexibility and high fault coverage using not only March algorithms but also non-linear algorithms such as Walking and Galloping. This NPMBIST has an optimized hardware overhead, since algorithms can be implemented with the minimum bits by the optimized instructions. Finally, various and complex algorithms can be run thanks to its support of multi-loop.

A scan chain is one of the most important testing techniques, but it can be used as side-channel attacks against a cryptography LSI. We focus on scan-based attacks, in which scan chains are targeted for side-channel attacks. The conventional scan-based attacks only consider the scan chain composed of only the registers in a cryptography circuit. However, a cryptography LSI usually uses many circuits such as memories, micro processors and other circuits. This means that the conventional attacks cannot be applied to the practical scan chain composed of various types of registers. In this paper, a scan-based attack which enables to decipher the secret key in an AES cryptography LSI composed of an AES circuit and other circuits is proposed. By focusing on bit pattern of the specific register and monitoring its change, our scan-based attack eliminates the influence of registers included in other circuits than AES. Our attack does not depend on scan chain architecture, and it can decipher practical AES cryptography LSIs.

UHF band passive RFID systems are being steadily adopted by industries because of their capability of long range automatic identification with passive tags. For an application which demands a large number of readers located in a limited geographical area, referred to as dense reader mode, interference rejection among readers is important. The coding method, baseband or subcarrier coding, in the tag-to-reader communication link results in a significant influence on the interference rejection performance. This paper examines the frequency sharing of baseband and subcarrier coding UHF RFID systems from the perspective of their transmission delay using a media access control (MAC) simulator. The validity of the numerical simulation was verified by an experiment. It is revealed that, in a mixed operation of baseband and subcarrier systems, assigning as many channels as possible to baseband system unless they do not exploit the subcarrier channels is the general principle for efficient frequency sharing. This frequency sharing principle is effective both to baseband and subcarrier coding systems. Otherwise, mixed operation fundamentally increases the transmission delay in subcarrier coding systems.

Recent technology mappers for LUT based FPGAs employ cut enumeration. Although many cuts are often needed to find a good network, enumerating all the cuts with large size consumes a lot of run-time. Existing algorithms employ the bottom-up merging which calculates Cartesian products of the fanins' cuts for each node. The number of cuts is much smaller than the size of the Cartesian products in most cases. Thus, the existing algorithms are inefficient. Furthermore, the number of cuts exponentially increases with the size of cuts, that makes the run-time much longer. Several algorithms to enumerate not all the cuts but partial cuts have been presented, but they tend to disturb the quality of networks. This paper presents two algorithms to enumerate cuts; an exhaustive enumeration and a partial enumeration. Both of them are efficient because they do not employ the bottom-up merging. The partial enumeration reduces the number of enumerated cuts with a guarantee that a depth-minimum network can be constructed. The experimental results show that the exhaustive enumeration runs about 5 and 13 times faster than the existing bottom-up algorithm for K=8, 9 respectively, while keeping the same results. On the other hand, the partial enumeration runs about 9 and 29 times faster than the existing algorithm for K = 8, 9, respectively. The average area of networks derived by the sets of cuts enumerated by the partial enumeration is only 4% larger than that derived with using all the cuts, and the depth is the same.

Scalable video coding (SVC) was standardized as an extension of H.264/AVC by the JVT (Joint Video Team) in Nov. 2007. The biggest feature of SVC is multi-layered coding where two or more video sequences are compressed into a single bit-stream. This letter proposes a fast block mode decision algorithm in spatial enhancement layer of SVC. The proposed algorithm achieves early decision by limiting the number of candidate modes for block with certain characteristic called same motion vector block (SMVB). Our proposed method reduces the complexity, in terms of encoding time by up to 66.17%. Nevertheless, it shows negligible PSNR degradation by only up to 0.16 dB and increases the bit-rate by only up to 0.64%, respectively.

Indium-sulfide-oxide thin films have been successfully deposited on indium-tin-oxide-coated glass from an aqueous solution containing Na2S2O3 and In2(SO4)3 by electrochemical deposition using a periodic 2-step-pulse voltage. The films have been annealed in nitrogen atmosphere for an hour at different temperatures; namely, 100, 200, 300 and 400. Then, the as-deposited and annealed films were characterized structurally, morphologically and optically. X-ray photoelectron spectroscopy (XPS) study was performed in order to understand the chemical states of the oxygen involved in the film composition. The photosensitivity was observed by means of photoelectrochemical measurements, which confirmed that the as-deposited and annealed films showed n-type conduction. Moreover, a heterostructure solar cell that has indium sulfide as a buffer layer and tin sulfide as an absorber was fabricated and characterized.

Trapdoor commitment schemes are widely used for adding valuable properties to ordinary signatures or enhancing the security of weakly secure signatures. In this letter, we propose a trapdoor commitment scheme based on RSA function, and prove its security under the hardness of the integer factoring. Our scheme is very efficient in computing a commitment. Especially, it requires only three multiplications for evaluating a commitment when e=3 is used as a public exponent of RSA function. Moreover, our scheme has two useful properties, key exposure freeness and strong trapdoor opening, which are useful for designing secure chameleon signature schemes and converting a weakly secure signature to a strongly secure signature, respectively.

This paper addresses the problem of optimizing metalization patterns of back-end connections for the power-MOSFET based driver since the back-end connections tend to dominate the on-resistance Ron of the driver. We propose a heuristic algorithm to seek for better geometric shapes for the patterns targeting at minimizing Ron and at balancing the current distribution. In order to speed up the analysis, the equivalent resistance network of the driver is modified by inserting ideal switches to avoid repeatedly inverting the admittance matrix. With the behavioral model of the ideal switch, we can significantly accelerate the optimization. Simulation on three drivers from industrial TEG data demonstrates that our algorithm can reduce Ron effectively by shaping metals appropriately within a given routing area.

We propose a method of assigning polarity to causal information extracted from Japanese financial articles concerning business performance of companies. Our method assigns polarity (positive or negative) to causal information in accordance with business performance, e.g. "zidousya no uriage ga koutyou: (Sales of cars are good)" (The polarity positive is assigned in this example). We may use causal expressions assigned polarity by our method, e.g., to analyze content of articles concerning business performance circumstantially. First, our method classifies articles concerning business performance into positive articles and negative articles. Using them, our method assigns polarity (positive or negative) to causal information extracted from the set of articles concerning business performance. Although our method needs training dataset for classifying articles concerning business performance into positive and negative ones, our method does not need a training dataset for assigning polarity to causal information. Hence, even if causal information not appearing in the training dataset for classifying articles concerning business performance into positive and negative ones exist, our method is able to assign it polarity by using statistical information of this classified sets of articles. We evaluated our method and confirmed that it attained 74.4% precision and 50.4% recall of assigning polarity positive, and 76.8% precision and 61.5% recall of assigning polarity negative, respectively.

Recently, two-level cache, L1 cache and L2 cache, is commonly used in a processor. Particularly in an embedded system whereby a single application or a class of applications is repeatedly executed on a processor, its cache configuration can be customized such that an optimal one is achieved. An optimal two-level cache configuration can be obtained which minimizes overall memory access time or memory energy consumption by varying the three cache parameters: the number of sets, a line size, and an associativity, for L1 cache and L2 cache. In this paper, we first extend the L1 cache simulation algorithm so that we can explore two-level cache configuration. Second, we propose two-level cache design space exploration algorithms: CRCB-T1 and CRCB-T2, each of which is based on applying Cache Inclusion Property to two-level cache configuration. Each of the proposed algorithms realizes exact cache simulation but decreases the number of cache hit/miss judgments by a factor of several thousands. Experimental results show that, by using our approach, the number of cache hit/miss judgments required to optimize a cache configurations is reduced to 1/50-1/5500 compared to the exhaustive approach. As a result, our proposed approach totally runs an average of 1398.25 times faster compared to the exhaustive approach. Our proposed cache simulation approach achieves the world fastest two-level cache design space exploration.

Objective assessment of image and video quality should be based on a correct understanding of subjective assessment by human observers. Previous models have incorporated the mechanisms of early visual processing in image quality metrics, enabling us to evaluate the visibility of errors from the original images. However, to understand how human observers perceive image quality, one should also consider higher stages of visual processing where perception is established. In higher stages, the visual system presumably represents a visual scene as a collection of meaningful components such as objects and events. Our recent psychophysical studies suggest two principles related to this level of processing. First, the human visual system integrates shape and color signals along perceived motion trajectories in order to improve visibility of the shape and color of moving objects. Second, the human visual system estimates surface reflectance properties like glossiness using simple image statistics rather than by inverse computation of image formation optics. Although the underlying neural mechanisms are still under investigation, these computational principles are potentially useful for the development of effective image processing technologies and for quality assessment. Ideally, if a model can specify how a given image is transformed into high-level scene representations in the human brain, it would predict many aspects of subjective image quality, including fidelity and naturalness.

In this paper, we propose a hybrid M-ary Quadrature Amplitude Modulation (M-QAM) transmission scheme that jointly uses discrete-rate adaptation and selection combining for singular value decomposition (SVD)-based multiple-input multiple-output (MIMO) systems, and derive exact closed-form expressions of the performance of the proposed scheme in terms of the average spectral efficiency and the outage probability.

This paper presents a simple antenna system for land vehicle communication aimed at Engineering Test Satellite-VIII (ETS-VIII) applications. The developed antenna system which designed for mounting in a vehicle is compact, light weight and offers simple satellite-tracking operation. This system uses a microstrip patch array antenna, which includes onboard-power divider and switching circuit for antenna feeding control, due to its low profile. A Global Positioning System (GPS) receiver is constructed to provide accurate information on the vehicle's position and bearing during traveling. The personal computer (PC) interfaces as the control unit and data acquisition, which were specifically designed for this application, allow the switching circuit control as well as the retrieving of the received power levels. In this research, the antenna system was firstly examined in an anechoic chamber for S parameter, axial ratio, and radiation characteristics. Satisfactory characteristics were obtained. As for beam-tracking of antenna, it was examined in the anechoic chamber with the gain above 5 dBic and the axial ratio below 3 dB. Moreover, good received power levels for tracking the ETS-VIII satellite in outdoor measurement, were confirmed.

An extreamly large scale periodic array antenna is required for transmitting power from space solar power systems. Analysis of the huge-scale array antenna is important to estimate the radiation property of the array antenna, but a full-wave analysis requires too much computer memory and excessive CPU time. In order to overcome these difficulties, the impedance extension method is proposed as a method of approximate analysis for huge periodic array antennas. From the results of actual gain pattern obtained by the proposed method and its relative error, it is shown that edge effects of a huge-scale array antenna can be ignored in calculating the radiation property.

This paper describes an incremental parser based on an adjoining operation. By using the operation, we can avoid the problem of infinite local ambiguity. This paper further proposes a restricted version of the adjoining operation, which preserves lexical dependencies of partial parse trees. Our experimental results showed that the restriction enhances the accuracy of the incremental parsing.

The hidden terminal problem leads to frequent collisions and decreases the throughput of ad hoc networks dramatically. Low network spatial reuse also results in fewer parallel transmissions, which further leads to reduced network throughput. Eliminating the hidden terminals and improving the spatial reuse are two important approaches to improving network throughput. In this paper, spatial distribution of the hidden terminals is analyzed in consideration of accumulated interference and environmental noise. As the distribution of hidden terminals is affected by many factors such as transmitter-receiver distance, SINR requirement and nodes density, it is inefficient to use fixed busy tone transmission power. To eliminate the hidden terminals and improve network spatial reuse, an enhancement to DBTMA named EDBTMA is proposed. This is achieved by using an adaptive busy tone power control scheme. Receivers adjust the transmission power of busy tone according to received signal power and accumulated interference adaptively so that all hidden terminals (and only hidden terminals) are covered by the busy tone. Simulation results show that EDBTMA protocol can solve the hidden terminal problem and improve network spatial reuse better than DBTMA and achieves 65% additional network throughput compared to DBTMA.