A highly stable oven-controlled crystal oscillator (OCXO) with low phase-noise characteristics has been developed using a dual-mode SC-cut quartz crystal oscillator. The OCXO uses a conventional oven-control system for coarse compensation and a digital-correction system, which uses B-mode signal in an SC-cut resonator as a temperature sensor, for fine compensation. Combining these two forms of compensation greatly improves the stability of the C-mode frequency without requiring a double-oven system. The experimental results indicated that the frequency stability of the proposed OCXO, including the frequency-temperature hysteresis, is ten times better than that of a conventional, free-running OCXO. The results also indicated that the proposed OCXO has good frequency retraceability and low phase-noise characteristics.

In this paper, we propose a universal biquad filter that can realize all types of 2nd-order functions, such as Low-pass Filters (LPF), High-Pass Filters (HPF), Band-Pass Filters (BPF), Band-Elimination Filters (BEF), and All-Pass Filters (APF). Also, the filter types can be programmable digitally with built-in switches. The proposed circuit can be realized by using a CMOS technology that is suitable for a mixed digital-analog LSI. In addition, the circuit can operate in high frequencies with a low power supply voltage because it is based on a current-mode circuit. Finally, the proposed circuit is simulated by PSpice to confirm its characteristics.

A fully on-chip active guard band circuit is proposed. The proposed circuit is mainly composed of current mirrors and based on a DC bias technique. HSPICE simulations and experiment results confirm the validity of the proposed active guard band circuit.

A new dimension-reduced interference suppression scheme is proposed for DS-CDMA systems over multipath channels. The proposed receiver resolves the problems of interference and multipath effects without needing to estimate the channel and training sequences. The minimum mean squared error (MMSE) criterion is used to obtain an algorithm to cancel the interference of each path. The MMSE filter is composed of two stages based on multipath effects. The proposed receiver has low complexity without great degradation of performance compared with the full dimension MMSE receiver with known channel information. Simulation results show that the proposed receiver converges to the optimal value rapidly because of its reduced dimension.

The mobile computing system is a set of functions on a distributed environment organized to support mobile hosts. In this environment, mobile hosts should be able to move without any constraints and should remain connected to the network even while moving. Also, they should be able to get necessary information regardless of their current location and time. Distributed mutual exclusion methods for supporting distributed algorithms have hitherto been designed for networks only with static hosts. However, with the emergence of mobile computing environments, a new distributed mutual exclusion method needs to be developed for integrating mobile hosts with underlying distributed systems. In the sense, many issues that should be considered stem from three essential properties of mobile computing system such as wireless communication, portability, and mobility. Thus far, distributed mutual exclusion methods for mobile computing environments were designed based on a token ring structure, which has the drawback of requiring high costs in order to locate mobile hosts. In this paper, we propose not only a distributed mutual exclusion method that can reduce such costs by structuring the entire system as a tree-based logical structure but also recovery schemes that can be applied when a node failure occurs. Finally, we evaluate the operation costs for the mutual exclusion scheme and the recovery scheme.

Recently, Kasahara and Murakami proposed new product-sum type public-key cryptosystems with the Chinese remainder theorem, Methods B-II and B-IV. They also proposed a new technique of selectable encryption key, which is referred to as 'Home Page Method (HP Method).' In this paper, first, we describe Methods B-II and B-IV. Second, we propose an effective attack for Method B-II and discuss the security of Methods B-II and B-IV. Third, applying the HP Method to Methods B-II and B-IV, we propose new product-sum type PKC with selectable encryption key. Moreover, we discuss the security of the proposed cryptosystems.

Watermarking techniques are widely used to protect the secret document. In some valuable literatures, most of them concentrate on the binary data watermarking by using comparisons of an original image and a watermarked image to extract the watermark. In this paper, an efficient watermarking algorithm is presented with two-layer hidden for gray-level image watermarking. In the first layer, the key information is found based on the codebook concept. Then the secret key is further hidden to the watermarked image adopting the encryption consisting of spatial distribution in the second layer. The simulations demonstrate that the watermarking information is perceptually invisible in the watermarked image. Moreover, the gray-level watermark can be extracted by referring key parameters rather than the original image, and the extracting quality is very good.

This paper investigates the accepting powers of one-way alternating and deterministic multi-counter automata operating in realtime. We partially solve the open problem posed in [4], and show that for each k1, there is a language accepted by a realtime one-way deterministic (k+3)-counter automaton, but not accepted by any realtime one-way alternating k-counter automaton.

In this paper, we address the key enabling technologies for long-span WDM transmissions at 40 Gbit/s. Experimental results of 1.28 Tbit/s (32 40 Gbit/s) unrepeatered transmission over 240 km of conventional 80-µm2 NDSF will be reported. Bi-directional pumped distributed Raman amplification has allowed a record unrepeatered WDM transmission distance over this fibre type, without using effective-area-enlarged fibres or remotely pumped EDFAs.

In this paper, we consider optimal mirror allocation problems for the purpose of load balancing in network servers. We focus on constructing high-reliability networks and propose the optimal mirror allocation model such that the system reliability is maximized subject to costs and delays, in view of the trade-off between the reliability and cost. This optimization model is capable of dealing with various kinds of network topologies, although for simplicity, we assume the read-only situation. We formulate this optimization problem into a 0-1 integer programming model, and we use an approximate method for numerical analysis in order to analyze more large-scale systems. Our objective is to find the optimal mirror allocation by solving this model, and to show quantitatively the general characteristics of the load balancing and the improvement of the system reliability by the distributed mirror allocation.

In this paper, we propose an activity-based estimation scheme to determine the received signal power disparity, that enhances the BER performance of the SIC scheme in a DS/CDMA system considering a practical voice activity factor, and compare BER performance with those of other schemes with or without estimation. Numerical analysis results show that the SIC scheme with the proposed activity-based estimation improves the BER performance compared with that without considering voice activity, and it approaches to that of the ideal estimation as the total number of concurrent users increases. In addition, the higher becomes the maximum attainable SNR, the better becomes the BER performance of the proposed activity-based estimation scheme.

It has been shown that virtual output queuing (VOQ) and a sophisticated scheduling algorithm enable an input-queued switch to achieve 100% throughput for independent arrival process. Several of the scheduling algorithms that have been proposed can be classified as either iterative scheduling algorithms or symmetric crossbar arbitration algorithms. i-OCF (oldest-cell-first) and TSA (two step arbiter) are well-known examples of iterative scheduling algorithms and symmetric crossbar arbitration algorithms, respectively. However, there are drawbacks in using these algorithms. i-OCF takes long time to find completely a conflict-free match between input ports and output ports because it requires multiple iterations. If i-OCF cannot find a conflict-free match completely, the switch throughput falls. TSA has the possibility that it finds a conflict-free match faster than i-OCF because it does not need any iterations. However, TSA suffers from the starvation problem. In this paper, we propose a new scheduling algorithm. It uses two schedulers, which we call scheduler 1 and scheduler 2, in parallel. After cells were transmitted, the information that input port i granted the offer from output port j in scheduler 2 is mapped to scheduler 1 if and only if input port i has at least one cell destined for output port j. If the information is moved, input port i and output port j are matched in scheduler 1 at the beginning of the next time slot. Our proposed algorithm uses one scheduler based on TSA and the other scheduler based on i-OCF. Numerical results show that the proposed scheduling algorithm does not require multiple iterations to find a conflict-free match completely and suffer from the starvation problem for both uniform and bursty traffic.

The periodicity of a target scattering matrix is studied when the target is rotated about the sight line of a monostatic radar. Except for the periodicity and invariance of the scattering matrix diag(a,a), it is proved that only helixes have the quasi-invariance, and that only N-targets have the quasi-periodicity, demonstrating that a target with some angle rotation symmetry also has the scattering matrix form diag(a,a). From this result, we conclude that it is impossible to extract the shape characteristics of a complex target from its scattering matrix or its Kennaugh matrix.

A 1.6-Tb/s dense WDM signal was successfully transmitted over 480 km using the carrier-suppressed return-to-zero (CS-RZ) modulation format. The CS-RZ format was chosen because it exhibited better transmission performance over a wide fiber-input power window than the NRZ and RZ formats in a 40-Gb/s-based WDM transmission experiment with 100-GHz channel spacing, confirming its nonlinearity-insensitive nature in dense WDM systems. With the wide power window of CS-RZ, we achieved stable transmission of 4040-Gb/s WDM signals over a 480-km (680 km) standard SMF line with only the C-band, in which a spectral ripple remained during transmission. Distributed Raman amplification and forward error correction were not used, providing a margin for already installed transmission lines.

In this paper, we propose a method of unicast and broadcast packet sharing for the orthogonal frequency division multiplexing (OFDM) multi-base station (BS) indoor wireless communication system using an adaptive array antenna on mobile terminals. The adaptive array antenna placed on the mobile terminal allows quality improvement due to the diversity effect when the data transmitted from all BSs are the same, and provides capacity improvement by channel sharing when the data from each BS are different. In the proposed sharing method, unicast packets are transmitted independently from multiple BSs in order to increase the communication capacity, and broadcast packets are transmitted simultaneously with other BSs in order to enhance the communication quality without retransmission. Furthermore, by modifying the packet assignment procedure, we confirm that quality can be improved for unicast packets in a low traffic environment.

The effectiveness of Aeff enlarged positive dispersion fiber (EE-PDF) and hybrid amplification configuration with erbium-doped fiber amplifier (EDFA) and fiber Raman amplifier for reducing the fiber nonlinearity and improving the transmission performance in long distance 40 Gbit/s-based WDM transmission was investigated. We have confirmed that the use of EE-PDF in modified dispersion map for 40 Gbit/s transmission is quite effective to increase the transmissible distance and have successfully demonstrated 16 40 Gbit/s WDM transmission over 2000 km with proper dispersion management. We have also confirmed that the use of distributed Raman amplification is quite effective to extend the repeater spacing. By adding the optimum Raman amplification, almost the same transmission performance was obtained with a doubled repeater spacing in long distance 40 Gbit/s-based WDM transmission.

A new approach on designing a finite field multiplier architecture is proposed. The proposed architecture trades reduction in the number of clock cycles with resources. This architecture features high performance, simple structure, scalability and independence on the choice of the finite field, and can be used in high security cryptographic applications such as elliptic curve crypto-systems in large prime Galois Fields (GF(2m)).

A fast, low-power 16-bit adder, 32-word register file and 512-bit cache SRAM have been developed using 0.25-µm GaAs HEMT technology for future multi-GHz processors. The 16-bit adder, which uses a negative logic binary look-ahead carry structure based on NOR gates, operates at the maximum clock frequency of 1.67 GHz and consumes 134.4 mW at a supply voltage of 0.6 V. The active area is 1.6 mm2 and there are about 1,230 FETs. A new DC/DC level converter has been developed for use in high-speed, low-power storage circuits such as SRAMs and register files. The level converter can increase the DC voltage, which is supplied to an active-load circuit on request, or supply a minimal DC voltage to a load circuit in the stand-by mode. The power dissipation (P) of the 32-word register file with on-chip DC/DC level converters is 459 mW, a reduction to 25.2% of that of an equivalent conventional register file, while the operating frequency (fc) was 5.17 GHz that is 74.8% of fc for the conventional register file. P for the 512-bit cache SRAM with the new DC/DC level converters is 34.3 mW, 89.7% of the value for an equivalent conventional cache SRAM, with the read-access time of 455 psec, only 1.1% longer than that of the conventional cache SRAM.

With increased size and issue-width, instruction issue queue becomes one of the most energy consuming units in today's superscalar microprocessors. This paper presents a novel architectural technique to reduce energy dissipation of adaptive issue queue, whose functionality is dynamically adjusted at runtime to match the changing computational demands of instruction stream. In contrast to existing schemes, the technique exploits a new freedom in queue design, namely the voltage per access. Since loading capacitance operated in the adaptive queue varies in time, the clock cycle budget becomes inefficiently exploited. We propose to trade-off the unused cycle time with supply voltage, lowering the voltage level when the queue functionality is reduced and increasing it with the activation of resources in the queue. Experiments show that the approach can save up to 39% of the issue queue energy without large performance and area overhead.

The power supply voltage of LSI has been lowered due to system requirements for low power dissipation. An on-chip power-on reset pulse generator (POR-PG) is used to determine the initial state of the memory devices of the system LSI. The requirement for the POR-PG is strict for lower power supply voltage because noise margin is smaller relatively. This paper describes a POR-PG for low power voltage supply (Vdd) which overcomes these problems. Hardware measurement proves improved pulse height relative to various power-on profiles (slope, rise time etc.) and fluctuations of temperature and process. Further, the design provides robust noise immunity against voltage fluctuations on the power supply line. The circuit is implemented within a small area (115 µm 345 µm) in the input/output buffer area of a micro-processor and hard-disk controller integrated LSI with 0.25-µm four-layer-metal CMOS technology.