In this paper, we propose a method of unicast and broadcast packet sharing for the orthogonal frequency division multiplexing (OFDM) multi-base station (BS) indoor wireless communication system using an adaptive array antenna on mobile terminals. The adaptive array antenna placed on the mobile terminal allows quality improvement due to the diversity effect when the data transmitted from all BSs are the same, and provides capacity improvement by channel sharing when the data from each BS are different. In the proposed sharing method, unicast packets are transmitted independently from multiple BSs in order to increase the communication capacity, and broadcast packets are transmitted simultaneously with other BSs in order to enhance the communication quality without retransmission. Furthermore, by modifying the packet assignment procedure, we confirm that quality can be improved for unicast packets in a low traffic environment.

Methodologies for more efficient Raman amplification and a more suitable modulation format for 40 Gbit/s WDM unrepeatered transmission are investigated. Management of the fiber effective area is proposed to realize low noise distributed Raman amplification. An Aeff management technique in which low-Aeff fiber is located in a median section instead of the last section, was confirmed numerically and experimentally to improve the OSNR and Q-factor. Carrier-suppressed-return-to-zero (CS-RZ) modulation has the advantage of reducing fiber-nonlinearity effects and permitting denser multiplexing of the wavelengths. 40 Gbit/s 32-channel unrepeatered WDM transmission over 202 km was demonstrated employing the proposed methodologies.

It has been shown that virtual output queuing (VOQ) and a sophisticated scheduling algorithm enable an input-queued switch to achieve 100% throughput for independent arrival process. Several of the scheduling algorithms that have been proposed can be classified as either iterative scheduling algorithms or symmetric crossbar arbitration algorithms. i-OCF (oldest-cell-first) and TSA (two step arbiter) are well-known examples of iterative scheduling algorithms and symmetric crossbar arbitration algorithms, respectively. However, there are drawbacks in using these algorithms. i-OCF takes long time to find completely a conflict-free match between input ports and output ports because it requires multiple iterations. If i-OCF cannot find a conflict-free match completely, the switch throughput falls. TSA has the possibility that it finds a conflict-free match faster than i-OCF because it does not need any iterations. However, TSA suffers from the starvation problem. In this paper, we propose a new scheduling algorithm. It uses two schedulers, which we call scheduler 1 and scheduler 2, in parallel. After cells were transmitted, the information that input port i granted the offer from output port j in scheduler 2 is mapped to scheduler 1 if and only if input port i has at least one cell destined for output port j. If the information is moved, input port i and output port j are matched in scheduler 1 at the beginning of the next time slot. Our proposed algorithm uses one scheduler based on TSA and the other scheduler based on i-OCF. Numerical results show that the proposed scheduling algorithm does not require multiple iterations to find a conflict-free match completely and suffer from the starvation problem for both uniform and bursty traffic.

In this paper, we propose an activity-based estimation scheme to determine the received signal power disparity, that enhances the BER performance of the SIC scheme in a DS/CDMA system considering a practical voice activity factor, and compare BER performance with those of other schemes with or without estimation. Numerical analysis results show that the SIC scheme with the proposed activity-based estimation improves the BER performance compared with that without considering voice activity, and it approaches to that of the ideal estimation as the total number of concurrent users increases. In addition, the higher becomes the maximum attainable SNR, the better becomes the BER performance of the proposed activity-based estimation scheme.

Existing byte error control codes require too many check bits if applied to a memory system that uses recent semiconductor memory chips with wide I/O data such as 16 or 32 bits, i.e., b=16 or 32. On the other hand, semiconductor memory chips are highly vulnerable to random double bit within a memory chip errors when they are used in some applications, such as satellite memory systems. Under this situation, it becomes necessary to design suitable new codes with double bit within a chip error correcting capability for computer memory systems. This correspondence proposes a class of codes called Double bit within a block Error Correcting - Single b-bit byte Error Correcting ((DEC)B-SbEC) codes where block and byte correspond to memory chip and memory sub-array data outputs, respectively. The proposed codes provide protection from both random double bit errors and single sub-array data faults. For most of the practical cases, the (DEC)B-SbEC codes presented in this correspondence have the capability of accommodating the check bits in a single dedicated memory chip.

A new approach on designing a finite field multiplier architecture is proposed. The proposed architecture trades reduction in the number of clock cycles with resources. This architecture features high performance, simple structure, scalability and independence on the choice of the finite field, and can be used in high security cryptographic applications such as elliptic curve crypto-systems in large prime Galois Fields (GF(2m)).

A near-optimum parallel algorithm for bipartite subgraph problem using gradient ascent learning algorithm of the Hopfield neural networks is presented. This parallel algorithm, uses the Hopfield neural network updating to get a near-maximum bipartite subgraph and then performs gradient ascent learning on the Hopfield network to help the network escape from the state of the near-maximum bipartite subgraph until the state of the maximum bipartite subgraph or better one is obtained. A large number of instances have been simulated to verify the proposed algorithm, with the simulation result showing that our algorithm finds the solution quality is superior to that of best existing parallel algorithm. We also test the proposed algorithm on maximum cut problem. The simulation results also show the effectiveness of this algorithm.

A 2-GHz down-converter for wide-band wireless communication systems is described. To achieve both wide-band output characteristic and LO signal suppression, an on-chip LC series resonator which is resonated at LO signal frequency and a transimpedance amplifier which is used in the output buffer circuit are used. To achieve a low sensitivity to temperature, two kinds of bias circuits; a VT reference current source and a bandgap reference current source are used. The measured 3-dB bandwidth of 600 MHz is achieved. The conversion gain varies less than 0.2 dB within 200 MHz 10 MHz and 400 MHz 10 MHz band and 0.7 dB for the temperature range from -34 to 85. At room temperature, conversion gain of 15 dB, NF of 9.5 dB and IIP3 of -5 dBm are obtained respectively. The down-converter is fabricated using Si BiCMOS process with ft=20 GHz, and it occupies approximately 1 mm2.

A method of learning for multi-layer artificial neural networks is proposed. The learning model is designed to provide an effective means of escape from the Backpropagation local minima. The system is shown to escape from the Backpropagation local minima and be of much faster convergence than simulated annealing techniques by simulations on the exclusive-or problem and the Arabic numerals recognition problem.

This paper investigates the accepting powers of one-way alternating and deterministic multi-counter automata operating in realtime. We partially solve the open problem posed in [4], and show that for each k1, there is a language accepted by a realtime one-way deterministic (k+3)-counter automaton, but not accepted by any realtime one-way alternating k-counter automaton.

A fast, low-power 16-bit adder, 32-word register file and 512-bit cache SRAM have been developed using 0.25-µm GaAs HEMT technology for future multi-GHz processors. The 16-bit adder, which uses a negative logic binary look-ahead carry structure based on NOR gates, operates at the maximum clock frequency of 1.67 GHz and consumes 134.4 mW at a supply voltage of 0.6 V. The active area is 1.6 mm2 and there are about 1,230 FETs. A new DC/DC level converter has been developed for use in high-speed, low-power storage circuits such as SRAMs and register files. The level converter can increase the DC voltage, which is supplied to an active-load circuit on request, or supply a minimal DC voltage to a load circuit in the stand-by mode. The power dissipation (P) of the 32-word register file with on-chip DC/DC level converters is 459 mW, a reduction to 25.2% of that of an equivalent conventional register file, while the operating frequency (fc) was 5.17 GHz that is 74.8% of fc for the conventional register file. P for the 512-bit cache SRAM with the new DC/DC level converters is 34.3 mW, 89.7% of the value for an equivalent conventional cache SRAM, with the read-access time of 455 psec, only 1.1% longer than that of the conventional cache SRAM.

In this paper, we address the key enabling technologies for long-span WDM transmissions at 40 Gbit/s. Experimental results of 1.28 Tbit/s (32 40 Gbit/s) unrepeatered transmission over 240 km of conventional 80-µm2 NDSF will be reported. Bi-directional pumped distributed Raman amplification has allowed a record unrepeatered WDM transmission distance over this fibre type, without using effective-area-enlarged fibres or remotely pumped EDFAs.

In this paper, we discuss an IF image rejection system with variable bandwidth and center frequency. The system is consists of a pair of frequency mixers multiplied by the complex sinusoid and a complex analog filter. By employing the complex leapfrog structure using OTA-C configuration and the frequency transformation from the normalized LPF, the proposed system is capable of variable bandwidth and center frequency characteristics. SPICE simulations result more than 43 [dB] image rejection is achieved for 6 [kHz] and 12 [kHz] bandwidths at 50 [kHz] IF.

This paper presents an explicit analysis of the output error power in wideband sampling systems with finite aperture time in the presence of sampling jitter. Sampling jitter and finite aperture time affect the ability of wideband sampling systems to capture high-frequency signals with high precision. Sampling jitter skews data acquisition timing points, which causes large errors in high-frequency (large slew rate) signal acquisition. Finite sampling-window aperture works as a low pass filter, and hence it degrades the high-frequency performance of sampling systems. In this paper, we discuss these effects explicitly not only in the case that either sampling jitter or finite aperture time exists but also the case that they exist together, for any aperture window function (whose Fourier transform exists) and sampling jitter of Gaussian distribution. These would be useful for the designer of wideband sampling data acquisition systems to know how much sampling jitter and aperture time are tolerable for a specified SNR. Some experimental measurement results as well as simulation results are provided as validation of the analytical results.

We present a state-space approach to the problem of designing a parallel feedforward compensator (PFC), which has the same dimension of the input i.e. input-dimensional, for a class of non-square linear systems such that the closed-loop system is strictly passive. For a non-minimum phase system or a system with high relative degree, passification of the system cannot be achieved by any other methodologies except by using a PFC. In our scheme, we first determine a squaring gain matrix and an additional dynamics that is connected to the system in a feedforward way, then a static passifying control law is designed. Consequently, the actual feedback controller will be the static control law combined with the feedforward dynamics. Necessary and sufficient conditions for the existence of the PFC are given by the static output feedback formulation, which enables to utilize linear matrix inequality (LMI). Since the proposed PFC is input-dimensional, our design procedure can be viewed as a solution to the low-order dynamic output feedback control problem in the literature. The effectiveness of the proposed method is illustrated by some numerical examples.

The jitter characteristics of synchronous residual time stamp (SRTS) method used in ATM adaptation layer type 1 (AAL1) are analyzed. In this letter, the root mean square amplitude of filtered SRTS jitter is calculated and the computer simulation has been carried out to show jitter of SRTS method considering also the phase time error of network clocks.

With increased size and issue-width, instruction issue queue becomes one of the most energy consuming units in today's superscalar microprocessors. This paper presents a novel architectural technique to reduce energy dissipation of adaptive issue queue, whose functionality is dynamically adjusted at runtime to match the changing computational demands of instruction stream. In contrast to existing schemes, the technique exploits a new freedom in queue design, namely the voltage per access. Since loading capacitance operated in the adaptive queue varies in time, the clock cycle budget becomes inefficiently exploited. We propose to trade-off the unused cycle time with supply voltage, lowering the voltage level when the queue functionality is reduced and increasing it with the activation of resources in the queue. Experiments show that the approach can save up to 39% of the issue queue energy without large performance and area overhead.

A new dimension-reduced interference suppression scheme is proposed for DS-CDMA systems over multipath channels. The proposed receiver resolves the problems of interference and multipath effects without needing to estimate the channel and training sequences. The minimum mean squared error (MMSE) criterion is used to obtain an algorithm to cancel the interference of each path. The MMSE filter is composed of two stages based on multipath effects. The proposed receiver has low complexity without great degradation of performance compared with the full dimension MMSE receiver with known channel information. Simulation results show that the proposed receiver converges to the optimal value rapidly because of its reduced dimension.

In this paper, we propose a universal biquad filter that can realize all types of 2nd-order functions, such as Low-pass Filters (LPF), High-Pass Filters (HPF), Band-Pass Filters (BPF), Band-Elimination Filters (BEF), and All-Pass Filters (APF). Also, the filter types can be programmable digitally with built-in switches. The proposed circuit can be realized by using a CMOS technology that is suitable for a mixed digital-analog LSI. In addition, the circuit can operate in high frequencies with a low power supply voltage because it is based on a current-mode circuit. Finally, the proposed circuit is simulated by PSpice to confirm its characteristics.

This paper proposes an extension of a conventional current conveyor (CC) concept and its applications. A relaxation of the definition of a conventional CC makes a CC simple. A novel current conveyor named extended current conveyor (ECC) is introduced. An ECC keeps the most significant feature of a CC, i.e., a CC is combination of a VCVS and a CCCS. On the other hand, the other conditions are relaxed. All terminals of the ECC are allowed to have offset voltage and offset current. An ECC usually has a simple structure with a small number of MOSFETs thanks to the relaxation of the conditions. Some circuit configurations for the ECC which have various characteristics are shown. An NIC and OTAs are realized using ECCs. Validity of an ECC is confirmed through HSPICE simulation.