The development of a far-infrared imaging system based on ultrafast THz time-domain spectroscopy has opened a new field of applications of femtosecond technology. We describe the principle of this new imaging technique and report recent progress to augment the possibilities of "T-ray" imaging. These include sub-wavelength-resolution near-field imaging and three-dimensional tomographic reconstruction of a samples refractive index profile.

This paper examines the design considerations for an opamp to be used in a low-power consumption LCD driver IC: (1) slew rate enhancement suitable for a rail-to-rail input stage; (2) improved phase compensation with reduced compensation capacitance; and (3) limitation of instantaneous current consumption. The experimental results support our opamp design approach and indicate the feasibility of a 10 µA quiescent current opamp.

We propose a mechanically tunable passively mode-locked semiconductor laser with a high repetition rate using a simple configuration with a moving mirror located very close to a laser facet. This scheme is demonstrated for the first time by a novel micromechanical laser consisting of an InGaAsP/InP multisegment laser with a monolithic moving micro-mirror driven by an electrostatic comb structure. The main advantage of this laser is the capability of generating high-quality mode-locked pulses stabilized by a phase-locked loop (PLL) with low residual phase noise in a wide repetition-rate tuning range. This paper describes the basic concept and tuning performances utilizing the micromechanical passively mode-locked laser in 22-GHz fundamental mode-locking and in its second-harmonic mode-locking.

A current-to-frequency converter using switched-current (SI) circuits is proposed. The SI integrator with a hold-and-reset switch can control integration by the output signals. In the proposed circuit the oscillation frequency can be controlled by the input current, and the circuit is operated in the current domain. This is verified by HSPICE simulations.

This paper describes a method for analyzing active impedance, i. e. equivalent resistance and equivalent reactance, of a narrow-band transistor Colpitts crystal oscillator. This oscillator, employing an AT-cut resonator filter, has a very narrow-band width and an achievement of extremely low phase-noise characteristics is expected. The analysis proposed is based on an algebraic formula, which employs a nonlinear approximation for transistor gm, and a simplified circuit model. Calculated results are compared with the experimental results in the frequency characteristics of the oscillator active impedance with changing the driving signal current. Good agreement between the calculation and experimental results shows that the proposed technique is suitable for designing Colpitts crystal oscillators with resonator filters. In addition we apply this technique to the analysis of dual-mode crystal oscillators.

The characteristics of several femtosecond solid-state laser systems are described illustrating the diversity of the operational parameters of these lasers. The systems include Pr:YLF, Cr:LiSAF, Cr:Forsterite and Cr:YAG, with wavelength of operation from the visible to the near infra-red. Particular emphasis is placed upon compact, efficient pumping schemes, all-solid-state diode-pumped femtosecond oscillator configurations and newly configured, highly-efficient, tunable, femtosecond lasers pumped by high power fibre lasers.

Input and output queueing two stage ATM switch model which is effective under variable hot-spot traffic is proposed. In order to prevent the degradation of performance due to hot-spot traffic, the hot-spot route is added in which cells destined to the hot-spot port bypass. The switch applies the backpressure mode basically. When the switch judges that the hot-spot port exists, it routes cells destined there to the hot-spot route and applies the queue loss mode on them. We evaluate both the cell loss probability and the mean system delay under the nonuniform traffic with variable hot-spot port by computer simulation. As the results, it is shown that our proposed switch can achieve better switching performance than those of conventional switches under variable traffic condition.

The novel application potential of mode-locked laser diodes (MLLDs) in ultrafast optical signal processing in addition to coherent optical pulse generation is described. As the most fundamental function of MLLDs, we show that the generation of ultrashort (2 ps) coherent optical pulses with low timing jitter (<0. 5 ps) at precisely controlled wavelength and repetition frequency can be achieved by employing a rigid module configuration for an external-cavity MLLD. We then discuss new aspects of MLLDs which are functions of ultrafast all-optical signal processing such as optical clock extraction and optical gating. All-optical clock extraction is based on the timing synchronization of MLLD output to the injected optical data pulse. When the passive mode-locking frequency of an MLLD is very close to the fundamental clock pulse frequency of optical data, the former frequency is pulled into the latter frequency by optical data injection. We show that same-frequency and subharmonic-frequency optical clock pulses can successfully be extracted from optical data pulses at bit rates of up to 80 Gbit/s with very simple configurations and very low excess timing jitter (<0. 1 ps). On the other hand, optical gating is due to absorption saturation and the following picosecond absorption recovery in a saturable absorber (SA) in an MLLD structure incorporating optical gate-pulse amplification. Here, MLLDs are anti-reflection coated and used as traveling wave devices instead of laser oscillators, and small saturation energy (<1 pJ) and ultrafast recovery time (<8 ps) are demonstrated. By combining all these MLLD functions, we successfully demonstrated an experiment with 40- to 10-Gbit/s all-optical demultiplexing processing.

We propose ATM switching nodes with a feedback rate control scheme, AREX, which does not require a large buffer space and does not deteriorate throughput even in large-scale and high-speed ATM-WANs. The goal of our study is to establish the ATM multi-protocol emulation network ALPEN, which is an ATM-WAN architecture for establishing a backbone for multimedia networks. ALPEN achieves an ATM-WAN which is robust against long propagation delays. It also provides high performance without a large buffer space in an ATM-WAN environment. In ALPEN, each transit node informs the edge nodes only its residual bandwidth ratio. The edge nodes support multiple ATM-layer services by emulating them based on the information notified by transit nodes. Our research has been directed towards achieving high performance ABR (Available Bit Rate) service in an ATM-WAN by using ALPEN. The conventional ABR service requires transit nodes to have relatively high calculation power and large buffer space to overcome the effect of the long propagation delays common in WANs. ALPEN node systems have been developed for trials with actual network traffic. ALPEN with AREX reduces the calculation load of transit nodes for ABR service. That is confirmed by the size of the DSP program created for a test system. ALPEN with AREX is, therefore, able to emulate ABR service with higher performance in ATM-WANs, because ALPEN edge nodes are able to indicate the users allowed by ER (Explicit Rate) feedback. The network throughput, maximum queue length at congestion point, and burst transmission rate are determined by simulation. ALPEN with AREX achieves better performances than the conventional ABR network.

Local Area Networks(LANs)are now being used all over the world. The need for cost-effective and high-speed communication services, such as LAN interconnections and large-volume file transfer of all types of data is rapidly increasing. At the same time, Internet services are spreading rapidly, and well soon see the construction of a cost-effective open computer network (OCN). Frame-relay and cell-relay technologies which can achieve higher-speed and higher-performance switching than packet switching, are therefore attracting much attention. Frame-relay technologies are also important because they provide an infrastructure for high-speed data communication as fast as 1. 5 Mbit/sec. Demand for these frame-relay network services have been increasing rapidly. We propose a cost-effective and highly reliable node architecture that we have developed at NTT. Our basic concept for this is based on the all-band switching node architecture which can provide both STM and ATM switches on the same hardware and software platforms, and can accommodate any type of node, such as STM nodes, and ATM nodes for B-ISDN. Our proposed architecture forms highly reliable frame-relay network infrastructure. By using a scale-flexibility building-block architecture, we can construct a small-scale node and a large-scale node cost-effectively. Next, the key technologies of highly reliable node architecture are presented. These are methods of changing over following function-units without frame-loss and/or cell-loss. We present two examples: frame-relay protocol processing units(PPUs)with an N+M-redundant architecture that consists of a number of acting PPUs(ACT)and a number of standby PPUs(SBY)waiting to become active, and duplicate ATM Mux/DemuX blocks(ATM MDXs)with a cell shaping buffer.

We propose a hardware-based packet forwarder for multi-gigabit IP backbone networks. The conventional Internet deploys routers as a key block, but its software-controlled architecture makes it hard to scale up the packet forwarders, especially for table-lookup processes. We propose introducing a pure connectionless (CL) switching approach with a hardware-based forwarder to construct the core part of a scalable IP multi-gigabit backbone. Compared to a software-based forwarder, the table-lookup time is reduced to 100 ns by using content-addressable memory. This hardware-based pipeline implementation easily achieves a maximum forwarding performance of up to 9. 6-Gbps, or 23 million packets per second, for applications ranging from traditional best-effort IP applications to newly emerging time-critical ones. We also consider additional processing when transferring IP packets to enhance best-effort quality. This is done using selective packet-level discarding, including early packet discard and its enhancement, to achieve minimum bandwidth guaranteed service at the packet level. We discuss the IP backbone scalability issue from the viewpoint of new IP-forwarder technologies, paying special attention to connection-oriented (CO) vs. CL switching and hardware vs. software implementation. A pure CL switching solution consisting of a CL server (CLS) and a CL client (CLC) is proposed to balance the hardware- and software-based CL transport functions. As a first step to this solution, a compact CLS has been developed. It supports 600-Mbps throughput and up to 9. 6-Gbps forwarding power using a modular architecture. It was evaluated in an ATM field trial using an experimental network. The results show the effectiveness of our approach to providing enhanced best effort services.

The ATM switching system accommodating the public switched telephone network (PSTN) and narrowband ISDN (N-ISDN) subscribers should ensure the continued support of existing services and applications and guarantee the same quality of voice services for the telephone users. The voice message connection control discussed in this paper is one of the various technical issues for voice services in the interworking function unit, IWF between asynchronous transfer mode (ATM) node and existing synchronous transfer mode (STM) node [2]. We describe the technical points for the implementation of the voice message connection control with the consideration of the development time and cost. And then we discuss several technical problems such as mapping pulse code modulation PCM coded voice data into an ATM cell, different switching operation, keeping performance of the ATM-PSTN interworking system and then present benefits of the voice message connection control processing from the hardware/software point of views.

Recently there has been an enormous growth in the popularity of the Internet. The provisions of access to the Internet will be one of the principal services of the next generation of access networks. In order to provide cost-effective Internet access over ATM-based broadband access networks, the introduction of an available bit rate (ABR) service class is a promising solution. This paper describes our analysis of ABR behavior over ATM-based access networks focusing on explicit-rate-based rate controls and their round-trip time effects. We also describe the hardware implementation of the ABR-based rate controls.

The paper is focused on the architectural and technological solutions that will allow the transition from small to huge capacity ATM Switching Systems. This path starts from the industrial nodes available today and will arrive at the photonic switching architecture. The progressive introduction of photonics has already started with the use of optical interconnections in ATM nodes of hundreds of Gbit/s. A balanced use of microelectronics and photonics is the correct answer to the Terabit/s switching system challenge. After presenting a modular ATM Switching System, some technological solutions like Multichip Modules and Optical Interconnections are presented in order to explain how node capacity can be expanded. Some results of the research activity on photonic Switching are finally shown in order to exploit the great attitude of this technique to obtain very high throughput nodes.

Although ATM networks support various traffic requirements, but many data applications are unable to precisely specify traffic parameters such as bit rate. These applications generally require a dynamic share of the available bandwidth among all active connections, they are called available-bit-rate (ABR) service. Due to bursty and unpredictable pattern of an ABR data stream, its traffic control is more challenging than other services. In this paper, we present an improved ABR traffic control approach, called Offset Proportional Rate Control Algorithm (OPRCA). The proposed approach achieves high link utilization, low delay and weighted fair sharing among contenting sources according to the predefined OPR. The implementation is much simpler than that of existing schemes. OPRCA combines an end-to-end rate control with link-by-link feedback control, and employs a buffering scheme that avoids Head-of-Line (HOL) blocking. It can dynamically regulate the transmission rate of source traffic and maintain the real fairness among all active connections. Simulation results have shown the effectiveness of OPRCA in several performance aspects.

Asynchronous Transfer Mode (ATM) networks are expected to support a diverse mix of traffic sources requiring different Quality Of Service (QOS) guarantees. This paper initially examines several existing scheduling disciplines which offer delay guarantees in ATM switches. Among them, the Earliest-Due-Date (EDD) discipline has been regarded as one of the most promising scheduling disciplines. The EDD discipline schedules the departure of a cell belonging to a call based on the delay priority assigned for that call during the call set-up. Supporting n delay-based service classes through the use of n respective urgency numbers D0 to Dn-1 (D0D1 Dn-1), EDD allows a class-i cell to precede any class-j (j>i) cell arriving not prior to (Dj-Di)-slot time. The main goal of the paper is to determine the urgency numbers (Dis), based on an in-depth queueing analysis, in an attempt to offer ninety-nine percentile delay guarantees for higher priority calls under various traffic loads. In the analysis, we derive system-time distributions for both high- and low-priority cells based on a discrete-time, single-server queueing model assuming renewal and non-renewal arrival processes. The validity of the analysis is justified via simulation. With the urgency numbers (Dis) determined, we further propose a feasible efficient VLSI implementation architecture for the EDD scheduling discipline, furnishing the realization of QOS guarantees in ATM switches.

In the first stage of ATM switching system development, the specifications are sometimes changed in order to match revisions in ITU standards. Fatal problems due to specification changes and unexpected bugs force ASIC redesign and subsequent debugging is seriously restricted. These situations demand the introduction of new hardware design methodologies. This paper proposes a flexible hardware design methodology, based on a novel real-time emulation technique, suitable for large-scale high-speed communication switching systems. The emulation technique offers desirable system performance without Application Specific Integrated Circuit (ASIC) fabrication by using commercial Field Programmable Gate Arrays (FPGAs) along with many simply-structured high-speed interconnect switch devices for multiple FPGA connection. This technique suits line interface units (LUs) that have ASICs operating at about 20 MHz; each LU employs an LU board and emulation boards, both of which have hierarchical structures with sub-boards. The emulation boards are indispensable for realizing prototype systems rapidly and dealing with specification changes. Different types of LUs can be realized by mounting different sub-boards to the common LU board. Each emulation board is attached to the LU board by the same connector used for LU sub-board mounting. Therefore, the proposed structure has the advantage of utilizing a common LU board for system emulation as well as permitting the development of practical systems. To suppress undesirable multiple FPGA partitioning, we propose the emulation board architecture that has two types of sub-boards, each of which carries a different type of FPGA. We produced some portions of the proposed LU and tested the nearly 20 MHz real-time emulation of a complicated ASIC designed to realize ATM cell header conversion functions. The results of multiple FPGA partitioning on the emulation board suggest that the proposed design methodology will yield economic systems that can be freely modified to overcome hardware bugs and comply with future ITU standards.

While active researches have been continuously made on the ATM switch architectures and the QoS service guarantees, most of them have been treated independently in the past. In this paper, we first explain the architectural requirement on the ATM switches to implement the mechanism of QoS guarantees in the context of ATM congestion control. Then we discuss how a vital link between two should be built, and remaining problems are pointed out.

A traffic engineering method has been developed to meet the requirements for efficient bandwidth dimensioning and for a practical and consolidated network design method. It characterizes the offered-traffic burstiness on a transit link by using time-series measurement of the aggregate traffic. It estimates future traffic characteristics based on the average traffic volume at that time which is easily derived from trend analysis, i. e. , an x% increase in bandwidth each year and gives the required link capacity. Simulation showed that the parameters estimated using this method fit the actual behavior of a network well. This method enables an appropriate bandwidth to be allocated to a transit link without having to estimate the specific traffic characteristics for each connection over the link. Once the burstiness parameter and its trend have been identified based on this method, it is possible to use a simple traffic measurement method to detect changes in network traffic and feed them back to the engineering procedure.

To construct the future multimedia network, ATM network technology and services should support cost-effective, high-speed interconnectivity and a variety of service-providing functions. Furthermore, as the infrastructure of future multimedia service, the ATM architecture should be adaptable to changes without needing replacement of its core functions and platform capabilities. This paper presents an overview of the current state of development, standardization and deployment of the ATM network service technologies and architecture concept. It also discusses the trend toward the integration of ATM technology and Internet technology. Also reported is the state of development and standardization for the individual ATM technologies and related issues, including access networks, bearer services, signalling, network middleware, and future ATM switching system technology.