This paper describes the 10-bit 50 MS/s pipelined CMOS A/D Converter using a "reference feed-forward architecture." In this architecture, reference voltage generated in a reference generator block and residual voltage from a DA/subtractor block are fed to the next stage. The reference generator block and DA/subtractor block are constructed using resistive-load, low-gain differential amplifiers. The high-gain, high-speed amplifiers consuming much power are not used. Therefore, the power consumption of this ADC is reduced. The gain matching of the reference voltage with the internal signal range is achieved through the introduction of the reference generator block having the same characteristics as a DA/subtractor block. Each offset voltage of the differential amplifier in the reference generator block and the DA/subtractor block is canceled by the offset cancellation technique, individually. In addition, the front-end sample/hold circuit is eliminated to reduce power consumption. Because of the introduction of high-speed comparators based on the source follower and latch circuit into the first stage A/D subconverter, analog bandwidth is not degraded. This ADC has been fabricated in double-polysilicon, double-metal, 0.5µm CMOS technology, and it operates at 50 MS/s with a 300-mW (Vdd=3.0 V) power consumption. The differential linearity error of less than +/-1 LSB is obtained.

Phase-Locked Loop (PLL) designers have two major problems with regard to the production of practical, portable multimedia communication systems. The first is the difficulty of achieving both fast lock time and low jitter operation simultaneously. This can be particularly difficult because the increase in loop stability needed to reduce jitter increases the lock time. The second is the problem caused by circuits operating at low voltage supplies. Low voltage supplies adversely effect the performance of phase-frequency detectors and charge pump circuits, and they can decrease the noise immunity of oscillators. We have developed a hot-standby architecture, which can achieve both fast lock time and low jitter operation simultaneously, and low-voltage circuit techniques, such as a noise-immune adaptive-gain voltage-controlled oscillator, for a fabricated PLL. This PLL is fully integrated onto a 480-µm450-µm die area with 0.18-µm CMOS technology. It can operate from 0.5 V to 1.2 V, and with a lock range from 40 MHz to 170 MHz at 0.5 V. The jitter is less than 200 ps and the lock time is less than 500 ns.

An experimental latch circuit is fabricated by using a 0.35µm MT-CMOS technology. This latch circuit has a volume smaller by 30%, a delay time shorter by 10%, and has an active power consumption smaller by 10% over those of a conventional MT-CMOS circuit. Furthermore, at a operation frequency of 100 MHz, an SRAM employing this IPS scheme has a standby current which is 0.4% of SRAM's without using IPS scheme.

This paper proposes a direct-sequence spread spectrum (DS/SS) communication system with a new diversity technique designed for indoor multi-path fading channels where path diversity isn't available. In this system, the transmitter sends a same signal from multiple antennas at the same time with intentional time delays, which allows the receiver to distinguish and combine the signals from different antennas. We also consider the combination of this scheme with the conventional receiving antenna diversity for additional diversity gain. Furthermore, it is found that the use of the multiple transmitting antennas decreases the effect of the multiple access interference.

In this paper, a simple frame synchronization method for the SS-CSC syytem is proposed, and the synchronization performance is analyzed. There have been growing interests in the M-ary/SS communication system and the bi-orthogonal modulation system because these systems can achieve the high frequency utilization efficiency. However, the frame synchronization is difficult. We proposed the SS-CSC system, and evaluated the bit error rate (BER) performance of the SS-CSC system under the completed synchronization. The BER performance of the SS-CSC system is much the same as that of the bi-orthogonal modulation system. In this paper, a frame synchronization method using the differential detector and racing counters is proposed. In particular, the lose lock time, the recovery time and the BER performance considering the synchronizing performance are analyzed. In consequence, the BER performance considering the synchronization performance can approach the lower bound of the SS-CSC system by tuning the number of the stages in racing counters.

The bit error rate (BER) performance against average Eb/No (signal energy per bit-to-noise power spectral density ratio) and the capacity of the pilot symbol-assisted coherent orthogonal filter (PSA-COF) based Rake receiver with fast transmit power control (TPC) are evaluated in DS-CDMA reverse link under multipath Rayleigh fading. Fast TPC, which controls all signals transmitted from users in the same cell or sector such that they are received with equal power at the cell site under fast Rayleigh fading, is essential for the PSA-COF based Rake receiver in the reverse link in order to improve the performance degradation experienced when the received signal level drops due to fading as the transmit power is limited in practical systems. Signal-to interference plus noise power ratio (SINR) based fast transmit power control (TPC) is assumed here. By using the fast TPC in reverse link and applying the PSA-COF based Rake receiver to base station (BS), the transmit power of each mobile station (MS) can be significantly reduced, thus increasing link capacity. It is demonstrated that the capacity of the PSA-COF based Rake receiver is about 1.5 times higher than that of the conventional matched filter (MF) receiver in interference-limited channels.

We consider the situation that plural degraded images are obtained. When no prior knowledge about original images are known, these images are individually restored by an optimum restoration filter, for example, by Wiener Filter or by Projection Filter. If correlations between original images are obtained, some restoration filters based on Wiener Filter or Projection Filter are proposed. In this paper, we deal with the case that some pixels or some parts of original images overlap, and propose a restoration method using a formulae for overlapping. The method is based on Partial Projection Filter. Moreover, we confirm an efficacy of the proposed method by numerical examples.

We have developed an efficient recursive algorithm based on the interacting multiple model (IMM) for enhancing speech degraded by additive white noise. The clean speech is modeled by the hidden filter model (HFM). The simulation results shows that the proposed method offers performance gains relative to the previous one with slightly increased complexity.

Pilot symbol-assisted (PSA) decision-directed coherent adaptive array diversity (CAAD) is proposed for increasing the reverse link capacity of DS-CDMA mobile radio systems. In the proposed scheme, PSA channel estimation is applied to coherent Rake combining, and the weights of the antenna array are adaptively updated using both pilot symbols and decision-directed data symbols after Rake combining as references for minimum mean squared error (MMSE) criteria. The reverse link capacity of a 3-sectored base station is evaluated by computer simulation when fast transmit power control (TPC) based on singal-to-interference plus backgound noise power ratio (SIR) measurement is applied under nultipath Rayleigh fading environments. It is shown that a 6-element (sector) CAAD receiver can increase the capacity to about 4.2 times that with a single antenna (per sector) receiver when links are interference-limited. The link capacity achievable with the 6-element CAAD receiver is 1.2 times that with a 6-branch antenna diversity reciever with antenna spacing of 10 carrier wavelengths, while significantly reducing the strong interference from high bit rate transmission (high transmit power) users.

In this paper, three issues concerning the linear adaptive receiver using the LMS algorithm for single-user demodulation in direct-sequence/code-division multiple-access (DS/CDMA) systems are considered. First, the convergence rate of the LMS algorithm in DS/CDMA environment is considered theoretically. Both upper and lower bounds of the eigenvalue spread of the autocorrelation matrix of receiver input signals are derived. It is cleared from the results that the convergence rate of the LMS algorithm becomes slow when the signal power of interferer is large. Second, fast converging technique using a prefilter is considered. The LMS based adaptive receiver using an adaptive prefilter adjusted by a Hebbian learning algorithm to decorrelate the input signals is proposed. Computer simulation results show that the proposed receiver provides faster convergence than the LMS based receiver. Third, the complexity reduction of the proposed receiver by prefiltering is considered. As for the reduced complexity receiver, it is shown that the performance degradation is little as compared with the full complexity receiver.

For traffic control in high speed ATM Networks Usage Parameter Control (UPC) plays an important role. The existing UPC schemes have some limitations. It is difficult to implement policy which involves monitoring vioations while guaranteeing QoS for the compliant connections-particularly with respect to bursty traffic sources. This is due to the difficulty in measuring the Sustained Cell Rate (SCR) and Maximum Burst Size (MBS) parameters simultaneously. To ensure prompt action against policy-violations, speedy detection is an important requirement. But the existing UPC schemes do not have a satisfactory response time. In this paper, we propose a new scheme called Markovian State-Dependent UPC schemes (MSDU) to police SCR and MBS parameter violation simultaneously with a satisfactory response time. The MSDU scheme is performed by using two virtual queues: 1) a Markovian State Dependent Service queue and 2) a Fixed Service queue. The discrete time analysis of the MSDU is carried out for a bursty source which is a Markov-Modulated Bernoulli Process (MMBP). The improved effectiveness of the proposed MSDU is clarified by a numerical comparison with UPC based on standard Leaky Bucket scheme.

In supervisory control, discrete event dynamic systems (DEDSs) are modeled by finite-state automata, and their behaviors described by the associated formal languages; control is exercised by a supervisor, whose control action is to enable or disable the controllable events. In this paper we present a general stability concept for DEDSs, stability in the sense of Lyapunov with resiliency, by incorporating Lyapunov stability concepts with the concept of stability in the sense of error recovery. We also provide algorithms for verifying stability and obtaining a domain of attraction. Relations between the notion of stability and the notion of fault-tolerance are addressed.

Many switching networks are currently designed to support ATM architectures. In this letter, we propose the performance improvement of a network called hybrid dilated banyan network with bypasses at the stage of 42 re-arrangeable output switch. Our letter also includes the performance analysis of the improved hybrid dilated banyan network.

This paper presents a proportional-share CPU scheduler which can support multimedia applications in a general-purpose workstation environment. For this purpose, we have extended the stride scheduler which is designed originally for conventional tasks. New scheduling parameters are introduced to specify timing requirements of multimedia applications. Through the use of the rate regulator, the accuracy error of the scheduling is reduced to 0 (1). Separate task groups are proposed to represent both relative shares and absolute shares. The proposed scheduler is evaluated using a simulation study. The results show that the proposed scheduler achieves improved accuracy and adaptability as well as flexibility.

In this paper, we discuss the use of convolutional codes with a multi-antenna transmission scheme for DS/CDMA systems. The binary input data to a rate 1/M encoder produces M coded bits, which, in turn, are assigned to M different antennas and transmitted from each antenna simultaneously. An intentional delay of several chips duration is introduced at each antenna before transmission, which enables a receiver to distinguish the signals from different antennas. Because the proposed scheme utilizes spatial and time domains for coding, it can achieve not only implicit time-diversity through the use of coding with interleaving, but also space-diversity through the transmission from multiple antennas. Multi-antenna schemes with convolutional codes can perform better than conventional single antenna schemes with the same codes and transmission diversity technique with the same number of transmitting antennas, especially when a fading is relatively slow and interleaving size is limited.

It is well known that M-ary/spread spectrum (M-ary/SS) system is superior to direct-sequence spread spectrum system under AWGN, and can achieve high spectral efficiency. On the other hand, however, the main drawback of this system is that the synchronization acquisition is difficult. In this paper, we propose a new synchronization acquisition method of M-ary/SS system. This method acquires the code synchronization by introducing a symmetrical property in spreading sequences, and detecting this property with the differential decoding technique. As spreading sequences, a set of orthogonal sequences and a set of non-orthogonal sequences are considered. The strong features of proposed systems are that the systems can acquire the code synchronization in carrier band and can reduce the complexity of calculation greatly. Among the comparison results of the systems with newly proposed orthogonal and some specific non-orthogonal spreading sequences, it is especially noted that the latter can reduce the mean acquisition time and calculation complexity much greater than the former.

In this paper, we present orthogonal multi-code CDMA systems with the constant amplitude transmission. In general, the dynamic range of the amplitude of the transmitting signal is very large in the case of orthogonal multi-code CDMA systems. In order to realize the constant amplitude transmission for orthogonal multi-code CDMA systems, we propose a constant amplitude coding. First, we show the basic concept of the constant amplitude coding. And then, we show that the constant amplitude transmission can be realized by the combination of the conventional orthogonal multi-code CDMA and the constant amplitude coding. Finally, the effectiveness of the proposed method is evaluated in terms of the bit error rate performance and it is shown that the proposed method is robust to the non-linear distortion caused by a high power amplifier (HPA).

In this paper, a simple frame synchronization system for M-ary Spread Spectrum (M-ary/SS) communication system is analyzed. In particular, synchronization performance, bit error rate performance, and Spread Spectrum Multiple Access (SSMA) performance are analyzed. The frame synchronization system uses the racing counters. The transmitted signal contains framing chips that are added to spreading sequences. In the receiver, the framing chips are detected from several frames. The authors have proposed the simple frame synchronization system that detects framing chips from consecutive 2 frames. In this system, as the number of framing chips increases, synchronization performance improves and bit error rate performance degrades. In this paper a frame synchronization system that improves bit error rate performance is treated and analyzed. As the rusult, when the number of reference frames is 3, the bit error rate is much improved than the conventional system.

ITU (International Telecommunication Union) has issued request for submission of candidate technologies for IMT (International Mobile Telecommunication)-2000/FPLMTS radio interface in April 1997. In order to propose a candidate technology and to contribute to the production of a world wide standard of IMT-2000, ARIB (Association of Radio Industries and Businesses) has studied radio transmission technologies for IMT-2000. This paper shows the recent study results on IMT-2000 radio transmission technologies in ARIB. Now in ARIB detailed study to produce necessary specifications and prepare of a proposal on candidate radio transmission technology to ITU are being conduced based on wide band DS-CDMA technologies.

Considering that the application of the direct-sequence slotted spread ALOHA communications system to access/control channel is effective in communications systems with traffic channels operating at CDMA mode, the spread ALOHA communications system is discussed in terms of the system configuration and transmission efficiency. The transmission efficiency of the spread ALOHA communications system using a unified spread code is derived by means of two methods. One is based on the simulation of demodulation algorithm, and the other is based on the approximation by modeling. It becomes obvious from quantitative evaluation in terms of the probability of packet success and the throughput performance that the approximated results coincide with the simulated results, and that the modeling is very effective to estimate the transmission efficiency of the spread ALOHA communications system.