In this paper, we discuss the use of convolutional codes with a multi-antenna transmission scheme for DS/CDMA systems. The binary input data to a rate 1/M encoder produces M coded bits, which, in turn, are assigned to M different antennas and transmitted from each antenna simultaneously. An intentional delay of several chips duration is introduced at each antenna before transmission, which enables a receiver to distinguish the signals from different antennas. Because the proposed scheme utilizes spatial and time domains for coding, it can achieve not only implicit time-diversity through the use of coding with interleaving, but also space-diversity through the transmission from multiple antennas. Multi-antenna schemes with convolutional codes can perform better than conventional single antenna schemes with the same codes and transmission diversity technique with the same number of transmitting antennas, especially when a fading is relatively slow and interleaving size is limited.

Pilot symbol-assisted (PSA) decision-directed coherent adaptive array diversity (CAAD) is proposed for increasing the reverse link capacity of DS-CDMA mobile radio systems. In the proposed scheme, PSA channel estimation is applied to coherent Rake combining, and the weights of the antenna array are adaptively updated using both pilot symbols and decision-directed data symbols after Rake combining as references for minimum mean squared error (MMSE) criteria. The reverse link capacity of a 3-sectored base station is evaluated by computer simulation when fast transmit power control (TPC) based on singal-to-interference plus backgound noise power ratio (SIR) measurement is applied under nultipath Rayleigh fading environments. It is shown that a 6-element (sector) CAAD receiver can increase the capacity to about 4.2 times that with a single antenna (per sector) receiver when links are interference-limited. The link capacity achievable with the 6-element CAAD receiver is 1.2 times that with a 6-branch antenna diversity reciever with antenna spacing of 10 carrier wavelengths, while significantly reducing the strong interference from high bit rate transmission (high transmit power) users.

This paper first investigates a relationship between inkdot-depth and inkdot-size of inkdot two-way alternating Turing machines and pushdown automata with sublogarithmic space, and shows that there exists a language accepted by a strongly loglog n space-bounded alternating pushdown automaton with inkdot-depth 1, but not accepted by any weakly o (log n) space-bounded and d (n) inkdot-size bounded alternating Turing machine, for any function d (n) such that limn [d (n)log n/n1/2] = 0. In this paper, we also show that there exists an infinite space hierarchy among two-way alternating pushdown automata with sublogarithmic space.

An experimental latch circuit is fabricated by using a 0.35µm MT-CMOS technology. This latch circuit has a volume smaller by 30%, a delay time shorter by 10%, and has an active power consumption smaller by 10% over those of a conventional MT-CMOS circuit. Furthermore, at a operation frequency of 100 MHz, an SRAM employing this IPS scheme has a standby current which is 0.4% of SRAM's without using IPS scheme.

This paper describes the design and architecture for a newly developed microprocessor suitable for consumer applications, which we call SuperH. To achieve both low-power and high-speed, the SuperH architecture includes 16-bit fixed length instruction code and several power saving features. The 16-bit fixed length instruction code makes the SuperH possible to achieve excellent code efficiency for the SPECint benchmarks when compared with conventional microcontrollers and RISC's for workstations and PC's. As a result, the SuperH provides almost the same code efficiency as that of 8-bit microcontrollers, and also achieves similar performance as that of RISC's with 32-bit fixed length instruction code. The SuperH also incorporates several power reduction techniques through the control of clock frequency and clock distribution. Thus, the 16-bit code format, power saving features, and other architectural innovations make the SuperH particularly proficient for portable multi-media applications.

A rigorous analysis of coupling between two twin-slot antennas using the Finite Difference Time Domain (FDTD) method is reported for the first time. The Phase Cancellation Effect (PGE) is used to reduce the coupling due to the TM0 surface wave mode between the Coplanar Waveguide (CPW) fed cascade-connected twin-slot antennas. To confirm the effectiveness of this approach, coupling between single-slot and twin-slot elements separated by λ0/2 was analysed. The coupling between the two single-slot antennas was S21 = -30.2 dB. For the case of two twin-slot antennas, the coupling was found to be -37.8 dB, 7.6 dB below that of the single-slot antennas. The phase cancellation effect of surface waves is significant in reducing coupling between two twin-slot antennas, in addition to minimising power loss into substrate modes. A memory optimised implementation of the FDTD method with the Berenger Perfectly Matched Layer (PML) Absorbing Boundary Condition (ABC) was used for the numerical analysis.

This paper propeses advanced multi-stage interference canceller systems (MSICS) wihch can estimate radio channels with precision in the direct sequence code division multiple access (DS-CDMA) systems. For the accurate channel estimations, we propose a novel radio channel estimation method specified by the following two signal processing methods. One is the radio channel estimation using both pilot and information signals. The other is the correction of estimated radio channels using adaptation algorithm based on the least mean square method (LMS). The results of our computer simulation indicate that the cell capacity of the advanced MSICS in serial and parallel structure can be increased by about 1.8 and 1.3 times over that of a receiver which does not has a canceller, respectively. Moreover, the advanced MSICS in serial and parallel structure can reduce the required Eb/No by about 1.2 dB and 1.6 dB at a BER of 10-3 compared to the Eb/No of a basic MSICS, respectively.

The bit error rate (BER) performance against average Eb/No (signal energy per bit-to-noise power spectral density ratio) and the capacity of the pilot symbol-assisted coherent orthogonal filter (PSA-COF) based Rake receiver with fast transmit power control (TPC) are evaluated in DS-CDMA reverse link under multipath Rayleigh fading. Fast TPC, which controls all signals transmitted from users in the same cell or sector such that they are received with equal power at the cell site under fast Rayleigh fading, is essential for the PSA-COF based Rake receiver in the reverse link in order to improve the performance degradation experienced when the received signal level drops due to fading as the transmit power is limited in practical systems. Signal-to interference plus noise power ratio (SINR) based fast transmit power control (TPC) is assumed here. By using the fast TPC in reverse link and applying the PSA-COF based Rake receiver to base station (BS), the transmit power of each mobile station (MS) can be significantly reduced, thus increasing link capacity. It is demonstrated that the capacity of the PSA-COF based Rake receiver is about 1.5 times higher than that of the conventional matched filter (MF) receiver in interference-limited channels.

Phase-Locked Loop (PLL) designers have two major problems with regard to the production of practical, portable multimedia communication systems. The first is the difficulty of achieving both fast lock time and low jitter operation simultaneously. This can be particularly difficult because the increase in loop stability needed to reduce jitter increases the lock time. The second is the problem caused by circuits operating at low voltage supplies. Low voltage supplies adversely effect the performance of phase-frequency detectors and charge pump circuits, and they can decrease the noise immunity of oscillators. We have developed a hot-standby architecture, which can achieve both fast lock time and low jitter operation simultaneously, and low-voltage circuit techniques, such as a noise-immune adaptive-gain voltage-controlled oscillator, for a fabricated PLL. This PLL is fully integrated onto a 480-µm450-µm die area with 0.18-µm CMOS technology. It can operate from 0.5 V to 1.2 V, and with a lock range from 40 MHz to 170 MHz at 0.5 V. The jitter is less than 200 ps and the lock time is less than 500 ns.

In this paper, a simple frame synchronization method for the SS-CSC syytem is proposed, and the synchronization performance is analyzed. There have been growing interests in the M-ary/SS communication system and the bi-orthogonal modulation system because these systems can achieve the high frequency utilization efficiency. However, the frame synchronization is difficult. We proposed the SS-CSC system, and evaluated the bit error rate (BER) performance of the SS-CSC system under the completed synchronization. The BER performance of the SS-CSC system is much the same as that of the bi-orthogonal modulation system. In this paper, a frame synchronization method using the differential detector and racing counters is proposed. In particular, the lose lock time, the recovery time and the BER performance considering the synchronizing performance are analyzed. In consequence, the BER performance considering the synchronization performance can approach the lower bound of the SS-CSC system by tuning the number of the stages in racing counters.

The advantages of DRAM-logic integration were demonstrated through a comparison with a conventional separate-chip architecture. Although the available DRAM capacity is restricted by chip size, the integration provides a high throughput and low I/O-power dissipation due to a large number of on-chip I/O lines with small load capacitance. These features result in smaller chip counts as well as lower power dissipation for systems requiring high data throughput and having relatively small memory capacity. The chip count and I/O-power dissipation were formulated for multimedia systems. For the 3-D computer graphics system with a frame of 12801024 pixels requiring a 60-Mbit memory capacity and a 4.8-Gbyte/s throughput, DRAM-logic integration enabled a 1/12 smaller chip count and 1/10 smaller I/O-power dissipation. For the 200-MIPS hand-held portable computing system that had a 16-Mbit memory capacity and required a 416-Mbyte/s throughput, DRAM-logic integration enabled a 1/4 smaller chip count and 1/17 smaller I/O-power dissipation. In addition, innovative architectures that enhance the advantages of DRAM-logic integration were discussed. Pipeline access for a DRAM macro having a cascaded multi-bank structure, an on-chip cache DRAM, and parallel processing with a reduced supply voltage were introduced.

This paper describes the 10-bit 50 MS/s pipelined CMOS A/D Converter using a "reference feed-forward architecture." In this architecture, reference voltage generated in a reference generator block and residual voltage from a DA/subtractor block are fed to the next stage. The reference generator block and DA/subtractor block are constructed using resistive-load, low-gain differential amplifiers. The high-gain, high-speed amplifiers consuming much power are not used. Therefore, the power consumption of this ADC is reduced. The gain matching of the reference voltage with the internal signal range is achieved through the introduction of the reference generator block having the same characteristics as a DA/subtractor block. Each offset voltage of the differential amplifier in the reference generator block and the DA/subtractor block is canceled by the offset cancellation technique, individually. In addition, the front-end sample/hold circuit is eliminated to reduce power consumption. Because of the introduction of high-speed comparators based on the source follower and latch circuit into the first stage A/D subconverter, analog bandwidth is not degraded. This ADC has been fabricated in double-polysilicon, double-metal, 0.5µm CMOS technology, and it operates at 50 MS/s with a 300-mW (Vdd=3.0 V) power consumption. The differential linearity error of less than +/-1 LSB is obtained.

Various high-performance SOI CMOS circuits were fabricated using fully-depleted 0.25-µm gate MOSFETs on a low-dose SIMOX substrate. 2.4-Gbps operations were achieved for I/O and speed conversion circuits which are key elements in a multimedia communication LSI. LVTTL-compatible gate array LSI was developed with an ESD protection circuit which is the first one to meer the MIL standard. A 120-kG test LSI was fabricated on the gate array, and the LSI performances using three kind of technologies; 0.25-µm bulk and SIMOX and 0.5-µm bulk; were compared. A 0.25-µm SIMOX LSI was 10% faster with 35% less power dissipation compared with a 0.25-µm bulk LSI. The 0.25-µm SIMOX LSI can operate at a VDD of 1.2 V to attain the same speed as the 0.5-µm bulk LSI operating at 3.3 V, and this results in 1/40 power reduction. For the high-speed communication use, an ATM-switch LSI with 220-kG and a 110-kb memory was fabricated. A high-performance of 2.5-Gbps interface speed and 312-Mbps internal speed were achieved using 0.25-µm CMOS/SIMOX. This ATM-switch LSI has the greatest bandwidth of 40-Gbps ever reported using a one-chip ATM-switch LSI.

In supervisory control, discrete event dynamic systems (DEDSs) are modeled by finite-state automata, and their behaviors described by the associated formal languages; control is exercised by a supervisor, whose control action is to enable or disable the controllable events. In this paper we present a general stability concept for DEDSs, stability in the sense of Lyapunov with resiliency, by incorporating Lyapunov stability concepts with the concept of stability in the sense of error recovery. We also provide algorithms for verifying stability and obtaining a domain of attraction. Relations between the notion of stability and the notion of fault-tolerance are addressed.

Equivalence of physical optics (PO) and aperture field integration method (AFIM) in the full 360 observation angle is discussed for polyhedron approximate reflectors; the necessary conditions of integration surface in AFIM for the equivalence to PO are presented. In addition to the condition that complete equivalent currents consisting of both geometrical optics (GO) reflected fields from the reflector and direct incident fields from the feed source are used, the integration surface should cap the reflector perfectly and should be in the illuminated region of the GO reflected field. Validity of the conditions is numerically confirmed for a two-dimensional (2-D) strip reflector, 3-D corner reflectors and a 2-D polyhedron approximate reflector.

A bicomplex representation for time-harmonic electromagnetic fields appearing in scattering and diffraction problems is given using two imaginary units i and j. Fieldsolution integral-expressions obtained in the high-frequency and low-frequency limits are shown to provide the new relation between high-frequency diffraction and low-frequency scattering. Simple examples for direct scattering problems are illustrated. It may also be possible to characterize electric or magnetic currents induced on the obstacle in terms of geometrical optics far-fields. This paper outlines some algebraic rules of bicomplex mathematics for diffraction or scattering fields and describes mathematical evidence of the solutions. Major discussions on the relationship between high-frequency and low-frequency fields are relegated to the companion paper which will be published in another journal.

This paper deals with two different quantitative inversion algorithms for reconstructing the complex permittivity profile of bounded inhomogeneous objects from measured scattered field data. The first algorithm involves an imaging method with single frequency excitation and multiincidence illumination and the second algorithm involves a method with synthetic pulse (multifrequency mode) excitation for objects surrounded by freespace or buried in stratified half-space media. Transmission or reflection imaging protocols are considered depending on aimed applications: microwave imaging in free-space from far-field data for target identification, microwave imaging from near-field data for nondestructive testing (NDT), microwave tomography of buried objects for mine detection and localization, civil engineering and geophysical applications. And Edge-Preserving regularization scheme leading to a significant enhancement in the image reconstructions is also proposed. The methods are illustrated with synthetic and experimental data.

The present paper gives a new formulation for rough surface scattering in terms of a stochastic integral equation which can be dealt with by means of stochastic functional approach. The random surface is assumed to be infinite and a homogeneous Gaussian random process. The random wave field is represented in the stochastic Floquet form due to the homogeneity of the surface, and in the non-Rayleigh form consisting of both upward and downward going scattered waves, as well as in the extended Voronovich form based on the consideration of the level-shift invariance. The stochastic integral equations of the first and the second kind are derived for the unknown surface source function which is a functional of the derivative or the increment of the surface profile function. It is also shown that the inhomogeneous term of the stochastic integral equation of the second kind automatically gives the solution of the Kirchhoff approximation for infinite surface.

A method for analyzing the scattering of electromagnetic waves by a general bianisotropic slab is presented by extending the author's previous approaches for anisotropic, chiral, and those periodic media. The analysis is formulated in a unified matrix form, so that scattering characteristics can be obtained by system matrix calculations. The method can be extended straightforwardly to multilayerd and periodic structures. The scattering efficiencies are obtained for the incidence of not only linearly polarized waves but also circularly polarized waves.

Three-dimensional (3-D) instrumentation using an image sequence is a promising instrumentation method for intelligent systems in which accurate 3-D information is required. However, real-time instrumentation is difficult since much computation time and a large memory bandwidth are required. In this paper, a 3-D instrumentation VLSI processor with a concurrent memory-access scheme is proposed. To reduce the access time, frequently used data are stored in a cache register array and are concurrently transferred to processing elements using simple interconnections to the 8-nearest neighbor registers. Based on a row and column memory access pattern, we propose a diagonally interleaved frame memory by which pixel values of a row and column are stored across memory modules. Based on the concurrent memory-access scheme, a 40 GOPS vprocessor is designed and the delay time for the instrumentation is estimated to be 42 ms for a 256256 images.