The search functionality is under construction.
The search functionality is under construction.

Keyword Search Result

[Keyword] TE(21534hit)

18581-18600hit(21534hit)

  • Service Interaction Resolution by Service Node Installed out of the Network

    Nagao OGINO  

     
    PAPER-Communication Software

      Vol:
    E80-B No:10
      Page(s):
    1537-1546

    Service interaction resolution is an important study subject to realize a network supporting various advanced communication services. This paper proposes service interaction resolution by service node connected with the communication network via the user-network interface. By executing various advanced services on the service node, service interactions can be efficiently resolved without adding new functions to the existing network. In other words, the service node enables a unified execution control of all the services including those for the originating side and those for the terminating side. This prevents the signalling system and the signalling procedure from being expanded to resolve service interactions. Moreover, the interactions between the services initiated at the conversation active state can be resolved by the service node equipped with function of receiving plural types of in-band signals. This avoids functional expansion of the switching systems in the network. In this paper, feasibility of the proposed resolution scheme is proved by showing a structure of the service node and a detailed procedure to resolve interactions on that service node. In the proposed service node, the application part is divided into basic call processing part and service processing part, and the basic call processing part is represented by three kinds of basic call processing state models. The proposed method for resolving service interactions can control services execution with high flexibility by using feature interaction table.

  • Cell-Attached Frame Encapsulation Schemes for a Global Networking Service Platform

    Junichi MURAYAMA  Hideo KITAZUME  Naoya KUKUTSU  Hiroyuki HARA  

     
    PAPER-System architecture

      Vol:
    E80-B No:10
      Page(s):
    1429-1435

    This paper proposes cell-attached frame encapsulation schemes in which encapsulation processing can be performed without cell reassembly. The proposed schemes are especially useful for a global networking service platform to integrate widely distributed user LANs into a single internetwork. The platform itself is an ATM-based frame forwarding network composed of access networks and a core network. These elemental networks are interconnected via edge nodes. In order to improve network interworking performance, these edge nodes should perform encapsulation processing without cell reassembly. Our proposal solves this problem. In the proposed schemes, when the first cell of a cell-divided access network frame arrives at an ingress edge node, a core-header-cell is generated from the IP header described in the first cell payload. This core-header-cell is first transmitted and then succeeding incoming cells including the first cell are forwarded cell-by-cell as soon as they arrive. Since cell-by-cell forwarding-processing reduces frame forwarding latency and cell buffer capacity, these schemes are effective from the viewpoint of both performance improvement and cost reduction.

  • Interworking in the Next Millennium

    Stephen M. WALTERS  

     
    INVITED PAPER

      Vol:
    E80-B No:10
      Page(s):
    1383-1385

    As the global telecommunications industry moves into the next millennium, the difficulty, the frequency and the importance of interworking will increase due to three factors. First, as the last decade has shown, new technology is being created and deployed at an ever increasing rate and with higher complexity. This will result in greater difficulty to successfully interwork between technologies. Secondly, because competition has led to an increase in the number of carriers providing services, there will be more and more instances of interworking among carriers. Lastly, because all the carriers are hoping to be profitable, the interworking needs to be fast and easy to implement, have low costs and be seamless for users. Otherwise, increased costs and low customer satisfaction will reduce profits and possibly drive the carrier out of business. This paper will examine these assertions and discuss trends which support this proposition.

  • Non-deterministic Constraint Generation for Analog and Mixed-Signal Layout

    Edoardo CHARBON  Enrico MALAVASI  Paolo MILIOZZI  Alberto SANGIOVANNI-VINCENTELLI  

     
    PAPER-Physical Design

      Vol:
    E80-D No:10
      Page(s):
    1032-1043

    In this paper we propose a comprehensive approach to physical design based on the constraint paradigm. Bounds on the most critical circuit parasitics are automatically generated to help designers and/or physical design tools meet a set of high-level specifications. The constraint generation engine is based on constrained optimization, where various parasitic effects on interconnect and devices are accounted for and dealt with in different manners according to their statistical behavior and their effect on performance.

  • Embedded System Cost Optimization via Data Path Width Adjustment

    Barry SHACKLEFORD  Mitsuhiro YASUDA  Etsuko OKUSHI  Hisao KOIZUMI  Hiroyuki TOMIYAMA  Akihiko INOUE  Hiroto YASUURA  

     
    PAPER-High Level Synthesis

      Vol:
    E80-D No:10
      Page(s):
    974-981

    Entire systems embedded in a chip and consisting of a processor, memory, and system-specific peripheral hardware are now commonly contained in commodity electronic devices. Cost minimization of these systems is of paramount economic importance to manufactures of these devices. By employing a variable configuration processor in conjunction with a multi-precision compiler generator, we show that there are situations in which considerable system cost reduction can be obtained by synthesizing a CPU that is narrower than the largest variable in the application program.

  • Path Mapping: Delay Estimation for Technology Independent Synthesis

    Yutaka TAMIYA  

     
    PAPER

      Vol:
    E80-A No:10
      Page(s):
    1782-1788

    This paper proposes "path mapping," a method of delay estimation for technology independent combinational circuits. Path mapping provides fast and accurate delay estimation using common ideas with the tree covering based technology mapping. First, path mapping does technology mapping for all paths in the circuit with minimum mapped delay. Then, it finds the largest mapped delay among all the paths in the circuit, and answers it as an estimated circuit delay. Experimental results show path mapping estimates more accurate circuit delay than unit delay, and runs much faster than the technology mapping.

  • Enhanced THz Radiation from YBCO Using a-Axis Oriented Thin Films Excited by Ultrashort Optical Pulses

    Shin-ichi SHIKII  Norihide TANICHI  Takeshi NAGASHIMA  Masayoshi TONOUCHI  Masanori HANGYO  Masahiko TANI  Kiyomi SAKAI  

     
    PAPER

      Vol:
    E80-C No:10
      Page(s):
    1297-1303

    The electric field intensity of the THz radiation from YBCO thin films excited by ultrashort laser pulses has been enhanced by a factor of 3 using a-axis oriented films instead of c-axis oriented ones used previously under the same excitation conditions. This corresponds to the enhancement of a factor of 10 for the radiation power. From the transmittance measurements of the millimeter wave for a-and c-axis oriented films, the origin of the enhancement is attributed to the increased fraction of the THz electromagnetic wave power transmitted from the YBCO film to free space. This result indicates that the utilization of the anisotropic properties of high-Tc superconductors is effective to enhance the radiation power.

  • The Signaling Network Deployment for Mobile Networks

    Kuo-Ruey WU  Rong-Hong JAN  

     
    PAPER-Mobile Communication

      Vol:
    E80-B No:10
      Page(s):
    1556-1563

    This paper proposes the signaling network deployment for mobile networks with a goal of reducing the signaling cost and time to set up calls. In this deployment, we solve the heavy concentration of signaling traffic resulting from the centralized database used in current mobile networks. The solution exploits the features of the distributed databases, data partition, locality of mobile users, and Common Channel Signaling System No.7 (CCSS No.7) network architectures. We assume the area served by the mobile network is partitioned into a few zones. There is a database associated with each zone. A numbering database strategy is proposed in this paper for the mobiles to register at some specific nearby databases according to their mobile identification numbers. Thus, a calling party can directly locate the called party by the mobile identification number he/she dialed. This method can reduce over 95% of the location-updating cost and 70% of the location-tracking cost under a general sumulation model. We also present the implementation considerations of this strategy. This implementation is an enhancement of the routing function of the Signaling Connection Control Part in CCSS No.7 protocol stacks. With few modifications on current mobile networks, the proposed strategy can obtain very excellent results.

  • The Formulae of the Characteristic Polarization States in the Co-Pol Channel and the Optimal Polarization State for Contrast Enhancement

    Jian YANG  Yoshio YAMAGUCHI  Hiroyoshi YAMADA  Shiming LIN  

     
    PAPER-Electronic and Radio Applications

      Vol:
    E80-B No:10
      Page(s):
    1570-1575

    For the completely polarized wave case, this paper presents the explicit formulae of the characteristic polarization states in the co-polarized radar channel, from which one can obtain the CO-POL Max, the CO-POL Saddle and the CO-POL Nulls in the Stokes vector form. Then the problem on the polarimetric contrast optimization is discussed, and the explicit formula of the optimal polarization state for contrast enhancement is presented in the Stokes vector form for the first time. To verify these formulae, we give some numerical examples. The results are completely identical with other authors', which shows the validity of the presented method.

  • Obtaining Unique Input/Output Sequences of Communication Protocols

    Wen-Huei CHEN  

     
    PAPER-Communication protocol

      Vol:
    E80-B No:10
      Page(s):
    1509-1513

    A Unique Input/Output (UIO) sequence for the state J of a protocol is a sequence of input/output pairs that is unique to state J. Obtaining UIO sequences from the protocol specification is a very important problem in protocol conformance testing. Let n and m be the total number of states and transitions of the protocol, respectively, and dmax be the largest outdegree of any state, W. Chun and P. D. Amer proposed an O(n2(dmax)2n-1) algorithm to obtain the minimum-length UIO sequences (where the length refers to the number of input/output pairs). However, n and m are normally very large for real protocols. In this paper, we propose an O(n*m) algorithm for obtaining UIO sequences. In theory, our algorithm yields a UIO sequence which contains at most n1 input/output pairs. In experimentation, ten protocol examples collected from recent papers, the ISO TP0 protocol, the ISDN Q. 931 network-side protocol, and the CCITT X. 25 protocol show that in average the obtained UIO sequences are only 11.8% longer than the minimum-length ones, and 97.4% of the existent UIO sequences can be found. And our algorithm is extended for minimizing the cost of UIO sequences and for obtaining synchronizable UIO sequences, which have not been achieved by any algorithm proposed earlier.

  • Performance Improvement of TCP over EFCI-Based ABR Service Class by Tuning of Congestion Control Parameters

    Go HASEGAWA  Hiroyuki OHSAKI  Masayuki MURATA  Hideo MIYAHARA  

     
    PAPER-Communication protocol

      Vol:
    E80-B No:10
      Page(s):
    1444-1453

    We investigate performance of TCP protocol over ATM networks by using a simulation technique. As the ATM layer, we consider (1) rate-based control of the ABR service class and (2) an EPD (Early Packet Discard) technique applied to the UBR service class and (3) and EPD with per-VC accounting for fairness enhancement applied to the UBR service class. In comparison, we adopt a multi-hop network model where the multiple ATM switches are interconnected. In such a network, unfairness among connections is a possible cause of the problem due to differences of the number of hops and/or the round trip times among connections. Simulation results show that the rate-based control method of ABR achieves highest throughput and best fairness in most circumstances. However, the performance of TCP over ABR is degraded once the cell loss takes place due to the inappropriate control parameter setting. To avoid this performance degradation, we investigate the appropriate parameter set suitable to TCP on ABR service. As a result, parameter tuning can improve the performance of TCP over ABR, but limited. We therefore consider TCP over ABR with EPD enhancement where the EPD technique is incorporated into ABR. We last consider the multimedia network environment, where the VBR traffic exists in the network in addition to the ABR/UBR traffic. By this, we investigate an applicability of the above observations to a more generic model. Through simulation experiments, we find that the similar results can be obtained, but it is also shown that parameters of the rate-based congestion control must be chosen carefully by taking into account the existence of VBR traffic. For this, we discuss the method to determine the appropriate control parameters.

  • Generalized Satellite Beam-Switching Modes

    Yiu Kwok THAM  

     
    PAPER-Switching and Communication Processing

      Vol:
    E80-B No:10
      Page(s):
    1523-1528

    Satellite beam-switching problems are studied where there are m up-link beams, n down-link beams and multiple carriers per beam. By augmenting a traffic matrix with an extra row and column, it is possible to find a sequence of switching modes ((0,1)-matrices with genrally multiple unit entries in each row and column) that realize optimal transmission time. Switching modes generated are shown to be linearly independent. The number of switching modes required for an mn matrix is bounded by (m1)(n1)1. For an augmented (m1)(n1) matrix, the bound is then mn1. The bounds on the number of switching modes and the computational complexity for a number of related satellite transmission scheduling problems are lowered. In simplified form, the results (particularly the linear independence of permutation matrices generated) apply to algorithmic decomposition of doubly stochastic matrices into convex combinations of permutation matrices.

  • Art Gallery Information Service System on IP Over ATM Network

    Miwako DOI  Kenichi MORI  Yasuro SHOBATAKE  Tadahiro OKU  Katsuyuki MURATA  Takeshi SAITO  Yoshiaki TAKABATAKE  

     
    PAPER-System architecture

      Vol:
    E80-B No:10
      Page(s):
    1415-1420

    This paper describes technological and operational issues of an image-art-on-demand system, which provides visitors with high-definition images of fine art in a virtual gallery. The system is presented as a typical example of multimedia information service systems on IP over ATM network. The high-definition images of fine arts from a database are interactively selected in a virtual gallery which is generated by an advanced computer graphics (CG) workstation. The generated images of the virtual gallery are transmitted by MPEG-2 over TCP/IP on ATM at 30 frames per second. This system was opened from January 1996 to March 1997 as one project of NTT's joint utilization tests of multimedia communications. As far as we know, this system is the first real-time image-art-on-demand system using MPEG-2 on IP over ATM-WAN to be exhibited to the general public.

  • Mobile Information Service Based on Multi-Agent Architecture

    Nobutsugu FUJINO  Takashi KIMOTO  Ichiro IIDA  

     
    PAPER-System architecture

      Vol:
    E80-B No:10
      Page(s):
    1401-1406

    This paper describes a mobile information access system based on a multi-agent architecture. With the rapid progress of wireless data communications, mobile Internet access will be more and more popular. In mobile environments, user location plays an important role for information filtering and flexible communication service. In this paper, we propose a mobile information service system where a user with a handy terminal accesses Internet in an open air to look up map information and related town information. Each user information is managed by an independent agent process. And the agent provides each user with a personal service collaborating with other applications. A map-based information service example based on this architecture is also described.

  • An Interworking Architecture between TINA-Like Model and Internet for Mobility Services

    Yuzo KOGA  Choong Seon HONG  Yutaka MATSUSHITA  

     
    PAPER-System architecture

      Vol:
    E80-B No:10
      Page(s):
    1393-1400

    In this paper, we propose a scalable service networking architecture as a TINA-like environment for providing flexibly various mobility services. The proposed architecture provides an environment that enables the advent of service providers and rapidly introduces multimedia applications, considering networks scalability. For supporting customized mobility services, this architecture adopts a new service component, which we call Omnipresent Personal Environment Manager (OpeMgr). In order to support mobile users who move between heterogeneous networks, for instance, between the TINA-like environment and the Internet environment, we propose a structure of a gateway. In addition, the proposed architecture uses the fixed and mobile agent approaches for supporting the user's mobility, and we evaluated their performances with comparing those approaches.

  • On Regular Segmented 2-D FPGA Routing

    Yu-Liang WU  Malgorzata MAREK-SADOWSKA  

     
    PAPER

      Vol:
    E80-A No:10
      Page(s):
    1871-1877

    In this paper we analyze the properties of regular segmentation schemes for 2-D Field Programmable Gate Arrays (FPGAs). Such schemes can be viewed as generalization of the Xilinx-like wire segmentations. We discuss their routing properties and propose a new FPGA design concept of applying architectural coupling to improve chip routability. We give the experimental routing results of such architectures for justification.

  • A New Distributed QoS Routing Algorithm for Supporting Real-Time Communication in High-speed Networks

    Chotipat PORNAVALAI  Goutam CHAKRABORTY  Norio SHIRATORI  

     
    PAPER-Communication protocol

      Vol:
    E80-B No:10
      Page(s):
    1493-1501

    Distributed multimedia applications are often sensitive to the Quality of Service (QoS) provided by the communication network. They usually require guaranteed QoS service, so that real-time communication is possible. However, searching a route with multiple QoS constraints is known to be a NP-complete problem. In this paper, we propose a new simple and efficient distributed QoS routing algorithm, called "DQoSR," for supporting real-time communication in high-speed networks. It searches a route that could guarantee bandwidth, delay, and delay jitter requirements. Routing decision is based only on the modified cost, hop and delay vectors stored in the routing table at each node and its directly connected neighbors. Moreover, DQoSR is proved to construct loop-free routes. Its worst case message complexity is O(|V|2), where |V| is the number of nodes in the network. Thus DQoSR is fast and scales well to large networks. Finally, extensive simulations show that average rate of establishing successful connection of DQoSR is very near to optimum (the difference is less than 0.4%).

  • A 3V-30MHz Analog CMOS Current-Mode Bandwidth Programmable Integrator

    Kwang Sub YOON  Jai-Sop HYUN  

     
    PAPER

      Vol:
    E80-A No:10
      Page(s):
    1994-1999

    A design methodology of the analog currentmode bandwidth programmable integrator for a low voltage (3V) and low power application is developed and the integrator designed by this method is successfully fabricated by a 0.8µm CMOS n-well single poly/double metal process. The integrator ocuppies the active chip area of 0.3mm2. The experimental result illustrates a low power dissipation (1.0mW-3.55mW), 65dB of the dynamic range, and bandwidth programmability (10MHz-30MHz) with an external digital 4bit.

  • An lterative Improvement Method for State Minimization of Incompletely Specified Finite State Machines

    Hiroyuki HIGUCHI  Yusuke MATSUNAGA  

     
    PAPER-Logic Design

      Vol:
    E80-D No:10
      Page(s):
    993-1000

    This paper proposes a heuristic algorithm for state minimization of incompletely specified finite state machines (FSMs). The strategy is similar to that in ESPRESSO, a wellknown heuristic algorithm for two-level logic minimization. It consists of generating an initial solution, the set of maximal compatibles, and attempting to apply a series of transformations to the solution. The main transformation is to reduce each compatible in the solution and delete unnecessary compatibles by iterative improvements. Other transformations, such as expansion and merging of compatibles, are also introduced for further reduction. When the number of compatibles is likely to be too large to handle explicitly, they are represented by a Binary Decision Diagram. Experimental results show that the proposed method finds better solutions in shorter CPU times for most of the examples than conventional methods.

  • A Co-Evaluation of the Architectures and the CAD System for Speed-Oriented FPGAs

    Tsunemasa HAYASHI  Atsushi TAKAHARA  Kennosuke FUKAMI  

     
    PAPER

      Vol:
    E80-A No:10
      Page(s):
    1842-1852

    This paper presents an FPGA architecture for high-speed systems, such as next-generation B-ISDN telecommunications systems. Such a system requires an LSI in which an over-10K-gate circuit can be implemented and that has a clock cycle rate of 80MHz. So far, the FPGA architecture has only been discussed in terms of its circuit structure. In contrast we consider the circuit structure of the FPGA along with the performance of its dedicated CAD system. We evaluate several FPGA logic-element structures with a technology mapping method. From these experiments, a multiplexor-based logic-element is found to be suitable for implementing such a high-speed circuit using the BDD-based technology mapping method. In addition, we examine how to best utilize the characteristics of the selected logic-cell structure in designing the wiring structure. It is found that the multiplexor-based cell can be connected efficiently in a clustered wiring structure.

18581-18600hit(21534hit)