This paper presents an FPGA architecture for high-speed systems, such as next-generation B-ISDN telecommunications systems. Such a system requires an LSI in which an over-10K-gate circuit can be implemented and that has a clock cycle rate of 80MHz. So far, the FPGA architecture has only been discussed in terms of its circuit structure. In contrast we consider the circuit structure of the FPGA along with the performance of its dedicated CAD system. We evaluate several FPGA logic-element structures with a technology mapping method. From these experiments, a multiplexor-based logic-element is found to be suitable for implementing such a high-speed circuit using the BDD-based technology mapping method. In addition, we examine how to best utilize the characteristics of the selected logic-cell structure in designing the wiring structure. It is found that the multiplexor-based cell can be connected efficiently in a clustered wiring structure.

As the global telecommunications industry moves into the next millennium, the difficulty, the frequency and the importance of interworking will increase due to three factors. First, as the last decade has shown, new technology is being created and deployed at an ever increasing rate and with higher complexity. This will result in greater difficulty to successfully interwork between technologies. Secondly, because competition has led to an increase in the number of carriers providing services, there will be more and more instances of interworking among carriers. Lastly, because all the carriers are hoping to be profitable, the interworking needs to be fast and easy to implement, have low costs and be seamless for users. Otherwise, increased costs and low customer satisfaction will reduce profits and possibly drive the carrier out of business. This paper will examine these assertions and discuss trends which support this proposition.

In computer hardware there is a constant evolution towards smaller transistor sizes. At the same time, more and more transistors are placed on one chip. Both trends make the pin limitation problem worse. Scaling down chip sizes adds to the shortage of available pins while increasing the number of transistors per chip imposes a higher need for chip terminals. The use of three-dimensional systems would alleviate this pin limitation problem. In order to decide whether the benefits of such systems balance the higher processing costs, one must be able to characterize these benefits accurately. This can be done by estimating important layout properties of electronic designs, such as space requirements and interconnection length values. For a two-dimensional placement, Donath found an upper bound for the average interconnection length that follows the trends of experimentally obtained average lengths. Yet, this upper bound deviates from the experimentally obtained value by a factor of approximately 2 which is not sufficiently accurate for some applications. In this paper, we first extend Donath's technique to a three-dimensional placement. We then compute a significantly more accurate estimate by taking into account the inherent features of the optimal placement process.

This paper describes the new write/erase operation methods in order to improve the read disturb characteristics for Flash EEPROM cells which are written by channel hot electron injection and erased by F-N tunneling emission from the floating gate to the substrate. The new operation methods is either applying a reverse polarity pulse after each erase pulse or applying a series of shorter erase pulses instead of a long single erase pulse. It is confirmed that by using the above operation methods, the leakage current can be suppressed, and then the read disturb life time after 105 cycles write/erase operation is more than 10 times longer in comparison with the conventional method. This memory cell by using the proposed write/erase operation method has superior potential for application to 256 Mbit Flash memories as beyond.

This paper describes a new reduction mechanism of the stress induced leakage current that is induced by step tunneling of electrons through the step tunneling sites. The concept of this mechanism is based on the deactivation of step tunneling sites for thin oxide. It is verified that the deactivation is electrically realized by the injected electrons int the sites. It is because the step tunneling probability of electrons though the deactivated sites is suppressed, since the electron capture cross section of the neutralized deactivation sites becomes extremely low. The deactivation scheme is as follows: (1) The deactivation of tunneling sites can be realized that the tunneling sites trapped holes change to neutralized tunneling sites due to electrons injection. (2) The injected electron can deactivate the activation tunneling sites only under energy level than the energy level of the injected electrons. It is shown that the above reduction phenomenon can be quantifiably with formulation. These results are very important for high reliable thin oxide films and for high performance ULSI.

We successfully observed curent-voltage (I-V) curves which showed the behavior of intrinsic Josephson junctions using Tl2Ba2CaCu2Ox (Tl-2212) thin films on MgO substrates by structuring mesas and measuring the electrical transport properties along the c-axis. For a 55 µm2 mesa, a hysteretic I-V curve was observed up to 80 K, which showed that series-connected SIS-type junctions are formed. Compared with the critical current density (Jc) of more than 106 A/cm2 parallel to the ab-plane, an anisotropic Jc of 1.4102 A/cm2 along the c-axis was observed at 4.9 K. By focusing on the I-V curve at lower bias current, the constant voltage jumps measured at the first seven branches were estimated to be 26 mV. The normal resistance (Rnk) of a unit SIS junction was estimated to be 580 Ω by substituting the measured voltage jump in the Ambegaokar and Baratoff relation. Using the calculation for McCumber parameter (βc), the capacitance (Ck) of the unit SIS junction was estimated to be 3.610-10 F/cm2 at 77 K. The IckRnk product was estimated to be 6.4 mV and the cut-off frequency (fc1/2πRnkCk) was calculated to be 3.1 THz at 77 K. The Jc and the hysteresis decreased with an increase in the mesa area, and finally, for a 300300µm2 mesa, a resistively shunted junction (RSI) like curve without hysteresis was observed up to 98 K. A Jc of 5.6101 A/cm2 along the c-axis was observed at 6.4 K. This may be explained by the higher content of conductive grain boundaries for a larger mesa area.

An analysis is carried out about the reflection influence on the microwave attenuation measurement for moisture content determination. A new method taking into account the reflection influence is proposed and it is proved valid by the experiment results. Using this method, the density dependence of the attenuation is measured and the measured data can be fitted well by a straight line passing through the origin. Therefore, the attenuation per unit density and propagation distance is a function which depends only on the moisture content and the function is useful to the determination of the moisture content.

This paper proposes a new approach that makes it possible for every undergraduate student to perform experiments of developing a Ipipelined RISC processor within limited time available for the course. The approach consists of 4 steps. At the first step, every student implements by himself/herself a pipelined RISC processor which is based on a given, very simple model; it has separate buses for instruction and data memory ("Harvard architecture") to avoid structural hazard, while it completely ignores data control hazards to make implementation easy. Although it is such a "defective" processor, we can test its functionality by giving object code containing sufficient amount of NOP instructions to avoid hazards. At the second step, NOP instructions are deleted and behavior of the developed processor is observed carefully to understand data and control hazards. At the third step, benchmark problems are provided, and every student challenges to improve its performance. Finally every student is requested to present how he/she improved the processor. This paper also describes a new educational FPGA board ASAver.1 which is useful for experiments from introductory class to computer architecture/system class. As a feasibility study, a 16-bit pipelined RISC processor "ASAP-O" has been developed which has eight 16-bit general purpose registers, a 16-bit program counter, and a zero flag, with 10 essential instructions.

Service interaction resolution is an important study subject to realize a network supporting various advanced communication services. This paper proposes service interaction resolution by service node connected with the communication network via the user-network interface. By executing various advanced services on the service node, service interactions can be efficiently resolved without adding new functions to the existing network. In other words, the service node enables a unified execution control of all the services including those for the originating side and those for the terminating side. This prevents the signalling system and the signalling procedure from being expanded to resolve service interactions. Moreover, the interactions between the services initiated at the conversation active state can be resolved by the service node equipped with function of receiving plural types of in-band signals. This avoids functional expansion of the switching systems in the network. In this paper, feasibility of the proposed resolution scheme is proved by showing a structure of the service node and a detailed procedure to resolve interactions on that service node. In the proposed service node, the application part is divided into basic call processing part and service processing part, and the basic call processing part is represented by three kinds of basic call processing state models. The proposed method for resolving service interactions can control services execution with high flexibility by using feature interaction table.

In this paper we analyze the properties of regular segmentation schemes for 2-D Field Programmable Gate Arrays (FPGAs). Such schemes can be viewed as generalization of the Xilinx-like wire segmentations. We discuss their routing properties and propose a new FPGA design concept of applying architectural coupling to improve chip routability. We give the experimental routing results of such architectures for justification.

We propose a top-down approach for cosimulation of hardware/software co-designs for embedded systems and introduce a component logical bus architecture as an interface between software components implemented by processors and hardware components implemented by custom logic circuits. Co-simulation using a component logical bus architecture is possible is the same environment from the stage at which the processor is not yet finalized to the stage at which the processor is modeled in register transfer language. Models based upon a component logical bus architecture can be circulated and reused. We further describe experimental results of our approach.

In this paper, an efficient approach to the synthesis of CA (Cellular Architecture) -type FPGAs is presented. To exploit the array structure of cells in CA-type FPGAs, logic expressions called Maitra terms which can be mapped directly to the cell arrays are generated by using ETDDs (EXOR Ternary Decision Diagrams). Since a traversal of the ETDD is sufficient to generate a Maitra term which takes O (n) steps where n is the number of nodes in the ETDD, Maitra terms are generated very efficiently. The experiments show that the proposed method generates better results than existing methods.

In this paper, we present CB-Power, a hierarchical power analysis and characterization environment of cell-based CMOS circuits. The environment includes two parts, a cell characterization system for timing, input capacitance as well as power and a cell-based power estimation system. The characterization system can characterize basic, complex and transmission gates. During the characterization, input slew rate, output loading, capacitive feedthrough effect and the logic state dependence of nodes in a cell are all taken into account. The characterization methodology separates the power consumption of a cell into three components, e.g., capacitive feedthrough power, short-circuit power and dynamic power. With the characterization data, a cell-based power estimator (CBPE) embedded in Verilog-XL is used for estimating the power consumption of the gates in a circuit. CBPE is also a hierarchical power estimator. Macrocells such as flip-flops and adders are partitioned into primitive gates during power estimation. Experimental results on a set of MCNC benchmark circuits show that the power estimation based on our power modeling and characterization provides within 6% error of SPICE simulation on average while the CPU time consumed is more than two orders of magnitude less.

The analysis of an architecture may provide statistic information on the use of the resources and on the execution time. Some of these information need just a static analysis. Others, such as the execution time, may need dynamic analysis. Moreover as the computation time of behavioral descriptions (control step time unit) and RTL ones (cycle based) may differ a lot, unexpected architectures may be generated by behavioral synthesis. Therefore means to debug the results of behavioral synthesis are required. This paper introduces a new approach to integrate an interactive simulator within a behavioral synthesis tool, thereby allowing concurrent synthesis and simulation. The simulator and the behavioral synthesis are based on the same model. This model allows to link the behavioral description and the architecture produced by synthesis. This paper also discusses an implementation of this concept resulting in a simulator, called AMIS. This tool assists the designer for understanding the results of behavioral synthesis and for architecture exploration. It may also be used to debug the behavioral specification.

A novel CMOS half-wave rectifying transconductor is presented. The proposed circuit utilizes a simple new cascode current subtracter which is obtained from conventional cascode current mirror by a judicious reconfiguration to yield additional subtrahend signal path. The simulated DC transfer characteristics is highly linear with 1.1% linearity error up to 1.5V differential input voltage and the blunt corner at zero-crossing is 20mV. The output resistance is greater than 23MΩ and the total harmonic distortions at 100kHz with 1.5Vp-p in the positive half cycle are better than -46.5dB. The usable operating frequencies are up to 10MHz with maximum peak-to-peak input voltage and 75µW power consumption.

This paper presents a salient method to find an optimal bandwidth for low noise phase-locked loop (PLL) applications by analyzing a discrete-time model of charge-pump PLLs based on ring oscillator VCOs. The analysis shows that the timing jitter of the PLL system depends on the jitter in the ring oscillator and an accumulation factor which is inversely proportional to the bandwidth of the PLL. Further analysis shows that the timing jitter of the PLL system, however, proportionally depends on the bandwidth of the PLL when an external jitter source is applied. The analysis of the PLL timing jitter of both cases gives the clue to the optimal bandwidth design for low noise PLL applications, Simulation results using a C-language PLL model are compared with the theoretical predictions and show good agreement.

The FPGA logic synthesis consists of logic minimization step and technology mapping step. These two steps are usually performed separately to reduce the complexity of the problem. Conventional logic minimization methods try to minimize the number of literals of a given Boolean network, while FPGA technology mapping techniques attempt to minimize the number of basic blocks. However, minimizing the number of literals, which is target architecture-independent feature, does not always lead to minimization of basic block count, which is a FPGA architecture specific feature. Therefore, most of the existing technology mapping systems take into account reorganization of its input circuits to get better mapping results. Such a loosely coupled logic synthesis paradigm may cause difficulties in finding the optimal solution. In this paper, we propose a new logic synthesis approach where logic minimization and technology mapping steps are performed tightly coupled. Our system takes into account FPGA specific features in logic minimization step and thus our technology mapping step does not need to resynthesize the Boolean network. We formulate the technology mapping problem as a graph covering problem. Such formulation provides more global view to optimality and supports versatile cost functions. in addition, a fast and exact library management technique is devised for efficient FPGA cell matching which is one of the most frequently used operations in the FPGA logic synthesis.

Nonuniform transmission lines are crucial in integrated circuits and printed circuit boards, because these circuits have complex geometries and layout between the multi layers, and most of the transmission lines possess nonuniform characteristics. In this article, an efficient numerical method for analyzing nonuniform transmission lines has been presented by using the Chebyshev expansion method and moment techniques. Efficiency on computational cost is demonstrated by numerical example.

A new current-mode sampled-data chaos circuit is proposed. The proposed circuit is composed of an operation block, a parameter block, and a delay block. The nonlinear mapping functions of this circuit are generated in the neuro-fuzzy based operation block. And these functions are determined by supervised learning. For the proposed circut, the dynamics of the learning and the state of the chaos are analyzed by computer simulations. The design conditions concerning the bifurcation diagram and the nonlinear mapping function are presented to clarify the chaos generating conditions and the effect of nonidealities of the proposed circuit. The simulation results showed that the nonlinear mapping functions can be realized with the precision of the order of several percent and that different kinds of bifurcation modes can be generated easily.

A fully differential folded cascode CMOS OP amp is combined with an adaptive bias OTA to increase the slew rate, and a continuous-time CMFB circuit with a push-pull type combination of a NMOS input and a PMOS input differential amplifiers is used to maximize the output voltage swing. The fabricated OP amp using a 0.8 µm digital CMOS process gives more than three times improvement in slew rate with a 15% increase in DC power consumption and a 7.5% increase in chip area compared to the conventional OP amp fabricated on the same die. The output voltage swing was measured to be -0.75 V -0.7 V at the supply voltage of +/-1.2 V.