A digital neuro chip with proliferating neuron architecture is described. This chip simulates a neural network model called the adaptive segmentation of quantizer neuron architecture (ASQA). It has proliferating neurons, and can automatically form the optimum network structure for recognition according to the input data. To develop inexpensive commercial hardware and implement a proliferating neuron architecture, we adopt a virtual neuron system for hardware implementation. Namely, this chip is implemented with only an arithmetic unit for network computations, and the network information such as network structure, synaptic weights and so on, are stored in external memories. We devise our original architecture which can efficiently memorize the network information, and moreover, construct a structured network using the ASQA model. As a result, we can recognize about 3,000 Kanji characters using a single chip and a recognition speed of 4.6 msec/character is achieved on a PC.

A new multiple-valued current-mode (MVCM) integrated circuit using a switched current-source control technique is proposed for a 1.5 V-supply high-speed arithmetic circuit with low-power dissipation. The use of a differential logic circuit (DLC) with a pair of dual-rail inputs makes the input voltage swing small, which results in a high driving capability at a lower supply voltage, while having large static power dissipation. In the proposed DLC using a switched current control technique, the static power dissipation can be greatly reduced because current sources in non-active circuit blocks are turned off. Since the gate of each current source is directly controlled by using a multiphase clock whose technique has been already used in dynamic circuit design, no additional transistors are required for currentsource control. As a typical example of arithmetic circuits, a new 1.5 V-supply 5454-bit multiplier based on a 0.8µm standard CMOS technology is also designed. Its performance is about 1.3 times faster than that of a binary fastest multiplier under the normalized power dissipation. A prototype chip is also fabricated to confirm the basic operation of the proposed MVCM integrated circuit.

The problem of large power dissipation in the conventional Neuron MOS (νMOS) inverter has been resolved by introducing a newly developed deep threshold νMOS inverter. This deep threshold νMOS inverter has a very simple circuit configuration composed of a νMOS inverter using deep-threshold NMOSFET and PMOSFET and two-staged CMOS inverter. Circuit configuration optimization has been conducted by HSPICE simulation. As a result, the power dissipation in the new νMOS inverter has been reduced by a factor of 1/30 as compared to conventional νMOS inverter while the delay-time has been increased only by a factor of 3. The number detector designed with new νMOS gate has 1/6 of the power-delay product and 1/3.5 of the layout area as compared to the implementation by regular CMOS gate.

The segmentation of images into regions that have some common properties is a fundamental problem in low level computer vision. In this paper, the region growing method to segmentation is studied. In the study, a coarse to fine processing strategy is adopted to identify the homogeneity of the subregion of an image. The pixels in the image are checked by a nested triple-layer neighborhood system based hypothesis test. The pixels can then be classified into single pixels or grain pixels with different size and coarseness. Instead of using the global threshold to the region growing, local thresholds are determined adaptively for each pixel in the image. The strength of the proposed method lies in the fact that the thresholds are computed automatically. Experiments for synthetic and natural images show the efficiency of our method.

Genetic algorithms were introduced by Holland in 1975 as a method of solving difficult optimization problems by means of simulated evolution. A major drawback of genetic algorithms is their slowness when emulated by software on conventional computers. Described is an adaptation of the original genetic algorithm that is advantageous to hardware implementation along with the architecture of a hardware framework that performs the functions of population storage, selection, crossover, mutation, fitness evaluation, and survival determination. Programming of the framework is illustrated with the set coverage problem that exhibits a 6,000 speed-up over software emulation on a 100 MHz workstation.

We propose a memory-based processor called a Functional Memory Type Parallel Processor for vector quantization (FMPP-VQ). The FMPP-VQ is intended for low bit-rate image compression using vector quantization. It accelerates the nearest neighbor search on vector quantization. In the nearest neighbor search, we look for a vector nearest to an input one among a large number of code vectors. The FMPP-VQ has as many PEs (processing elements, also called "blocks") as code vectors. Thus distances between an input vector and code vectors are computed simultaneously in every PE. The minimum value of all the distances is searched in parallel, as in conventional CAMs. The computation time does not depend on the number of code vectors. In this paper, we explain the detail of the architecture of the FMPP-VQ, its performance and its layout density. We designed and fabricated an LSI including four PEs. The test results and performance estimation of the LSI are also reported.

A model for estimating the bending loss of 1.3 µm zero-dispersion single-mode fibers at 1.58 µm from the value at 1.55 µm is investigated experimentally and theoretically. An approximated equation for estimating the bending loss ratio of 1.58 µm to 1.55 µm is proposed, which provides good agreement with the experimental results.

In this paper a novel narrow-band bandpass filter with an output pair of analytic signals is presented. Since it is based on the complex analog filter, both synthesis and response characteristics of this filter are different from conventional bandpass filters. In the design of this filter, the frequency shift method is employed and the conventional lowpass to bandpass frequency transformation is not required. The analysis and examples show that the output signal pair of the proposed filter possesses same filtering characteristics and a 90 degree phase shifting characteristics in the passband. Therefore, the proposed filter will be used for a single sideband (SSB) signal generator without quadrature generator.

It is highly desirable to develop an efficient and flexible dynamic channel assignment algorithm in order to realize an integrated traffic TDMA mobile radio communication network. In this paper, an integrated traffic TDMA system is studied in which transmission of voice and data are assumed to occupy one and n time slots in each TDMA frame, respectively. In general, there are two types of channel (time slot) assignment algorithms: the partitioning algorithm and the sharing algorithm. However, they are not well-suited to the multimedia traffic consisting of various information sources that occupy different number of slots per frame. In this paper, assuming that voice is much more sensitive to transmission delay than data, an algorithm based on the sharing algorithm with flexible tima slot management scheme is proposed. Our method tries to vary the number of data slots adaptively so as to improve the quality of servive of voice calls and the system capacity. Computer simulations show the good performance of the proposed algorithm when compared to conventional channel assignment algorithms.

In this paper, we propose a quasi-optimum multiuser detector using co-channel interference cancellation technique in an asynchronous code-division multiple-access communication system, and evaluate its performance by computer simulations. In the proposed detector, maximum likelihood sequence estimation is performed to compare the original received signal with replicas of the signal which are produced from the demodulation data bit sequence of a co-channel interference canceller. In several conditions, the proposed detector is compared with the co-channel interference canceller, and it is shown that the average bit error rate characteristics of the propose detector are improved considerably.

This study was conducted to assess the relationship between fatigue and pupillary responses. Pupillary responses, ECG and blood pressure were measured for 24 hours every 30 min in 8 subjects. A questionnaire was used to rate subjective feeling of fatigue. Twenty-four hours were divided equally into four 6-hour blocks. Subjective feeling of fatigue increased markedly in the fourth block, and the difference in subjective fatigue between fourth and first blocks was significant. Of nine pupillary responses, the pupil diameter was found to decrease with time. With respect to the function of the autonomic nervous system such as heart rate, systolic blood pressure and diastolic blood pressure, only heart rate was found to be sensitive to the increased subjective feeling of fatigue. A significant difference was found in the mean pupil diameter and mean heart rate between the last and first blocks. This result indicates that pupil diameter is related to fatigue and can be used to assess fatigue. Possible implications for fatigue assessment are discussed.

This paper proposes the use, in integrated wireless systems, of the Reserved Idle Signal Multiple Access with Collision Resolution (R-ISMA/CR) protocol for applications in future multimedia mobile communications. It is applied to the integrated voice and data wireless system. Moreover, the consideration is made of the integrated voice and the low-bit video wireless system in R-ISMA/CR. To integrate video we employed not only a packed discard for video packets when the video packet delay is more than a threshold value, but also the connection packet (CP) technique for improving the channel utilization. Finally the integration of voice, data, and low-bit-video wireless system in R-ISMA/CR is considered. The performance are evaluated mainly by simulations.

We propose a soft decision Viterbi decoding scheme and a self-interference cancellation method applicable to a Parallel Combinatory CDMA (PC-CDMA) system. In this decoding scheme, branch metric is calculated for every bit by weighting the output levels of the PC-CDMA correlators so as to enable an effective soft decision capability to the system. The effectivity of this scheme is then further enhanced by the use of a simple pseudo-random bit interleaving scheme. Moreover, to increase the capacity of the PC-CDMA system, we propose a simple self-interference cancellation method for self-induced cross-correlation arising from the multipath environment. This further enhances the efficacy of the decoding scheme because the false contributions of the self-induced cross-correlation component are removed from the branch metric prior to soft decision Viterbi decoding. Finally, we simulated a possible PC-CDMA system with a user data rate of 1.92Mbps, transmitting it at a chip rate of 3.84Mcps and at 7.68Mcps under a multipath-Rayleigh fading interference environment. For a chip rate of 7.68Mcps, BER after Viterbi decoding is less than 3.2e-7 even without the use of interference cancellation. For a chip rate of 3.84Mcps, BER after Viterbi decoding with interference cancellation is 1.0e-4.

A self-learning analog neural network LSI with non-volatile analog memory which can be updated with more than 13-bit resolution has been designed, fabricated and tasted for the first time. The non-volatile memory is attained by a new floating-gate MOSFET device that has a charge injection part and an accumulation part separated by a high resistance. We also propose a partially-serial weight-update architecture in which the plural synapse circuits use a weight-update circuit in common to reduce the circuit area. A prototype chip fabricated using a 1.3-µm double-poly CMOS process includes 50 synapse elements and its computational power is 10 MCPS. The weights can be updated at a rate of up to 40 kHz. This chip can be used to implement backpropagation networks, deterministic Boltzmann machines, and Hopfield networks with Hebbian learning.

In client-server database management systems (DBMSs), inter-transaction caching is an effective technique for improving the performance. However, inter-transaction caching requires a cache consistency maintenance (CCM) protocol to ensure that cached copies at clients are kept mutually consistent. Such a protocol could be complex to implement and expensive to run, since several rounds of message exchange may be required. In this paper, we propose a new CCM scheme based on the primary-copy locking algorithm. In the proposed scheme, a number of lock requests and a data-shipping request are combined into a single message packet to reduce client-server interactions, which are known to be very critical to the performance of clientserver DBMSs. We examine its performance tradeoffs on the basis of a simulation model under a wide range of workloads. The performance results indicate that the proposed scheme improves the overall system throughput significantly over the caching two-phase locking and the optimistic two-phase locking scheme. Its higher performance mainly results from its lower communication overhead and lower degree of transaction blocking ratio.

In contrast to previous algorithms for reconfiguring processor arrays under the assumption that spare rows and columns are placed on the perimeter of the array or on fixed positions, our new algorithm employs movable and partitionable spare rows and columns. The objective of moving and partitioning spare rows and/or columns is the elimination of faulty processors each of which is blocked in all directions to spare processors. The results of our computer simulation indicate that reconfigurability can significantly be improved.

We present a new method for the adaptive control of nonminimum phase continuous-time systems based on the pole-zero placement using approximate inverse systems to avoid the unstable pole-zero cancellations. Using this method effect of the unstable zeros cab be compensated approximately. We show how unstable pole-zoro cancellations can be avoided, and that this method has the advantage of being able to determine an approximate inverse system independently of the plant zeros. The proposed scheme uses only the available input and output data and the stability using approximate inverse systems is analyzed. Finally, the results of computer simulation are presented to illustrate the effectiveness of the proposed method.

We discuss a new decoder for the multiple-valued signed-digit number, using a current-mode CMOS transistor-oriented circuit structure. In this paper, a new decoding method with the selective summation of a redundantly represented addend "O = [-1 r]" is proposed, where r is the radix and the addend is applied to each digit with a negative value and any consecutively higher digit takes which has a value of O. A newly designed literal linear circuit is realized, which has a current-switch function that makes independently the short path when each digit has a value of O. Through the parallel connections of these current swiches, the same addend signal at the lower digit is transmitted in a higher speed, The decoder circuit is tested by using the general circuit simulation software SPICE and the circuit characteristics of the selective summation of a redundantly represented O addend and the output results of the SD decoding operation were simulated. We also evaluated the decoder circuit in terms of the processing speed and the circuit size.

Several multiuser detectors have been recently proposed to combat multiple-access interference and near-far problem for CDMA systems. The performance of a multi-user receiver in combining the decorrelating decision-feedback scheme for a synchronous DS/CDMA system is considered. Using the Gaussian approximation on the multiple-access interference and amplitude estimation errors, we derive a closed form expression for the BER performance of the decorrelating decision-feedback detector in single-path Rayleigh fading channel and power controlled system. And, we show that our analysis agrees with the results of simulations. A modified decision-feedback detector is also proposed and analyzes. Numerical results show that the modified dicision-feedback detector proposed in this paper results in enhanced performance.

As the number of different video compression algorithms in use and also the specific bit rates at which they are operated increase, there is a growing need for converters from one algorithm or bit rate to another. In general, this can only be accomplished by decoding and re-encoding. It has previously been assumed that the additional delays introduced by such decoding and re-encoding are additive and thereby become unacceptable for some interactive applications. This paper shows that it is possible to construct a transcoder such that the aggregate end-to-end delay is substantially less than the sum of the delays from the two encode and decode pairs. Two techniques are described. The first is more general while the second is simpler but is restricted to the case of reducing the bit rate and keeping the same compression algorithm. Results from simulations of the latter method are included.