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18701-18720hit(21534hit)

  • Design and Performance of a New OQPSK Coherent Demodulator Using an Advanced Simultaneous Carrier and Bit-Timing Recovery SchemeApplication to Wireless ATM Systems

    Yoichi MATSUMOTO  Masahiro UMEHIRA  

     
    PAPER

      Vol:
    E80-A No:7
      Page(s):
    1175-1182

    This paper presents a new offset-quadrature-phase-shift-keying (OQPSK) coherent demodulation scheme for wireless asynchronous transfer mode (WATM) systems that premise the Ricean fading communication channels (e.g., typically with derectional antennas). The presented demodulator is basically advanced from a simultaneous carrier and bit-timing recovery (SCBR) scheme by newly employing a phase compensated filter and a reverse-modulation scheme for OQPSK. This advancement aims to enhance the carrier phase tracking performance against the phase fluctuation due to the fading and/or the phase rotation caused by the carrier frequency error of the oscillator. Design consideration and performance evaluation of the demodulator are extensively carried out under Ricean fading channels typical of the WATM systems as well as additive white Gaussian noise (AWGN) channels. The evaluation ressults show that the advanced SCBR (ASCBR) scheme achieves a bit-error-rate/cell-error-rate (BER/CER) performance close to ideal coherent detection with a considerably short preamble, e.g., 8 symbols. Specifically, compared with differential detection (evaluated for QPSK with the hard-wired clock), the new coherent demodulator achieves a significant required Eb/No improvement, which becomes larger as the fading condition degrades. This paper concludes that the ASCBR scheme is a strong candidate for the Ricean-fading-premise WATM systems.

  • An Accurate Model of Fully-Depleted Surrounding Gate Transistor (FD-SGT)

    Tetsuo ENDOH  Tairiku NAKAMURA  Fujio MASUOKA  

     
    PAPER-Novel Structure Devices

      Vol:
    E80-C No:7
      Page(s):
    905-910

    A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) is analyzed. First, the new gate oxide capacitance model and the new threshold voltage model of FD-SGT are proposed. It is shown that the gate oxide capacitance per unit area increases with scaling down the silicon pillar's diameter. It is newly found that the threshold voltage decreases with scaling down the silicon pillar's diameter, because the gate oxide electric fields increase with increasing gate oxide capacitance. Next, by using the proposed models, the new current-voltage characteristics equation of FD-SGT is analytically formulated for the first time. In comparison with the results of the three-dimensional (3D) device simulator, the results of the new threshold voltage model show good agreement within 0.012V error in maximum. The results of the newly formulated current-voltage characteristics also show good agreement within 1.4% average error. The results of this work make it possible to theoretically clear the device designs of FD-SGT and show the new viewpoints for future ULSI's with SGT.

  • Hardware Framework for Accelerating the Execution Speed of a Genetic Algorithm

    Barry SHACKLEFORD  Etsuko OKUSHI  Mitsuhiro YASUDA  Hisao KOIZUMI  Katsuhiko SEO  Takashi IWAMOTO  

     
    PAPER-Multi Processors

      Vol:
    E80-C No:7
      Page(s):
    962-969

    Genetic algorithms were introduced by Holland in 1975 as a method of solving difficult optimization problems by means of simulated evolution. A major drawback of genetic algorithms is their slowness when emulated by software on conventional computers. Described is an adaptation of the original genetic algorithm that is advantageous to hardware implementation along with the architecture of a hardware framework that performs the functions of population storage, selection, crossover, mutation, fitness evaluation, and survival determination. Programming of the framework is illustrated with the set coverage problem that exhibits a 6,000 speed-up over software emulation on a 100 MHz workstation.

  • A Dynamic Channel Assignment Algorithm for Voice and Data Integrated TDMA Mobile Radio

    Lan CHEN  Susumu YOSHIDA  Hidekazu MURATA  

     
    PAPER

      Vol:
    E80-A No:7
      Page(s):
    1204-1210

    It is highly desirable to develop an efficient and flexible dynamic channel assignment algorithm in order to realize an integrated traffic TDMA mobile radio communication network. In this paper, an integrated traffic TDMA system is studied in which transmission of voice and data are assumed to occupy one and n time slots in each TDMA frame, respectively. In general, there are two types of channel (time slot) assignment algorithms: the partitioning algorithm and the sharing algorithm. However, they are not well-suited to the multimedia traffic consisting of various information sources that occupy different number of slots per frame. In this paper, assuming that voice is much more sensitive to transmission delay than data, an algorithm based on the sharing algorithm with flexible tima slot management scheme is proposed. Our method tries to vary the number of data slots adaptively so as to improve the quality of servive of voice calls and the system capacity. Computer simulations show the good performance of the proposed algorithm when compared to conventional channel assignment algorithms.

  • Adaptive Maximum Likelihood Detection of MPSK Signals in Frequency Nonselective Fast Rayleigh Fading

    Fumiyuki ADACHI  

     
    PAPER-Radio Communication

      Vol:
    E80-B No:7
      Page(s):
    1045-1054

    Adaptive maximum likelihood (ML) detection implemented by the Viterbi algorithm (VA) is proposed for the reception of MPSK signals in frequency nonselective fast Rayleigh fading. M-state VA, each state in the VA trellis represents a signal constellation point, is used. Diversity reception is incorporated into the structure of Viterbi decoding. The pilot symbol (unmodulated carrier) is periodically inserted to terminate the trellis so that the phase ambiguity of the detected data sequence is avoided. Applying the per-survivor processing principle (PSPP), adaptive ML detection performs adaptive channel estimation using a simple linear predictor at all trellis states in parallel. The predictor coefficient is stochastically adapted without requiring a priori knowledge of fading channel statistics, based on a recursive least-squares (RLS) adaptation algorithm, to match changes in the statistical properties of the channel (i.e., AWGN of fast/slow fading) using both data and pilot symbols. Simulations of 4PSK signal transmission demonstrate that the proposed adaptive ML detection scheme can track fast fading, thus significantly reducing the irreducible bit error rate (BER) due to Doppler spread in the fading channel. It is also shown that adaptive ML detection provides BER performance close to ideal coherent detection (CD) in AWGN channels.

  • CAM-Based Highly-Parallel Image Processing Hardware

    Takeshi OGURA  Mamoru NAKANISHI  

     
    INVITED PAPER

      Vol:
    E80-C No:7
      Page(s):
    868-874

    This paper describes content addressable memory (CAM) -based hardware that serves as a highly parallel, compact and real-time image-processing system. The novel concept of a highly-parallel integrated circuits and system (HiPIC), in which a large-capacity CAM tuned for parallel data processing is a key element, is introduced. Several hardware algorithms for highly-parallel image processing based on a HiPIC with a CAM are presented in order to demonstrate that the HiPIC concept is effective for compact and real-time image processing. Two kinds of HiPIC-dedicated CAM have been developed. One is embedded on a 0.5-µm CMOS gate array. An embedded CAM up to 64 kbit and logic up to 40 kgate can be integrated on a single chip. The other is a 0.5-µm CMOS full-custom CAM LSI tuned for parallel data processing. A fully-parallel 336-kbit CAM LSI has been successfully developed. The HiPIC concept and CAM-based hardware described here promises to be an important step towards the realization of a compact and real-time image-processing system.

  • A Long Data Retention SOI DRAM with the Body Refresh Function

    Shigeki TOMISHIMA  Fukashi MORISHITA  Masaki TSUKUDE  Tadato YAMAGATA  Kazutami ARIMOTO  

     
    PAPER-Novel Structure Devices

      Vol:
    E80-C No:7
      Page(s):
    899-904

    SOI (Silicon On Insulator) transistors have certain problems due to the floating body. These problems become remarkable in the memory cell transistors of DRAMs. We propose a new refresh function and circuits for SOI DRAMs. And we obtained the result that this refresh function removed the injected hole from the body region and gave stable body potential by the device simulation. Therefore we can realize the long data retention characteristics for SOI DRAMs without an increase of the memory cell area or an additional refresh operation.

  • Performance Evaluation of a Voice/Data Integrated Fast PRMA Protocol

    Jae-Shin JANG  Byung-Cheol SHIN  

     
    PAPER-Mobile Communication

      Vol:
    E80-B No:7
      Page(s):
    1074-1089

    In this work, the performance evaluation of a voice and data integrated fast PRMA has been done. In this newly proposed protocol, every data terminal has an infinite buffer and voice terminals can work independently of data terminals. Thus voice terminals have the higher priority over data terminals. We can, therefore, analyze voice and data subsystems separately. For voice analysis, we use a Markov analysis, and we use the EPA method for data analysis in order to create an analytic form. As performance measures, the voice packet dropping probability, the average voice and data delays, and the total throughput have been derived. It is shown how many voice and data terminals the fast PRMA protocol can accommodate in a frame under the constraints that the voice packet dropping probability should be less than 0.01, and average data packet delay should be less than 250 msec. We also discuss the stable region for this system. Numerical results show close agreement between analysis and computer simulation.

  • Evaluation on Personal Communication Systems with Low and High Degree of Mobility

    Takeshi HATTORI  Hiroshi YOSHIDA  Keisuke OGAWA  

     
    PAPER

      Vol:
    E80-A No:7
      Page(s):
    1249-1256

    This paper presents the evaluation for personal communication systems (PCS). Two types of PCS are supposed for low and high degree of mobility. The service area with 30km radius is covered by a multiple hexagonal cells, which are micro cells and macro cells for the low mobility and high mobility planes respectively. As for a traffic distribution, uniform and exponentially tapered traffic distributions are assumed. After defining the system model, cost evaluation form along with capacity has been derived. The evaluation and discussions are made in terms of cost economy, capacity and spectrum usage in various conditions. It is shown that there exist the optimum cell radius for the prescribed subscriber numbers and the integration of two systems is desirable for the support of full mobility with cost-effectiveness and spectrum efficiency.

  • Performance Analysis of a Hybrid Wireless LAN Using R-ISMA

    Gang WU  Takeshi OKAZAKI  Yoshihiro HASE  

     
    PAPER

      Vol:
    E80-A No:7
      Page(s):
    1272-1280

    In this paper, we propose a modified R-ISMA (reserved idle signal multiple access) protocol for a wireless local area network (WLAN) with a hybrid system construction. The protocol can support a basic service area as large as that supported by a centralized system and allows the direct transmission between neighbor stations as in a distributed system without the problem of hidden terminals. Since a polling scheme is used during transmission of information packets, an ARQ (auto repeat request) scheme is easily applied. A dynamic analysis using transient fluid approximation analysys is used for performance evaluation. In the analysis, we use Fritchman channel model to describe a burst error environment. Some numerical examples using a set of practical system parameters are given. It is shown that the system performance is improved compared with a centralized system with R-ISMA.

  • ECKF-SVD Method for Estimating a Single Complex Sinusoid and Its Parameters in White Noise

    Kiyoshi NISHIYAMA  

     
    PAPER-Digital Signal Processing

      Vol:
    E80-A No:7
      Page(s):
    1308-1317

    A new method is proposed for estimating a single complex sinusoid and its parameters (frequency and amplitude) from measurements corrupted by white noise. This method is called the ECKF-SVD method, which is derived by applying an extended complex Kalman filter (ECKF) to a nonlinear stochastic system whose state variables consist of the AR coefficient (a function of frequency) and a sample of the original signal. Proof of the stability is given in the case of a single sinusoid. Simulations demonstrate that the proposed ECKF-SVD method is effective for estimating a single complex sinusoid and its frequency under a low signal-to-noise ratio (SNR). In addition, the amplitude estimation by means of the ECKF-SVD method is also discussed.

  • Deferred Locking with Buffer Validation on Demand for Client-Server Database Consistency: DL

    Hyeokmin KWON  Songchun MOON  

     
    PAPER-Databases

      Vol:
    E80-D No:7
      Page(s):
    705-716

    In client-server database management systems (DBMSs), inter-transaction caching is an effective technique for improving the performance. However, inter-transaction caching requires a cache consistency maintenance (CCM) protocol to ensure that cached copies at clients are kept mutually consistent. Such a protocol could be complex to implement and expensive to run, since several rounds of message exchange may be required. In this paper, we propose a new CCM scheme based on the primary-copy locking algorithm. In the proposed scheme, a number of lock requests and a data-shipping request are combined into a single message packet to reduce client-server interactions, which are known to be very critical to the performance of clientserver DBMSs. We examine its performance tradeoffs on the basis of a simulation model under a wide range of workloads. The performance results indicate that the proposed scheme improves the overall system throughput significantly over the caching two-phase locking and the optimistic two-phase locking scheme. Its higher performance mainly results from its lower communication overhead and lower degree of transaction blocking ratio.

  • Novel Electronic Properties on Ferroelectric/ferromagnetic Heterostructures

    Hitoshi TABATA  Tomoji KAWAI  

     
    PAPER-Novel Concept Devices

      Vol:
    E80-C No:7
      Page(s):
    918-923

    We have constructed a new concept device with combination of ferroelectric and ferromagnetic materials by a laser ablation technique. An ideal hetero-epitaxy can be obtained owing to the similar crystal structure of perovskite type ferroelectric Pb (Zr, Ti) O3; (so called PZT) and ferromagnetic (La, Sr) MnO3. The ferromagnetic (La, Sr) MnO3 compounds are well known for their colossal magnetoresistance (CMR) properties. The CMR effect is strongly affected by the lattice stress. The PZT, on the other hand, is famous for its large piezoelectrics. We can introduce the lattice stress easily by applying voltage for the piezoelectric compounds. In the heterostructured ferromagnetic/ferroelectric devices, there are remarkable interesting phenomena. Electric properties of the ferromagnetic material can be controlled by piezoelectric effect via distortion of crystal structure.

  • Model for Estimating Bending Loss in the 1.5 µm Wavelength Region

    Kyozo TSUJIKAWA  Masaharu OHASHI  Osamu KAWATA  

     
    LETTER-Opto-Electronics

      Vol:
    E80-C No:7
      Page(s):
    1067-1069

    A model for estimating the bending loss of 1.3 µm zero-dispersion single-mode fibers at 1.58 µm from the value at 1.55 µm is investigated experimentally and theoretically. An approximated equation for estimating the bending loss ratio of 1.58 µm to 1.55 µm is proposed, which provides good agreement with the experimental results.

  • Uplink Capacity of Macro/Spot-Microcellular Systems in Frequency Division CDMA

    Kohji TAKEO  

     
    PAPER

      Vol:
    E80-A No:7
      Page(s):
    1218-1225

    Macro/microcellular systems have recently been proposed to accommodate both fast and slow moving users. If macrocells and microcells reuse the same frequency band in a macro/microcellular system, the interference between both types of cells can become a critical problem and degrade system capacity, particularly in CDMA systems. In this paper, Frequency Division CDMA (FD-CDMA) is applied to CDMA macro/spot-microcellular systems and uplink capacity is evaluated. The CDMA frequency band is divided into several subbands and both macrocells and microcells reuse the same subbands simultaneously. Interference signals from both types of cells are dispersed by dividing the frequency band, and performance degradation resulting from interference is reduced at both the macrocell and microcell. By reusing the same frequency band for macrocells and microcells, the system capacities become more flexible and can be changed according to variations in traffic. This paper describes the detail of the FD-CDMA system. Uplink capacities are calculated for some cell conditions such as microcell size or location through simulation evaluations. A comparison with a non-reuse subband system as well as results of adaptive control of subbands are described.

  • Piezoelectric Transformer Converter with PWM Control

    Toshiyuki ZAITSU  Tamotsu NINOMIYA  Masahito SHOYAMA  

     
    PAPER-Power Supply

      Vol:
    E80-B No:7
      Page(s):
    1035-1044

    A piezoelectric transformer (PT) converter with PWM control is presented. The combination of an active-clamp circuit and a resonant circuit makes it possible to control the output voltage of the PT converter with PWM at a constant switching frequency. The PT converter circuit is evaluated using an AC analysis, and a design procedure is presented. The PT converter implemented on a printed circuit board is experimentally evaluated and a good controllability is successfully achieved.

  • A New High Gain Circularly Polarized Microstrip Antenna with Diagonal Short

    Hiroyuki OHMINE  Hitoshi MIZUTAMARI  Yonehiko SUNAHARA  

     
    PAPER-Antennas and Propagation

      Vol:
    E80-B No:7
      Page(s):
    1090-1097

    A new configuration of high gain circularly polarized microstrip antenna with a diagonal short and its analysis using boundary element method with a radiation load are presented. The center of a radiating patch is shorted with a 45-degree diagonal offset for not only obtaining a high gain but exciting a circular polarization. This configuration leads to achieving high gain with keeping a very low profile configuration. Boundary element method with radiation load which takes into account the effect of radiation loss is employed to analyze this complicated configuration. The radiation load, which is very important when boundary element method is applied to antenna analyses, can be obtained from radiation admittance using recurring technique, so that the accuracy of the antenna characteristic calculations can be improved. This antenna was designed and tested in the L-band and good characteristics, axial ratios and radiation patterns, have been verified.

  • An Interactive Identification Scheme Based on Quadratic Residue Problem

    DaeHun NYANG  EaGu KIM  JooSeok SONG  

     
    PAPER-Information Security

      Vol:
    E80-A No:7
      Page(s):
    1330-1335

    We propose an interactive identification scheme based on the quadratic residue problem. Prover's identity can be proved without revealing his secret information with only one accreditation. The proposed scheme requires few computations in the verification process, and a small amount of memory to store the secret information, A digital signature based on this scheme is proposed, and its validity is then proved. Lastly, analysis about the proposed scheme is presented at the end of the paper.

  • Self-Learning Analog Neural Network LSI with High-Resolution Non-Volatile Analog Memory and a Partially-Serial Weight-Update Architecture

    Takashi MORIE  Osamu FUJITA  Kuniharu UCHIMURA  

     
    PAPER-Neural Networks and Chips

      Vol:
    E80-C No:7
      Page(s):
    990-995

    A self-learning analog neural network LSI with non-volatile analog memory which can be updated with more than 13-bit resolution has been designed, fabricated and tasted for the first time. The non-volatile memory is attained by a new floating-gate MOSFET device that has a charge injection part and an accumulation part separated by a high resistance. We also propose a partially-serial weight-update architecture in which the plural synapse circuits use a weight-update circuit in common to reduce the circuit area. A prototype chip fabricated using a 1.3-µm double-poly CMOS process includes 50 synapse elements and its computational power is 10 MCPS. The weights can be updated at a rate of up to 40 kHz. This chip can be used to implement backpropagation networks, deterministic Boltzmann machines, and Hopfield networks with Hebbian learning.

  • An Analytic Steady-State Current-Voltage Characteristics of Short Channel Fully-Depleted Surrounding Gate Transistor (FD-SGT)

    Tetsuo ENDOH  Tairiku NAKAMURA  Fujio MASUOKA  

     
    PAPER-Novel Structure Devices

      Vol:
    E80-C No:7
      Page(s):
    911-917

    A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) with short channel effects, such as threshold voltage lowering and channel length modulation, is analyzed. First, new threshold voltage model of FD-SGT, which takes threshold voltage lowering caused by decreasing channel length into consideration, are proposed. We express surface potential as capacitance couple between channel and other electrodes such as gate, source and drain. And we analyze how surface potential distribution deviates from long channel surface potential distribution with source and drain effects when channel length becomes short. Next, by using newly proposed model, current-voltage characteristics equation with short channel effects is analytically formulated for the first time. In comparison with a three-dimensional (3D) device simulator, the results of newly proposed threshold voltage model show good agreement within 0.011 V average error. And newly formulated current-voltage characteristics equation also shows good agreement within 0.95% average error. The results of this work make it possible to clear the device designs of FD-SGT theoretically and show the new viewpoints for future ULSI's with SGT.

18701-18720hit(21534hit)