The mesh-connected computers with hyperbus broadcasting are an extension of the mesh-connected computers with multiple broadcasting. Instead of using local buses, we use global buses to connect processors. Such a strategy efficiently reduces the time complexity of the semigroup problem from O(N) to O(log N). Also, the matrix multiplication and the transitive closure problems are solved in O(log N) and O(log2 N) time, respectively. Then, based on these operations, several interesting problems such as the connected recognition problem, the articulation problem, the dominator problem, the bridge problem, the sorting problem, the minimum spanning tree problem and the bipartite graph recognition problem can be solved in the order of polylogarithmic time.

High resolution algorithms in sensor arrays lead to accurate results but with expensive eigendecompositions making its use in real-time applications such as mobile communications relatively difficult. In this paper, a trade-off between accuracy and computational load is accomplished through a simplified algorithm which instead of eigendecompositions, uses the robust QR decomposition for which many effcient parallel (systolic, wavefront array) implementations exist. First, a simple detection scheme is presented and, through simulations, is shown to work very well for sufficient SNR, even when signals are coherent. Outputs of the detection process include simultaneously estimates of signals Direction Of Arrivals (DOA's) and a simple beamformer vector resulting in an estimate of the desired signal. Extensive simulations are performed assuming different scenarios of variations in SNR, DOA's leading to discussions on the possibilities and limitations of the proposed solution.

In this work, a new structure of M-channel linear-phase paraunitary filter banks is proposed, where M is even. Our proposed structure can be regarded as a modification of the conventional generalized linear-phase lapped orthogonal transforms (GenLOT) based on the discrete cosine transform (DCT). The main purpose of this work is to overcome the limitation of the conventional DCT-based GenLOT, and improve the performance of the fast implementation. It is shown that our proposed fast GenLOT is superior to that of the conventional technique in terms of the coding gain. This work also provides a recursive initialization design procedure so as to avoid insignificant local-minimum solutions in the non-linear optimization processes. In order to verify the significance of our proposed method, several design examples are given. Furthermore, it is shown that the fast implementation can be used to construct M-band linear-phase orthonormal wavelets with regularity.

Various reconfiguration schemes against faults of mesh-connected processor arrays have been proposed. As one of them, the mesh-connected processor arrays model based on single-track switches was proposed in [1]. The model has an advantage of its inherent simplicity of the routing hardware. Furthermore, the 2 track switch model [2] and the multiple track switch model [3] were proposed to enhance yields and reliabilities of arrays. However, in these models, Simplicity of the routing hardware is somewhat lost because multiple tracks are used for each row and column. In this paper, we present a builtin self-reconstruction approach for mesh-connected processor arrays which are partitioned into sub-arrays each using single-track switches. Spare PEs which are located on the boundaries of the sub-arrays compensate faulty PEs in these sub-arrays. First, we formulate a reconfigulation algorithm for partitioned mesh-arrays using a Hopfield-type neural network, and then its performance for reconfigulation in terms of survival rates and reliabilities of arrays and processing time are investigated by computer simulations. From the results, we can see that high reliabilites are achieved while processing time is a little and hardware overhead (links and switches) required for reconstruction is as same as that for the track switch model. Next, we present a hardware implementation of the neural algorithm so that a built-in self-reconfigurable scheme may be realized.

The characteristics of a-Si bottom-gate TFT test devices with several kinds of inorganic "quasi-black matrix," such as metal, semiconductor, and insulator, on the top were investigated for various black matrix(BM) resistivities. In the Ia-Vg characteristics, for a BM sheet resistance of about1 1012 Ω/, a high off current and large Vth shift were observed due to the back-gating effects when the BM is charged up. Accrding to the ac dynamic characteristics, there was almost no leakage due to the capacitive coupling between source and drain after 16.6 msec(one frame) when the BM sheet resistance was above 7 1013 Ω/ . It was found that hydrogenated amorphous silicon germanium(a-SiGe:H) film, which has enough optical density, with the sheet resistance above the order of 1014 Ω/ is a promising candidate for an inorganic BM on TFT array.

Communication latency is central to multiprocessor design. This study presents the design principles of the EM-X distributed-memory multiprocessor towards tolerating communication latency. The EM-X overlaps computation with communication for latency tolerance by multithreading. In particular, we present two types of hardware support for remote memory access: (1) priority-based packet scheduling for thread invocation, and (2) direct remote memory access. The priority-based scheduling policy extends a FIFO ordered thread invocation policy to adopt to different computational needs. The direct remote memory access is designed to overlap remote memory operations with thread execution. The 80-processor prototype of EM-X is developed and is operational since December 1995. We execute several programs on the machine and evaluate how the EM-X effectively overlaps computation with communication toward tolerating communication latency for high performance parallel computing.

Super twisted nematic (STN) liquid crystal displays(LCDs) using spiral polymer aligned nematic (SPAN) liquid crystals have been achieved by photo-polymerization of some kinds of chiral monoacrylates in liquid crystalline hosts.The spiral polymer made of a chiral monoacrylate in STN LCD has effect to reduce the driving voltage without any disadvantages for the STN LCD. The relation of chemical structure of a chiral monoacrylate and nature of spiral polymer is discussed.

This paper describes the effects of operating temperature on delay time in a 1-V multi-threshold CMOS(MTCMOS) circuit, Delay-time analysis including the temperature factor shows that the delay-time variation of the CMOS circuit becomes amall for low-voltage operation and the variation is mainly determined by the threshold voltage and its variation-rate with temperature. As a design method of a MTCMOS circuit with both high-threshold and low-threshold MOSFETs, optimization of the low-threshold voltage at which the delay-time of the circuit is independent of operating temperature is described in detail. The validity of the design method is confirmed by the evaluation of a gate-chain TEG and a 1-V 12 K-gate digital-filter LSI fabricated with o.5-µm MTCMOS technology.

A new ATM switch architecture, named shared multibuffering, features great advantages on memory access speed for a large switch, and overall size of buffer memories to achieve excellent cell-loss performance. We have developed a 622-Mb/s 88 shared multibuffer ATM switch with multicast functions and hierarchical queueing functions to accommodate 156-Mb/s, 622-Mb/s and 2.4-Gb/s interfaces. Implementation of the shared multibuffer ATM switch is described with respect to the four sorts of 0.8-µm BiCMOS LSIs and ATM switch boards. The switch board/type-1, with C1-LSI, allows to accommodate effectively 156-Mb/s and 622-Mb/s interfaces, which is suitable for an ATM access system. The switch board/type-2, with C2-LSI, can provide multicast functions and accommodate a 2.4-Gb/s interface. By using four switch boards, it is possible to apply them to a 2.4-Gb/s ATM loop system.

In the design of a large slotted waveguide array, evaluation of mutual couplings between the slots is time consuming. This paper proposes an effective approximation analysis of the external mutual couplings using periodic boundary condition. Simple design procedure is verified for two-dimensional slot array.

This paper concerns optimized facility design for VLSI production. The methods proposed are applicable in planning LSI production facilities with a good balance between the number of machines and the number of operators. The sequence in each processing step is analyzed in detail. A new algorithm based on the queueing model is developed for estimating the simultaneous requirements for the two kinds of resources, machines and operators. This estimation system can be applied to complicated fabrication schemes, such as batch processing, continuous processing, and mixed technologies. This methodology yields guidelines for ASIC LSI production system design.

This paper presents a binary neural network approach for link activation problems in multihop radio networks. The goal of the NP-complete problems is to find a conflict-free link activation schedule with the minimum number of time slots for specified communication requirements. The neural network is composed of NM binary neurons for scheduling N links in M time slots. The energy functions and the motion equations are newly defined with heuristic methods. The simulation results through 14 instances with up to 419 links show that the neural network not only surpasses the best existing neural network in terms of the convergence rate and the computation time, but also can solve large scale instances within a constant number of iteration steps.

Multistage Interconnection Networks (MIN) with multiple outlets are networks which can support higher bandwidth than those of nonblocking networks by passing multiple packets to the same destination. Fault recovery mechanisms are proposed for two of such networks (TBSF/PBSF) with the best use of their inherent fault tolerant capability. With these mechanisms, on-the-fly fault recovery is possible for multiple faults on switching elements. For the link fault, the networks are reconfigured after fault diagnosis, and the network is available with some performance degradation. The bandwidth degradation under multiple faults on link/element is analyzed with both theoretical models and simulation. Through the analysis, F-PBSF shows high fault tolerance under high traffic load and low reliability by using 3 or more banyan networks.

A laser power optimizing method for multi-pulse recording is described. Multi-pulse recording uses the recording pulse formed by bias part and comb part. To obtain best readout signal characteristics and reduce the time for optimizing, new mark pattern is recorded and then two parts of the recording pulse are individually adjusted by evaluating the detected signals during pre-write testing. At the optimized laser power by this method, a good qualitative eyepattern was obtained. As a result, this new method proves to be suitable for the multi-pulse recording and adapted to various disks with different recording properties.

We studied a 0.15-µm InGaP/InGaAs/GaAs pseudomorphic HEMT operating under a negative drain bias, using a parameter extraction technique based on an analytical parameter transformation. The bias-dependent data of smallsignal equivalent circuit elements was obtained from Sparameters measured at up to 62.5 GHz at various bias settings. We then described the intrinsic part of the device using a new empirical large-signal model in which charge conservation and dispersion effects were taken into consideration. As far as we know, this is the first report to clarify the behavior of a HEMT operating under negative drain bias. We included our largesignal model in a commercially-available harmonic-balance simulator as a user-defined model, and designed a 60 GHz MMIC oscillator. The fabricated oscillator's characteristics agreed well with the design calculations.

Physical optics(PO) and the aperture field integration method (AFIM) give accurate and similar field patterns near the first few sidelobes of reflector antennas. It is widely accepted that the use of AFIM is restricted to norrower angles than PO. In this paper, uniform equivalent edge currents of PO and AFIM are compared analytically and their equivalence in high frequency in discussed. It is asymptotically verified that the patterns by AFIM are almost identical to PO fields in the full 360angular region, provided that AFIM uses the equivalent surface currents consisting of two components, that is, the geometrical optics(GO) reflected fields from the reflector and the incident fields from the feed source, the latter of which are often neglected. Slightly weaker equivalence is predicted for cross polarization patterns. Numerical comparison of PO and AFIM confirms all these results, the equivalence holds not only for large but also for a very small refiector of the order of one wavelength diameter.

The order of faults which are targeted for test-pattern generation affects both of the processing time for test generation and the number of generated test-patterns. This order is referred to as a test generation schedule. In this paper, we consider the effect of scheduling in test generation. We formulate the test generation scheduling problem which minimizes the cost of testing. We propose schedulings based on test-pattern generation time, dominating probability and dominated probability, and analyze the effect of these schedulings. In the analysis, we show that the total test-pattern generation time and the total number of test-patterns can be reduced by the scheduling according to the descending order of dominating probability prior to the ascending order of test-pattern generation. This is confirmed by the experiments using ISCAS'85 benchmark circuits. Further, in the experiments, we consider eight schedulings, and show that the scheduling according to the ascending order of dominated probability is the most effective of them.

The purpose of this letter is to investigate the stability of the active two port networks having some restrictions on load and source terminations, and the stability conditions having two inequalities have been obtained. As the terminations making the active two port networks stable can be obtained from these inequalities, these stability conditions are very useful for designing high frequency amplifiers, especially, tuned amplifiers.

Flurorinated liquid crystal compounds having fluorophenyl, difluorophenyl and trifluorophenyl moieties combined with ester linkages, 1,2-ethylenes and covalent bonds were prepared and checked for their physical properties i.e. mesophases, dielectric and optical anisotropy. viscosity, pretilt angle and threshold voltage. By introducing fluorine atom(s) into the molecules, optical anisotropy and threshold voltage decreased, though the nematic temperature range diminished. The investigated compounds were all chemically stable and by using the compounds nematic liquid crystalline mixtures having low threshold voltage, low viscosity, large optical anisotropy and wide nematic ranges which were suitable for AM-LCDs, could be obtained.

Because the match phase in OPS5-type production systems requires most of the system's execution time and memory accesses, we proposed hash-based parallel production systems, CPPS (Clustered Parallel Production Systems), based on the RETE algorithm for distributed memory parallel computers, or multicomputers to reduce such a bottleneck. CPPS was effective in speeding up the match phase, but still left room for optimizations. In this paper, we introduce software cache techniques to memory nodes in the CPPS as one of the optimizations, and implement it on a multicomputer, nCUBE2. The benchmark results show that the CPPS with the software cache is about 2-fold faster than the original, and more than 7-fold faster than the simple hash method proposed by Acharya et al. for a large scale problem. The speed-up can be attributed to decreased communication costs.