We present a new technique for hierarchical intellectual property (IP) protection using partially-mergeable cores. The proposed core partitioning technique guarantees 100% protection of critical-IP, while simplifying test generation for the logic that is merged with the system. Since critical-IP is tested using BIST, the controllability and observability of internal lines in the core are enhanced, and test application time is reduced. Case studies using the ISIT-DLX and Picojava processor cores demonstrate the applicability of our technique.

External pins for tests are precious hardware resources because this number is strongly restricted. Cores are tested via test access mechanisms (TAMs) such as a test bus architecture. When cores are tested via test buses which have constant bit widths, test stimuli and test responses for a particular core have to be transported over these test buses. The core might require more widths for input and output than test buses, and hence, for some part of the test, the TAMs are idle; this is a wasteful usage of the TAMs. In this paper, an optimization method of test accesses with a combined BIST and external test (CBET) scheme is proposed for eliminating the wasteful usage of test buses. This method can minimize the test time and eliminate the wasteful usage of external pins by considering the trade-off between test time and the number of external pins. Our idea consists of two parts. One is to determine the optimum groups, each of which consists of cores, to simultaneously share mechanisms for the external test. The other is to determine the optimum bandwidth of the external input and output for the external test. Our idea is basically formulated for the purpose of eliminating the wasteful external pin usage. We make the external test part to be under the full bandwidth of external pins by considering the trade-off between the test time and the number of external pins. This is achieved only with the CBET scheme because it permits test sets for both the BIST and the external test to be elastic. Taking test bus architecture as an example, a formulation for test access optimization and experimental results are shown. Experimental results reveal that our optimization can achieve a 51.9% reduction in the test time of conventional test scheduling and our proposals are confirmed to be effective in reducing the test time of system-on-a-chip.

We propose a timing driven gate duplication algorithm for the technology independent phase. Our algorithm is a generalization of the gate duplication strategy suggested in [3]. Our technique gets a more global view by duplicating multiple gates at a time. We compare the minimum circuit delay obtained by SIS with the delay obtained by using our gate duplication. Results show that up to 11% improvement in delay can be obtained. Our algorithm does not have an adverse effect on the overall synthesis time, indicating that gate duplication is an efficient strategy for timing optimization.

Reversible variable length codes (RVLCs), which make instantaneous decoding possible in both forward and backward directions, are exploited to code data stream in noisy enviroments. Because there is no redundancy in code words of RVLCs, RVLCs are suitable for very low bit-rate video coding. Golomb-Rice code, one of variable length code for infinite number of symbols, is widely used to encode exponentially distributed non-negative integers. We propose a reversible variable length code by modifying Golomb-Rice code, which is called parity check reversible Golomb-Rice code and abbreviated to P-RGR code. P-RGR code has the same code length distribution as GR code but can detect one-bit error in any arbitrary position of the code stream. The sets of P-RGR code words in both directions are identical so that they can be constructed by nearly the same algorithm. Furthermore, this paper also gives a general construction method for all instantaneously decodable RGR codes.

In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such that a clock-input timing of each register is a multiple of a predefined unit delay and the wire length from a clock buffer to an element driven by it is bounded. The clock trees are constructed for several practical circuits. The size of constructed clock tree is comparable to a zero skew clock tree. In order to assure the practical quality of the clock trees, they are examined under the five delay conditions, which cover various environmental and manufacturing conditions. As a result, they are proved stable under each condition and improve the clock speed up to 17.3% against the zero skew clock trees.

Topological sorting is, given with a directed acyclic graph G=(V,E), to find a total ordering of the vertices such that if (u,v)E then u is ordered before v. Instead of topological sorting, we are interested in how many total orderings exist in a given directed acyclic graph. We call such a total ordering as legal sequence and the problem of finding total number of legal sequences as legal sequence number problem. In this paper, we firstly give necessary definitions and known results obtained in our previous research. Then we give a method how to obtain legal sequence number for a class of directed acyclic graphs, extended 2-b-SPGs. Finally we discuss the complexity of legal sequence number problem for extended 2-b-SPGs.

A workflow is a flow of work carried out by workers, and workflow management is to automate the flow of work. In workflow management, an actual work is carried out based on the workflow, which is called case. In order to effectively meet various requirements, it is necessary to change current workflow dynamically, which is called dynamic workflow change. When the dynamic change is required, there exist cases in the workflow. In order to handle these cases and further to keep the queuing order, the dynamic change takes period of time (called transient time) until the changed workflow becomes steady state again. During the transient time, workers are forced to do irregular work, and therefore it is important to clarify if a change type takes shorter transient time. In this paper, we do the performance evaluation on transient time of dynamic workflow changes. To do so, we first give a definition of transient time, and then propose methods of computing transient time of three change types proposed by Ellis et al. Finally, we do the performance evaluation for 90 dynamic changes by computing the transient times.

Petri net is a mathematical model for concurrent systems. Liveness is one of important properties of Petri net. Liveness problem of general Petri net is of exponential space complexity and subclasses are suggested with less computational complexity. It is well known that liveness problem of bounded (extended) free choice net is solved in deterministic polynomial time. This paper treats liveness problem of AC/DC nets. AC/DC net is a subclass of Petri net that exhibits no confusion (mixture of concurrency and conflict). This class properly includes the class of free choice nets. It is shown that every minimal siphon of an AC/DC net is trap if and only if every strongly connected siphon is a trap. This result shows that monotone liveness of bounded AC/DC net is solved in deterministic polynomial time. It is shown that this result is true of bounded time AC/DC net with static fair condition.

The legal firing sequence problem of Petri nets (LFS) is one of fundamental problems in the analysis of Petri nets, because it appears as a subproblem of various basic problems. Since LFS is shown to be NP-hard, various heuristics has been proposed to solve the problem of practical size in a reasonable time. In this paper, we propose a new algorithm for this problem. It is based on the partial order verification technique, and reduces redundant branches in the search tree. Moreover, the proposed algorithm can be combined with various types of heuristics.

This paper describes a design scheme of generalized minimum variance controllers (GMVC) using a group method of data handling (GMDH) network for nonlinear systems. Concretely, the predictive value of the output required in the GMVC is obtained by using the GMDH which is a kind of multilayered networks. Since the predictive value of the output in GMVC is calculated by a nonlinear model which is generated by the GMDH network, one can expect to obtain the better control performance than that by the conventional scheme. The behavior of the newly proposed control scheme is evaluated on numerical examples.

Spatiotemporal chaos in a multidomain regime in a Gunn-effect device is numerically investigated as an example of collective domain oscillations under global constraints. The dynamics of carrier densities are computed using a set of model partial differential equations. Numerical results reveal some distinctive and chaotic clustering features caused by the global coupling and boundary effects. The chaotic regime is then characterized in terms of a Lyapunov spectrum and Lyapunov dimension, the latter increasing with the size of the system.

Agent technology is widely recognized as a new paradigm for the design of concurrent software and systems. The aim of this paper is to give a mathematical foundation for the design and the analysis of multi-agent systems by means of a Petri-net-based model. The proposed model, called PN2, is based on place/transition nets (P/T nets), which is one of the simplest classes of Petri nets. The main difference of PN2's from P/T nets is that each token, representing an agent, is also a P/T net. PN2's are sufficiently simple for the mathematical analysis, such as invariant analysis, but have enough modeling power.

This paper presents a new framework for synthesizing look-up table (LUT) networks. Some of the existing LUT network synthesis methods are based on one or two functional (Boolean) decompositions. Our method also uses functional decompositions, but we try to use various decomposition methods, which include algebraic decompositions. Therefore, this method can be thought of as a general framework for synthesizing LUT networks by integrating various decomposition methods. We use a cost database file which is a unique characteristic in our method. We also present comparisons between our method and some well-known LUT network synthesis methods, and evaluate the final results after placement and routing. Although our method is rather heuristic in nature, the experimental results are encouraging.

This paper proposes a heuristic algorithm which, given a basis of a subspace of the space of cuspforms of weight 2 for 0(N) which is invariant for the action of the Hecke operators, tests whether the subspace corresponds to a quotient A of the jacobian of the modular curve X0(N) such that A is the jacobian of a curve C. Moreover, equations for such a curve C are computed which make the quotient suitable for applications in cryptography. One advantage of using such quotients of modular jacobians is that fast methods are known for finding their number of points over finite fields.

This paper proposes a non-linear adaptive algorithm, the amplitude banded RLS (ABRLS) algorithm, as an adaptation procedure for time variant channel equalizers. In the ABRLS algorithm, a coefficient matrix is updated based on the amplitude level of the received sequence. To enhance the capability of tracking for the ABRLS algorithm, a parallel adaptation scheme is utilized which involves the structures of decision feedback equalizer (DFE). Computer simulations demonstrate that the novel ABRLS based equalizer provides a significant improvement relative to the conventional RLS DFE on a rapidly time variant communication channel.

In this paper we present two contributions for a set of local transformations (a selection set) to improve a performance of a very large circuit. The first contribution is an idea of "padding node" and "multi-separator-set. " We have proven that combination of padding node and multi-separator-set provides the optimum selection set. The second contribution is our heuristic method to find a semi-optimum multi-separator-set, which uses a network flow algorithm. Our method is robust for very large circuits, because its memory usage and calculation time are linear and polynomial order with the size of the circuit. We have compared our method with Singh's selection function method, which provides the optimum selection set and is the best method in literature to date. Our method has successfully optimized delays of all circuits, while Singh's selection function method has aborted with three large circuits because of memory overflow. The results also has shown our method has a comparable capability in delay optimization to Singh's method, although our method is heuristic.

In this paper, we present a new algorithm for statistical static timing analysis of a CMOS combinatorial circuit, which takes correlations into account to improve accuracy of the distribution of the maximum delay of the circuit. The correlations treated in the algorithm are not only the one between distributions of arrival times of input signals to a logic gate but also correlation between switching delays of a logic gate and correlation between interconnect delays of a net. We model each delay by a normal distribution, and use a normal distribution of two stochastic variables with a coefficient of correlation for computing the maximum of two delays. Since the algorithm takes the correlation into account, the time complexity is O(m2) in the worst-case, where m is the number of edges of the graph representing a given circuit. But, for real combinatorial circuits, the complexity is expected to be less than this.

We propose a transistor sizing method that downsizes MOSFETs inside a cell to eliminate redundancy of cell-based circuits as much as possible. Our method reduces power dissipation of detail-routed circuits while preserving interconnects. The effectiveness of our method is experimentally evaluated using 3 circuits. The power dissipation is reduced by 75% maximum and 60% on average without delay increase. Compared with discrete cell sizing, the proposed method reduces power dissipation furthermore by 30% on average.

In this paper, we study nonblocking supervisory control of discrete event systems under partial observation. We introduce a weak normality condition defined in terms of a modified natural projection map. The weak normality condition is weaker than the original one and stronger than the observability condition. Moreover, it is preserved under union. Given a marked language specification, we present a procedure for computing the supremal sublanguage which satisfies Lm(G)-closure, controllability, and weak normality. There exists a nonblocking supervisor for this supremal sublanguage. Such a supervisor is more permissive than the one which achieves the supremal Lm(G)-closed, controllable, and normal sublanguage.

In an optical fiber ring topology network such as FDDI (Fiber Distributed Data Interface) rings and SONET (Synchronous Optical Network) rings, the number of consecutively bypassed failed stations is limited by the optical power loss constraint. In recent years, this situation was represented as a consecutive k-out-of-n:F system and the two-terminal reliability was presented in the literature, but K-terminal reliability has not been presented. In this paper, we obtain K-terminal reliability expressions for dual-counter rotating networks (DR's) that use both self-heal and station-bypass switches in which all components (stations, links and bypass switches) can fail. The results are useful in evaluating the reliabilities of FDDI ring networks parametrically and making reliability comparisons. This method can be used to obtain a closed-form reliability expression in a more general ring-network such as 'ring of trees. '