Recently, Kasahara and Murakami proposed new product-sum type public-key cryptosystems with the Chinese remainder theorem, Methods B-II and B-IV. They also proposed a new technique of selectable encryption key, which is referred to as 'Home Page Method (HP Method).' In this paper, first, we describe Methods B-II and B-IV. Second, we propose an effective attack for Method B-II and discuss the security of Methods B-II and B-IV. Third, applying the HP Method to Methods B-II and B-IV, we propose new product-sum type PKC with selectable encryption key. Moreover, we discuss the security of the proposed cryptosystems.

Today, an ultra-high capacity transmission system based on N40 Gb/s channel rate is the most promising approach to achieve multi-terabit/s of capacity over a single fiber. We have demonstrated 5.12 Tbit/s transmission of 128 channels at 40 Gbit/s over 3100 km and 10.24 Tbit/s transmission of 256 channels at 42.6 Gbit/s (using FEC) over 100 km, based on four main technologies: 40 Gbit/s electrical time-division multiplexing (ETDM), vestigial sideband demultiplexing (VSB), advanced amplifier technology including Raman amplification and TeraLightTM fiber. A record spectral efficiency of 1.28 bit/s/Hz is applied to achieve 10.24 Tbit/s transmission within the C- and L-band.

Phase-inversion between neighboring pulses appearing in carrier-suppressed return-to-zero pulses is effective in reducing the signal distortion due to chromatic dispersion and nonlinear effects. A generation method of the anti-phase pulses at 40 GHz is demonstrated by using semiconductor mode-locked lasers integrated with chirped gratings. Operation principle and pulse characteristics are described. Suppression of pulse distortion due to fiber dispersion is confirmed for generated anti-phase pulses. Repeaterless 150-km dispersion-shifted-fiber L-band transmission at 42.7 Gbit/s is demonstrated by using the pulse source.

In leased line services used by ISPs (Internet Service Providers) the bandwidth is fixed, but the traffic changes dynamically. Therefore, there is a necessity for ISPs to accommodate extra capacity to meet peak usage demands; many resources are not used in off-peak hours. To address this, we propose an auction method for the dynamic allocation of bandwidth to ISPs sharing backbone networks. By this method, backbone networks can be used effectively as each ISP is able to secure bandwidth according to its own policy. The Internet users can also be expected to receive good services, as it enables them to obtain information about all ISPs, such as the access fee and QoS (quality of service) provided, and to select congenial ISPs from among all ISPs according to this information. In this study, we compare a dynamic bandwidth allocation service with a leased line service (fixed allocation of bandwidth to ISPs) by using the users' utility to estimate the effectiveness of the proposed method.

A new dimension-reduced interference suppression scheme is proposed for DS-CDMA systems over multipath channels. The proposed receiver resolves the problems of interference and multipath effects without needing to estimate the channel and training sequences. The minimum mean squared error (MMSE) criterion is used to obtain an algorithm to cancel the interference of each path. The MMSE filter is composed of two stages based on multipath effects. The proposed receiver has low complexity without great degradation of performance compared with the full dimension MMSE receiver with known channel information. Simulation results show that the proposed receiver converges to the optimal value rapidly because of its reduced dimension.

Sophisticated and robust resource management is an essential issue in future wireless systems which will provide a variety of application services. In this paper, we employ an adaptive-network-based fuzzy inference system (ANFIS) to control the resource allocation for mobile multimedia networks. ANFIS, possessing the advantages of expert knowledge of fuzzy logic system and learning capability of neural networks, can provide a systematic approach to finding appropriate parameters for the Sugeno fuzzy model. The fuzzy resource allocation controller (FRAC) is designed in a two-layer architecture and selects properly the capacity requirement of new call request, the capacity reservation for future handoffs, and the air interface performance as input linguistic variables. Therefore, the statistical multiplexing gain of mobile multimedia networks can be maximized in the FRAC. Simulation results indicate that the proposed FRAC can keep the handoff call blocking rate low without jeopardizing the new call blocking rate. Also, the FRAC can indeed guarantee quality of service (QoS) contracts and achieve higher system performance according to network dynamics, compared with the guard channel scheme and ExpectedMax strategy.

A fully on-chip active guard band circuit is proposed. The proposed circuit is mainly composed of current mirrors and based on a DC bias technique. HSPICE simulations and experiment results confirm the validity of the proposed active guard band circuit.

Much has been said and written about the changes in analog IC technology such as shrinking line widths, vanishingly low supply voltages, severe power limitations, and digital noise. But beyond these technology changes and their subsequent methodology changes, a far more subtle revolution is happening in the nature of the profession itself. Technology, software, and product evolution have all conspired to create a new kind of analog IC designer, one very different from the IC designers of the past.

In this paper, we propose a novel architecture for low-power direct-mapped instruction caches, called "history-based tag-comparison (HBTC) cache. " The cache attempts to reuse tag-comparison results for avoiding unnecessary tag checks. Execution footprints are recorded into an extended BTB (Branch Target Buffer). In our evaluation, it is observed that the energy for tag comparison can be reduced by more than 90% in many applications.

This paper proposes list Viterbi equalizers (LVEs) that use two kinds of metric criteria for wide-spread time-dispersive channels to achieve a good trade-off between complexity and bit error rate (BER) performance. For Viterbi equalization employing a state-reduction algorithm, the modified metric criterion proposed by Ungerboeck is not always equivalent to the squared Euclidean distance metric criterion. This paper proposes the following two schemes for the LVE: (1) to combine two kinds of metric criteria like combining diversity; (2) to select the metric criterion like selection diversity according to the channel impulse response. Finally, computer simulation shows that the proposed schemes improve BER performance on wide-spread frequency selective fading channels, even if the proposed schemes have smaller complexity than the conventional one.

A fast, low-power 16-bit adder, 32-word register file and 512-bit cache SRAM have been developed using 0.25-µm GaAs HEMT technology for future multi-GHz processors. The 16-bit adder, which uses a negative logic binary look-ahead carry structure based on NOR gates, operates at the maximum clock frequency of 1.67 GHz and consumes 134.4 mW at a supply voltage of 0.6 V. The active area is 1.6 mm2 and there are about 1,230 FETs. A new DC/DC level converter has been developed for use in high-speed, low-power storage circuits such as SRAMs and register files. The level converter can increase the DC voltage, which is supplied to an active-load circuit on request, or supply a minimal DC voltage to a load circuit in the stand-by mode. The power dissipation (P) of the 32-word register file with on-chip DC/DC level converters is 459 mW, a reduction to 25.2% of that of an equivalent conventional register file, while the operating frequency (fc) was 5.17 GHz that is 74.8% of fc for the conventional register file. P for the 512-bit cache SRAM with the new DC/DC level converters is 34.3 mW, 89.7% of the value for an equivalent conventional cache SRAM, with the read-access time of 455 psec, only 1.1% longer than that of the conventional cache SRAM.

A new logic-in-memory circuit is proposed for a fine-grain pipelined VLSI system. Dynamic-storage elements are distributed over a logic-circuit plane. A functional pass gate is a key component, where a linear summation and threshold function are merged compactly using charge-storage and charge-coupling effect with a DRAM-cell-based circuit structure. The use of dynamic logic based on pass-transistor network using functional pass gates makes it possible to realize any logic circuits compactly with small power dissipation. As a typical example, a 54-bit pipelined multiplier is implemented by using the proposed circuit technology. Its power dissipation and chip area are reduced to about 63 percent and 72 percent, respectively, in comparison with those of a corresponding binary CMOS implementation under 0.35-µm CMOS technology.

In this paper, we propose a probabilistic approach to derive an approximate polyhedral description from range data. We first compare several least-squares-based methods for estimation of local normal vectors and select the most robust one based on a reasonable noise model of the range data. Second, we extract the stable planar regions from the range data by examining the distributions of the local normal vectors together with their spatial information in the 2D range image. Instead of segmenting the range data completely, we use only the geometries of the extracted stable planar regions to derive a polyhedral description of the range data. The curved surfaces in the range data are approximated by their extracted plane patches. With a probabilistic approach, the proposed method can be expected to be robust against the noise. Experimental results on real range data from different sources show the effectiveness of the proposed method.

We introduce PC Linux cluster computing techniques to an Evolutionary Graph Generation (EGG) system, and successfully implement the parallel version of the EGG system, called PEGG. Our survey satisfactorily shows that the parallel evolutionary approach meets our expectation that the final solutions obtained from PEGG will be as good as or better than those obtained from EGG, and that PEGG can ultimately improve the speed of evolution.

The power supply voltage of LSI has been lowered due to system requirements for low power dissipation. An on-chip power-on reset pulse generator (POR-PG) is used to determine the initial state of the memory devices of the system LSI. The requirement for the POR-PG is strict for lower power supply voltage because noise margin is smaller relatively. This paper describes a POR-PG for low power voltage supply (Vdd) which overcomes these problems. Hardware measurement proves improved pulse height relative to various power-on profiles (slope, rise time etc.) and fluctuations of temperature and process. Further, the design provides robust noise immunity against voltage fluctuations on the power supply line. The circuit is implemented within a small area (115 µm 345 µm) in the input/output buffer area of a micro-processor and hard-disk controller integrated LSI with 0.25-µm four-layer-metal CMOS technology.

The jitter characteristics of synchronous residual time stamp (SRTS) method used in ATM adaptation layer type 1 (AAL1) are analyzed. In this letter, the root mean square amplitude of filtered SRTS jitter is calculated and the computer simulation has been carried out to show jitter of SRTS method considering also the phase time error of network clocks.

A 1.6-Tb/s dense WDM signal was successfully transmitted over 480 km using the carrier-suppressed return-to-zero (CS-RZ) modulation format. The CS-RZ format was chosen because it exhibited better transmission performance over a wide fiber-input power window than the NRZ and RZ formats in a 40-Gb/s-based WDM transmission experiment with 100-GHz channel spacing, confirming its nonlinearity-insensitive nature in dense WDM systems. With the wide power window of CS-RZ, we achieved stable transmission of 4040-Gb/s WDM signals over a 480-km (680 km) standard SMF line with only the C-band, in which a spectral ripple remained during transmission. Distributed Raman amplification and forward error correction were not used, providing a margin for already installed transmission lines.

It has been shown that virtual output queuing (VOQ) and a sophisticated scheduling algorithm enable an input-queued switch to achieve 100% throughput for independent arrival process. Several of the scheduling algorithms that have been proposed can be classified as either iterative scheduling algorithms or symmetric crossbar arbitration algorithms. i-OCF (oldest-cell-first) and TSA (two step arbiter) are well-known examples of iterative scheduling algorithms and symmetric crossbar arbitration algorithms, respectively. However, there are drawbacks in using these algorithms. i-OCF takes long time to find completely a conflict-free match between input ports and output ports because it requires multiple iterations. If i-OCF cannot find a conflict-free match completely, the switch throughput falls. TSA has the possibility that it finds a conflict-free match faster than i-OCF because it does not need any iterations. However, TSA suffers from the starvation problem. In this paper, we propose a new scheduling algorithm. It uses two schedulers, which we call scheduler 1 and scheduler 2, in parallel. After cells were transmitted, the information that input port i granted the offer from output port j in scheduler 2 is mapped to scheduler 1 if and only if input port i has at least one cell destined for output port j. If the information is moved, input port i and output port j are matched in scheduler 1 at the beginning of the next time slot. Our proposed algorithm uses one scheduler based on TSA and the other scheduler based on i-OCF. Numerical results show that the proposed scheduling algorithm does not require multiple iterations to find a conflict-free match completely and suffer from the starvation problem for both uniform and bursty traffic.

This paper proposes a statistical design approach for Non-Return-to-Zero (NRZ) 40 Gbit/s systems with Forward Error Correction (FEC); the approach considers Polarization Mode Dispersion (PMD). We introduce a fluctuating PMD emulator to experimentally clarify FEC performance in PMD-limited systems. By using the proposed design approach, and considering the FEC relaxation effect on PMD, the maximum transmission distance of an NRZ 40 Gbit/s system without PMD compensation is estimated as several hundreds of km depending on the number of cable concatenations per link and the probability threshold of system acceptance.

Methodologies for more efficient Raman amplification and a more suitable modulation format for 40 Gbit/s WDM unrepeatered transmission are investigated. Management of the fiber effective area is proposed to realize low noise distributed Raman amplification. An Aeff management technique in which low-Aeff fiber is located in a median section instead of the last section, was confirmed numerically and experimentally to improve the OSNR and Q-factor. Carrier-suppressed-return-to-zero (CS-RZ) modulation has the advantage of reducing fiber-nonlinearity effects and permitting denser multiplexing of the wavelengths. 40 Gbit/s 32-channel unrepeatered WDM transmission over 202 km was demonstrated employing the proposed methodologies.