This paper presents an application-specific, heterogeneous multiprocessor synthesis system, named HeMPS, that combines a form of Evolutionary Computation known as Differential Evolution with a scheduling heuristic to search the design space efficiently. We demonstrate the effectiveness of our technique by comparing it to similar existing systems. The proposed strategy is shown to be faster than recent systems on large problems while providing equivalent or improved final solutions.

Transmission and distribution systems are investigated for application in future fiber optic super-broadband and super-multi-channel subscriber loops. Gradual upgrading is considered so that future systems can keep compatibility with existing systems. First, time frame and strategies for subscriber loop upgrade are overviewed and assumptions for evolution of broadband multimedia distribution systems are discussed. It is suggested that upgrading to super-high definition (SHD) quality multimedia is desirable. Next, some examples of extra-auxiliary picture (EAP) formats are discussed to show the possibility of improving upgradability and compatibility by using extra-channels. Then multiplexing and channel selecting systems are investigated for economical realization of super-multi-channel distribution and flexible channel selection, and hybrid multiplexing (HMUX) and a trans-selector (T-SEL) are proposed. Finally, the efficiencies of HMUX and T-SEL are discussed by using numerical examples. Although broadband down streams are mainly considered, other streams such as IP traffics can be accommodated in the distribution systems investigated in this paper.

This paper proposes iterative demodulation/decoding for parallel combinatorial spread spectrum (PC/SS) systems. A PC/SS system conveys information data by a combination of pre-assigned orthogonal spreading sequences with polarity. In this paper, convolutional coding with a uniform random interleaver is implemented in channel coding, just like as a serial concatenated coding. A 'soft-in/soft-out' PC/SS demodulator based on a posteriori probability algorithm is proposed to perform the iterative demodulation and decoding. Simulation results demonstrate that the proposed iterative demodulation/decoding scheme bring significant improvement in bit error rate performance. This proposed decoding scheme achieves high-speed transmission by two approaches. One is a puncturing operation, and the other is to increase the number of transmitting sequences. In the latter approach, lower error rate performance is achieved comparing with that the punctured convolutional code is used to increase the information bit rate.

We summarize recent studies on performance improvement in the correlation-based continuous-wave technique for optical fiber distributed strain measurement using Brillouin scattering, that had been proposed previously. The correlation-based technique enables the spatial resolution of 1 cm, which is difficult for conventional sensing techniques using Brillouin scattering to achieve. Though the correlation-based technique left a problem with measurement range, we have proposed methods to overcome it with keeping high spatial resolution. In addition, we verified usefulness of the technique for smart materials by measuring strain distribution along surface of a ring structure.

Telepresentations will be popular in the future of ubiquitous digital media. To realize a telepresentation easily over the Internet, we design a communication protocol to control a remote material (digital media) used in a telepresentation. We describe our proposed protocol; RMOP (Remote Material Operation Protocol) in this paper. This protocol specifies commands for material operations such as synchronization of slides, drawing, and pointing. Since this protocol just specifies the common formats through IP networks independent of special functions of presentation tools, it can be applied to various presentation tools. To design the protocol, we consider the trade-off between reliability of IP multicast and practical availability in the actual Internet. We adopt the reliable multicast mechanism to improve reliability but not to lose practicality in the protocol. Also, we describe an implementation of our prototype system using RMOP for a telepresentation. Then we show some evaluations such as the protocol overhead and comparisons with the other existing systems. Last, we show a case study of a telepresentation over the Internet using our system.

As a new category of the optical application system integrated with electronics, the opto-electronic information system (OEIS) is presented. Combination of the different characteristic technologies, optics and electronics, is expected to be useful for development of an effective and high-performance information systems. The properties of the optical technologies such as parallelism, high-speed, and large information capacity can be utilized for information processing. Even if some of the functions are emulated by the electronics, the optics give more effective solutions. To implement the OEIS, various optoelectronic devices and fabrication technologies are available including vertical cavity surface emitting lasers and spatial light modulators. There are two forms of system construction for the OEIS: an application of optics to an electronic-based system and the reversed form. As examples of the OEIS, the parallel matching architecture (PMA) and the thin observation module by bound optics (TOMBO) are presented. The PMA is an architecture of parallel computing system specified for global processing. This architecture shows a typical strategy to utilize the optical interconnection capability with flexibility of the electronic technology. The TOMBO presents possibility of morphological conversion using combination of the optical and electronic technologies. A compound-eye imaging system and post digital processing enable us to realize a very thin image capturing system. The issues related on development of the OEIS are proper usage of optics, effective fusion of the optical and electronic technologies, methodologies for system construction, fabrication supporting tools, and development of attractive demonstrators other than communication and interconnection fields.

This paper presents a new approach to shape and motion estimation based on geometric primitives and relations in a model-based framework. A description of a scene in terms of structured geometric elements sharing relationships allows to derive a parametric model with Euclidian constraints, and a camera model is also proposed to reduce the problem dimensionality. It leads to a sequential MAP estimation, that gives accurate and comprehensible results on real images.

Partially depleted SOI technology with body-tied hybrid trench isolation was developed in order to counteract floating body effects which offers negative impact on the drive current of transistors and the stability of circuit operation while maintaining SOI's specific merits such as high speed operation and low power consumption. The feasibility of this technology and its superior soft error effects were demonstrated by a fully functional 4M-bit SRAM. Its radio frequency characteristics were also evaluated and it was verified that high-performance transistors and passive elements can be realized by the combination of the SOI structure and a high-resistivity substrate. Moreover, its application to a 2.5 GHz digital IC for optical communication was also demonstrated. Thus it was proven that the body-tied SOI devices with the hybrid trench isolation is suitable to realize intelligent and reliable high-speed system-on-a chip integrating various IP's.

In order to assess the possible impacts of meteors with spacecraft, which is among major hazard in the space environment, it is essential to establish an accurate statistics of their mass and velocity. We developed a radar-optical combined system for detecting faint meteors consisting of a powerful VHF Doppler radar and an ICCD video camera. The Doppler pulse compression scheme is used to enhance the S/N ratio of the radar echoes with very large Doppler shifts, as well as to determine their range with a resolution of 200 m. A very high sensitivity of more than 14 magnitude and 9 magnitude for radar and optical sensors, respectively, has been obtained. Instantaneous direction of meteor body observed by the radar is determined with the interferometry technique. We examined the optimum way of the receiving antenna arrangements, and also of the signal processing. Its absolute accuracy was confirmed by the optical observations with background stars as a reference. By combining the impinging velocity of meteor bodies derived by the radar with the absolute visual magnitude determined by the video camera simultaneously, the mass of each meteor body was estimated. The developed observation system will be used to create a valuable data base of the mass and velocity information of faint meteors, on which very little is known so far. The data base is expected to play a vital role in our understanding of the space environment needed for designing large space structures.

Complex-valued region-based-coupling image clustering (continuous soft segmentation) neural networks are proposed for interferometric radar image processing. They deal with the amplitude and phase information of radar data as a combined complex-amplitude image. Thereby, not only the reflectance but also the distance (optical length) are consistently taken into account for the clustering process. A continuous complex-valued label is employed whose structure is the same as that of input raw data and estimation image. Experiments demonstrate successfully the clustering operations for interferometric synthetic aperture radar (InSAR) images. The method is applicable also to future radar systems for image acquisition in, e.g., invisible fire smoke places and intelligent transportation systems by generating a processed image more recognizable by human and automatic recognition machine.

This paper describes performance enhancement of high-resolved delay time estimation by pattern diversity of wheel-shaped dipole antennas for the MUSIC algorithm. We propose that the wheel-shaped dipole antennas are used to average covariance matrices weightedly with their pattern diversity without decreasing the matrix dimension and to obtain freedom of selecting sweeping frequencies. It is numerically confirmed that the wheel-shaped dipole antennas can be used to enhance capability of the delay time estimation.

The concept of stochastic association has originally been proposed in relation to single-electron devices having stochastic behavior due to quantum effects. Stochastic association is one of the promising concepts for future VLSI systems that exceed the conventional digital systems based on deterministic operation. This paper proposes a CMOS stochastic associative processor using PWM (pulse-width modulation) chaotic signals. The processor stochastically extracts one of the stored binary patterns depending on the order of similarity to the input. We confirms stochastic associative processing operation by experiments for digit pattern association using the CMOS test chip.

In the present GHz-clock high-density LSI, a design of signal lines is getting so critical that the transmission line analysis should be introduced to signal line design. This leads to the complex design of line structure and i/o drivers including impedance matching. Our target is to implement a system-in-package (SiP) for software-defined-radio (SDR). The SiP operates up to 10 GHz, and requires a compact and high-density packaging technology with a simple signal wiring design. In this paper, we propose a new concept of 3-D multilayer-stacked SiP. The new 3-D packaging concept includes (1) design guideline for interconnection lengths, (2) bridging register circuits in LSI chips, (3) flip-chip microbump bonding technology of chips onto system-buildup printed wiring boards (PWB), (4) multilayer-stacked 3-D package of several sets of chips and PWB, and (5) 100-µm-diameter bumps at peripheral region of PWB as vertical via-bump bus lines. A critical interconnect length, in which interconnect wiring is treated as a conventional RC line, is discussed for wiring design. Both wiring lengths in LSI chips and that among chips corresponding to total thickness of vertical bus lines are designed to be shorter than the critical length. The key points of the 3-D package for GHz signal transfer are a delay guarantee due to limitation of line length and separation between local lines in a chip and a bus line among chips.

We propose the kernel-based pattern recognition hardware and its design methodology using the genetic algorithm. In the proposed design methodology, pattern data are transformed into the truth tables and the truth tables are evolved to represent kernels in the discrimination functions for pattern recognition. The evolved truth tables are then synthesized to logic circuits. Because of this data direct implementation approach, no floating point numerical circuits are required and the intrinsic parallelism in the pattern data set is embedded into the circuits. Consequently, high speed recognition systems can be realized with acceptable small circuit size. We have applied this methodology to the image recognition and the sonar spectrum recognition tasks, and implemented them onto the newly developed FPGA-based reconfigurable pattern recognition board. The developed system demonstrates higher recognition accuracy and much faster processing speed than the conventional approaches.

Available statistical skew models are too conservative in estimating the expected clock skew of a well-balanced H-tree. New closed form expressions are presented for accurately estimating the expected values and the variances of both the clock skew and the largest clock delay of a well-balanced H-tree. Based on the new model, clock period optimizations of wafer scale H-tree clock network are investigated under both conventional clocking mode and pipelined clocking mode. It is found that when the conventional clocking mode is used, clock period optimization of wafer scale H-tree is reduced to the minimization of expected largest clock delay under both area restriction and power restriction. On the other hand, when the pipelined clocking mode is considered, the optimization is reduced to the minimization of expected clock skew under power restriction. The results obtained in this paper are very useful in the optimization design of wafer scale H-tree clock distribution networks.

As LSIs are two-dimensional structures, the number of external pins increases at a lower rate than the corresponding increase in the number of gates on the LSI. Therefore, the number of flip-flops on a scan path increases as the density of gates on LSIs rises, resulting in longer test application times. In this paper, three novel DFT strategies aimed at reducing test application time are proposed. DFT strategy 1 is a full scan design method with test point insertion, DFT strategy 2 is a partial scan design method, and DFT strategy 3 is a partial scan design method with test point insertion. Experimental results show that these DFT strategies reduced the test application times by 45% to 82% compared with conventional full scan design methods.

This paper presents an enhancement of a software project simulator to perform risk prediction with cost estimation capability. So far, we have developed a software project simulator to simulate software development projects. In this simulator, a development process was described using Petri net model, and it was applied to some actual project data in a certain company successfully. On the other hand, we have also presented a risk predicting system to find "risky" projects by statistical analysis on risk questionnaire for project managers. In this approach, only the probability to be risky was calculated for a project. Thus, the managers in the company wanted to know a concrete proof why a software project becomes risky. In this paper, to present the proof that a software project becomes risky, we try to enhance the previous project simulator so that the simulator can deal with risk factors. To consider the risk factors, we modify the previous simulator so that both the fluctuation of skill level and the deadline pressure can be represented by the parameters in the simulator. By using a case study, we confirm that the enhanced simulator can estimate the development cost under some typical risks. As a result, we can expect that the simulator shows how much the development cost of a risky project exceeds an estimate.

This paper describes a new architecture-based microprocessor, a dynamically programmable parallel processor (DPPP), that consists of large numbers of simplified ALUs (sALU) as processing blocks. All sALUs are interconnected via a code division multiple-access bus interface that provides complete routing flexibility by establishing connections virtually through code-matching instead of physical wires. This feature is utilized further to achieve high parallelism and fault tolerance. High fault tolerance is realized without the limitations of conventional fabrication-based techniques nor providing spare elements. Another feature of the DPPP is its simple programmability, as it can be configured by compiling numerical formula input using the provided user auto-program interface. A prototype chip based on the proposed architecture has been implemented on a 4.5 mm 4.5 mm chip using 0.6 µm CMOS process.

In this paper we propose a MIN (Multistage Interconnection Network) whose performance in the faulty case degrades as gracefully as possible. We focus on a two-dilated baseline network as a sort of MIN. The link connection pattern in our MIN is determined so that all the available paths established between an input terminal and an output terminal via an identical input of a SE (Switching Element) in some stage will never pass through an identical SE in the next stage. Extra links are useful in improving the performance of the MIN and do not complicate the routing scheme. There is no difference between our MIN and others constructed from a baseline network with regard to numbers of links and cross points in all SEs. The theoretical computation and simulation-based study show that our MIN is superior to others in performance, especially in robustness against concentrated SE faults in an identical stage.

Recently, an efficient algorithm has been proposed for finding all solutions of systems of nonlinear equations using inverses of approximate Jacobian matrices. In this letter, an effective technique is proposed for improving the computational efficiency of the algorithm with a little bit of computational effort.