A multiport representation of the step junction of two circular dielectric waveguides of different size is given. Continuous spectral modes of the circular dielectric waveguide are discretized at a terminal plane by means of expressing their mode amplitudes in the form of infinite series of orthonormal Gaussian Laguerre function. Applying the mode matching technique, a multiport representation of the step junction is derived. Numerical examples are given where the results are tested for the conservation of power. Also the numerical results are compared with those from Marcuse's approximate methods.

Hardware/software partitioning is one of the key processes in a hardware/software cosynthesis system for digital signal processor cores. In hardware/software partitioning, area and delay estimation of a processor core plays an important role since the hardware/software partitioning process must determine which part of a processor core should be realized by hardware units and which part should be realized by a sequence of instructions based on execution time of an input application program and area of a synthesized processor core. This paper proposes area and delay estimation equations for digital signal processor cores. For area estimation, we show that total area for a processor core can be derived from the sum of area for a processor kernel and area for additional hardware units. Area for a processor kernel can be mainly obtained by minimum area for a processor kernel and overheads for adding hardware units and registers. Area for a hardware unit can be mainly obtained by its type and operation bit width. For delay estimation, we show that critical path delay for a processor core can be derived from the delay of a hardware unit which is on the critical path in the processor core. Experimental results demonstrate that errors of area estimation are less than 2% and errors of delay estimation are less than 2 ns when comparing estimated area and delay with logic-synthesized area and delay.

Reactive sputtering of a metallic target in DC planar magnetron discharge shows a drastic mode transition between metallic and oxide modes. To describe the experimental results quantitatively, a new reactive sputtering model including the secondary electron emission coefficient of a target has been developed. The model is based on a simple reactive gas balance model proposed by Berg et al., and can quantitatively describe experimental results such as the oxygen flow rate dependence of deposition rate and discharge, observed for MgO sputter-deposition.

In this letter, blind adaptive H multiuser detection is developed by employing a generalized sidelobe canceler (GSC) with and without subweight partition scheme. It is shown that the adaptive H algorithm with subweight approach has the advantages of fast convergence speed, insensitivity of dynamic estimate error, and suitability for arbitrary ambient noise over the conventional H and the RLS-based adaptive algorithms.

We present a simple cell scheduling algorithm for an input buffered switch. The suggested algorithm is based on iSLIP and consists of request, grant and accept steps. The pointer update scheme of iSLIP is simplified in the suggested algorithm. By virtue of the new update scheme, the performance of the suggested algorithm is better than that of iSLIP with one iteration. Using computer simulations under a uniform traffic, we show the suggested algorithm is more appropriate than iSLIP for scheduling of an input buffered switch with multiple service classes.

We propose a timing driven gate duplication algorithm for the technology independent phase. Our algorithm is a generalization of the gate duplication strategy suggested in [3]. Our technique gets a more global view by duplicating multiple gates at a time. We compare the minimum circuit delay obtained by SIS with the delay obtained by using our gate duplication. Results show that up to 11% improvement in delay can be obtained. Our algorithm does not have an adverse effect on the overall synthesis time, indicating that gate duplication is an efficient strategy for timing optimization.

This paper presents an intelligent routing algorithm, called Q-Agents, which bases its actions only on the agent-environment interaction. This algorithm combines properties of three learning strategies (Q-learning, dual reinforcement learning and learning based on ant colony behavior), adding to them two further mechanisms to improve its adaptability. Hence, the proposed algorithm is composed of a set of agents, moving through the network independently and concurrently, searching for the best routes. The agents share knowledge about the quality of the paths traversed through indirect communication. Information about the network and traffic status is updated by using Q-learning and dual reinforcement updating rules. Q-Agents were applied to a model of an AT&T circuit-switched network. Experiments were carried out on the performance of the algorithm under variations of traffic patterns, load level and topology, and with addition of noise in the information used to route calls. Q-Agents suffered a lower number of lost calls than two algorithms based entirely on ant colony behavior.

An adaptive rate communication system based on the N-MSK modulation technique is described. Two examples of the system using a 2-MSK adaptive modulation scheme and a 4-MSK adaptive modulation scheme are presented and analysed in slow fading channel. The channel attenuation obeys either Rayleigh or lognormal distribution. The proposed adaptive rate communication system is able to track slow variations of channel attenuation and the average system throughput is therefore increased at a given BER.

In this paper, we consider the subchannel detection problem in forward links for the multicarrier DS-CDMA system when some different subchannel allocation policies are used. An optimal subchannel decision algorithm is proposed based on the maximum-likelihood (ML) criterion. Theoretical analysis and simulation results are presented. Furthermore, we discuss the parameter selection problem on the length of the training sequences in the subchannel allocation scheme in [8],[12] by using the proposed ML detection algorithm. The results show that the subchannel allocation scheme in [8],[12] is feasible since only a few symbols overhead is required.

This paper proposes an automatic dispersion equalization system using extracted clock power monitoring in order to facilitate the field installation of high-speed time-division multiplexed (TDM) systems over existing fiber cables. The proposed scheme adjusts the dispersion of a variable-dispersion equalizer so as to maximize the extracted clock power level. This scheme has a simple configuration, needs no communication channel between the transmitter and the receiver, and is sensitive to parameters such as initial chirping and fiber input power. The clock power dependence on the fiber dispersion is theoretically analyzed assuming that the return-to-zero (RZ) format is used and that pulse broadening is small compared to the bit duration. We show that the clock power is maximized when the dispersion-induced waveform distortion is minimized. Numerical simulations show that the proposed scheme is effective with the non-return-to-zero (NRZ) format and for the case that the optimum total dispersion deviates from zero due to initial and/or self-phase modulation (SPM)-induced chirping. The operation of the proposed automatic equalization system is experimentally confirmed in 20-Gbit/s transmission using both RZ and NRZ formats. Moreover, a 40-Gbit/s transmission experiment over 200 km of dispersion-shifted fiber (DSF) is successfully demonstrated using the proposed equalization scheme.

In this paper, we present a design for an optical video transmission system employing a super wide-band FM modulation scheme. We focus on the design of optical transmitters and receivers, especially a wide-band electrical-to-optical converter and optical-to-electrical converter. With this system, it is important to develop optical and microwave devices which have a wide frequency response combined with flat group delay characteristics in order to improve the quality of the video signals after transmission. We also analyze theoretically the hybrid transmission capacity of AM analog video signals and 64QAM signals for digital video and data, and show the FM modulation parameters needed to realize high quality transmission. An experimental evaluation shows that our designed optical transmitter and receiver achieve high quality for the various channel plans for AM/64QAM hybrid transmission. The system has high received optical sensitivity and a wide optical dynamic range, allowing it to distribute analog video, digital video, and Internet data to many users over a wide area.

This paper proposes the Vector Evaluated GA-ICT (VEGA-ICT), a novel design method that employs the Genetic Algorithm (GA) to obtain the optimum antenna design. GA-ICT incorporates an arbitrary wire-grid model antenna to derive the optimum solution without any basic structure or limitation on the number of elements by merely optimizing an objective function. GA-ICT comprises the GA and an analysis method, the Improved Circuit Theory (ICT), with the following characteristics. (1) To achieve optimization of an arbitrary wire-grid model antenna without a basic antenna structure, the unknowns of the ICT are directly assigned to variables of the GA in the GA-ICT. (2) To achieve a variable number of elements, duplicate elements generated by using the same feasible region are deleted in the ICT. (3) To satisfy all complex design conditions, the GA-ICT generates an objective function using a weighting function generated based on electrical characteristics, antenna configuration, and size. (4) To overcome the difficulty of convergence caused by the nonlinearity of each term in the objective function, GA-ICT adopts a vector evaluation method. In this paper, the novel GA-ICT method is applied to downsize sector antennas. The calculation region in GA-ICT is reduced by adopting cylindrical coordinates and a periodic imaging structure. The GA-ICT achieves a 30% reduction in size compared to the previously reported small sector antenna, MS-MPYA, while retaining almost the same characteristics.

The IEEE 1394 is a standard for the high performance serial bus interface. This standard has the isochronous transfer mode that is suitable for real-time applications and the asynchronous transfer mode for delay-insensitive applications. It can be used to construct a small-size local area network. We propose a queueing model for a network with this standard under some assumptions, and calculate the average waiting time of an asynchronous packet in the buffer in the steady state. We give some numerical results, along with validation by simulation, in order to evaluate its performance.

A distributed network management system (NMS) is urgently needed to manage large number of network managed objects (MOs) such as public network MOs. The ATM Forum has proposed the M4-interface to achieve just such a distributed NMS. However, the basis of the M4-interface is not adequate in terms of flexible distribution, because its main unit of distribution is location. To improve the granularity of the distribution, we have defined the route as a further unit of distribution. We also describe new MOs that provide for a distribution based on routes. A more detailed distribution is then possible than with a distribution purely based on location. In addition, we propose a new CMIP Action to move MOs from one sub-NMS (SubNMS) to another while the system is running. Using this Action, we can achieve a more flexible distribution in terms of network problems and load.

A multi-grid finite-difference time-domain (FDTD) method was applied for numerical dosimetry analysis in the human head for 5 GHz band portable terminals. By applying fine FDTD grids to the volumes in the human head where the highest electromagnetic (EM) absorption occurs and coarse grids to the remaining volumes of the head, the spatial peak specific absorption rate (SAR) assessment was achieved with a less computation memory and time. The accuracy of applying the multi-grid FDTD method to the spatial peak SAR assessment was checked in comparison with the results obtained from the usual uniform-grid method, and then the spatial peak SARs for three typical situations of a person using a 5.2 GHz band portable terminal were calculated in conjunction with an anatomically based human head model.

This paper investigates a device model of the power current used for an LSI/IC. The model is proposed to analyze the power bus noise in digital circuit boards. This model is defined in the frequency domain and constructed with an equivalent internal impedance and an equivalent internal current source. Accordingly, the output current of the model is affected by power bus impedance, such as the capacitance of bypass capacitors and the parasitic inductance of power bus wiring. Therefore, the model is useful for analyzing the effectiveness of bypass capacitors and power bus wiring. The structure of equivalent internal impedance for a simple logic IC, such as 74HCXX, can be represented as an RLC series circuit. These parameters are identified by applying the least square method. To demonstrate the validity of the model, an experimental study was conducted. As a result, it was shown that the output current of the model corresponds to the measured current under a variety of power bus impedance levels within 6 dB.

We present a new technique for hierarchical intellectual property (IP) protection using partially-mergeable cores. The proposed core partitioning technique guarantees 100% protection of critical-IP, while simplifying test generation for the logic that is merged with the system. Since critical-IP is tested using BIST, the controllability and observability of internal lines in the core are enhanced, and test application time is reduced. Case studies using the ISIT-DLX and Picojava processor cores demonstrate the applicability of our technique.

In this paper, we present an RTL design-space exploration method for high-level applications. We formulate the RTL design-space exploration into a performance-driven module selection problem. We devise a dynamic-programming algorithm to solve the problem. We present an exploration flow by integrating commercial synthesis and layout tools with our proposed method. Experimental results have demonstrated that generating AT-curve for all modules is the most time consuming task in the design-space exploration process. Using the proposed 3-point AT projection approach, our method can achieve on an average of 80% speed-up in run time and 90% accuracy in design estimation.

External pins for tests are precious hardware resources because this number is strongly restricted. Cores are tested via test access mechanisms (TAMs) such as a test bus architecture. When cores are tested via test buses which have constant bit widths, test stimuli and test responses for a particular core have to be transported over these test buses. The core might require more widths for input and output than test buses, and hence, for some part of the test, the TAMs are idle; this is a wasteful usage of the TAMs. In this paper, an optimization method of test accesses with a combined BIST and external test (CBET) scheme is proposed for eliminating the wasteful usage of test buses. This method can minimize the test time and eliminate the wasteful usage of external pins by considering the trade-off between test time and the number of external pins. Our idea consists of two parts. One is to determine the optimum groups, each of which consists of cores, to simultaneously share mechanisms for the external test. The other is to determine the optimum bandwidth of the external input and output for the external test. Our idea is basically formulated for the purpose of eliminating the wasteful external pin usage. We make the external test part to be under the full bandwidth of external pins by considering the trade-off between the test time and the number of external pins. This is achieved only with the CBET scheme because it permits test sets for both the BIST and the external test to be elastic. Taking test bus architecture as an example, a formulation for test access optimization and experimental results are shown. Experimental results reveal that our optimization can achieve a 51.9% reduction in the test time of conventional test scheduling and our proposals are confirmed to be effective in reducing the test time of system-on-a-chip.

In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such that a clock-input timing of each register is a multiple of a predefined unit delay and the wire length from a clock buffer to an element driven by it is bounded. The clock trees are constructed for several practical circuits. The size of constructed clock tree is comparable to a zero skew clock tree. In order to assure the practical quality of the clock trees, they are examined under the five delay conditions, which cover various environmental and manufacturing conditions. As a result, they are proved stable under each condition and improve the clock speed up to 17.3% against the zero skew clock trees.