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24181-24200hit(30728hit)

  • An Evaluation of the Physiological Effects of CRT Displays on Computer Users

    Sufang CHEN  Xiangshi REN  HunSoo KIM  Yoshio MACHI  

     
    PAPER-General Fundamentals and Boundaries

      Vol:
    E83-A No:8
      Page(s):
    1713-1719

    An experiment was conducted to measure and compare the physiological effects of three types of CRT on users. We proposed a new strategy for measuring the user's level of relaxation. In this strategy, called "Task Break Monitoring (TBM)," the subjects took a break with eyes closed after each interaction with the computer. During each break, electroencephalogram (EEG), especially alpha 1 waves, electrocardiogram (ECG) and galvanic skin resistance (GSR) were monitored and recorded. The results show that the type of CRT display which emits far-infrared rays modulated by a FIR-fan induce less fatigue in users while they are working and reduce the recovery time after the task was completed. We believe "TBM" to be an important innovation in human computer research and development because the after effects of computer use have an obvious bearing on recovery time, user endurance and psychological attitude to the technology in general etc.

  • Adaptive Array Employing Eigenvector Beam of Maximum Eigenvalue and Fractionally-Spaced TDL with Real Tap

    Yasushi TAKATORI  Keizo CHO  Kentaro NISHIMORI  Toshikazu HORI  

     
    PAPER

      Vol:
    E83-B No:8
      Page(s):
    1678-1687

    This paper proposes a new digital beamforming adaptive array antenna (DBFAAA) that is effective in severe multipath environments in which timing and carrier synchronization circuits cannot function ideally resulting in the DBFAAA losing control. The proposed DBFAAA has two stages. In the first, the DBFAAA captures the desired signal and establishes synchronization. In the second, the DBFAAA optimizes the beam pattern of the signal. The proposed configuration employs an eigenvector beam of the maximum eigenvalue in the first stage beam-forming. In addition, a fractionally-spaced-tapped-delay-line (FS-TDL) with real tap weights, which is placed after the beam-former, is applied to achieve timing synchronization. The behavior of the proposed DBFAAA for asynchronous sampling data is investigated and the results indicate that the proposed configuration enables asynchronous sampling at the A/D converter. A prototype of the proposed DBFAAA achieving 38-Mbps real-time data communication is introduced and the transmission performance is shown.

  • Interconnect Modeling in Deep-Submicron Design

    Won-Young JUNG  Soo-Young OH  Jeong-Taek KONG  Keun-Ho LEE  

     
    INVITED PAPER-Circuit Applications

      Vol:
    E83-C No:8
      Page(s):
    1311-1316

    As scaling has been continued more than 20 years, it has yielded faster and denser chips with ever increasing functionality. The scaling will continue down to or beyond 0.1 µm as proposed in SIA Technical Road map. With scaling, device performance improves, however, interconnect performance is degraded. In this scaled deep submicron technology, however, interconnects limit the performance, packing density and yield, if not properly modeled. In order to properly model and design the interconnect-dominated circuits, accurate and proper interconnect modeling is a must to assure the performance and functionality of ever-increasing complex multi-million transistor VLSI circuits. In this paper, the overall flow of interconnect modeling in IC design is reviewed including interconnect characterization, various 2-D/3-D field solvers, 2-D/3-D interconnect model library generation, and parameter extraction. And advanced topics of interconnect modeling in deep submicron are reviewed; statistical interconnect modeling.

  • Fixed Channel Assignment Optimization for Cellular Mobile Networks

    Kwan L. YEUNG  Tak-Shing P. YUM  

     
    PAPER

      Vol:
    E83-B No:8
      Page(s):
    1783-1791

    The optimization of channel assignment in cellular mobile networks is an NP-complete combinatorial optimization problem. For any reasonable size network, only sub-optimal solutions can be obtained by heuristic algorithms. In this paper, six channel assignment heuristic algorithms are proposed and evaluated. They are the combinations of three channel assignment strategies and two cell ordering methods. What we found are (i) the node-color ordering of cells is a more efficient ordering method than the node-degree ordering; (ii) the frequency exhaustive strategy is more suitable for systems with highly non-uniformly distributed traffic, and the requirement exhaustive strategy is more suitable for systems with less non-uniformly distributed traffic; and (iii) the combined frequency and requirement exhaustive strategy with node-color re-ordering is the most efficient algorithm. The frequency spans obtained using the proposed algorithms are much lower than that reported in the literature, and in many cases are equal to the theoretical lower bounds.

  • Dynamic Power Dissipation of Track/Hold Circuit

    Hiroyuki SATO  Haruo KOBAYASHI  

     
    LETTER-Analog Signal Processing

      Vol:
    E83-A No:8
      Page(s):
    1728-1731

    This paper describes the formula for dynamic power dissipation of a track/hold circuit as a function of the input frequency, the input amplitude, the sampling frequency, the track/hold duty cycle, the power supply voltage and the hold capacitance for a sinusoidal input.

  • Weighted OFDM for Wireless Multipath Channels

    Homayoun NIKOOKAR  Ramjee PRASAD  

     
    PAPER

      Vol:
    E83-B No:8
      Page(s):
    1864-1872

    In this paper the novel method of "weighted OFDM" is addressed. Different types of weighting factors (including Rectangular, Bartlett, Gaussian, Raised cosine, Half-sin and Shanon) are considered. The impact of weighting of OFDM on the peak-to-average power ratio (PAPR) is investigated by means of simulation and is compared for the above mentioned weighting factors. Results show that by weighting of the OFDM signal the PAPR reduces. Bit error performance of weighted multicarrier transmission over a multipath channel is also investigated. Results indicate that there is a trade off between PAPR reduction and bit error performance degradation by weighting.

  • Diffusion Model for Multimedia and Mobile Traffic Based on Population Process for Active Users in a Micro-Cell

    Shin'ichiro SHINOMIYA  Masaki AIDA  Kazuyoshi SAITOH  Noriteru SHINAGAWA  Takehiko KOBAYASHI  

     
    PAPER

      Vol:
    E83-B No:8
      Page(s):
    1827-1833

    Recent development of compact and powerful portable computers and mobile phones and proliferation of the Internet will enable mobile multimedia communications. From the viewpoint of implementing multimedia services into mobile communications, it allows us to predict that traffic characteristics of mobile networks change. For planning, designing, and operating mobile multimedia networks, it is important to investigate traffic models which take the effect of multimedia services into consideration. This paper investigates population of active users in a micro-cell and proposes a traffic model for mobile multimedia networks. This model describes a population process of active users in a micro-cell in diffusion model, and its characteristics include self-similarity and activity of mobility. We also made an evaluation of network performance by using simulation, in order to show that characteristics of the proposed traffic model have impact on planning and designing networks.

  • Teletraffic Characteristics in Prioritized Handoff Control Method Considering Reattempt Calls

    Noriteru SHINAGAWA  Takehiko KOBAYASHI  Keisuke NAKANO  Masakazu SENGOKU  

     
    PAPER

      Vol:
    E83-B No:8
      Page(s):
    1810-1818

    When a mobile station with a call in progress moves across cell boundary in a cellular mobile communications system, the system must switch the circuit to the base station in the destination cell to enable uninterrupted communications in a process called "handoff. " However, if a circuit to the destination base station cannot be secured when a handoff is attempted, the call is forcibly terminated. Studies have therefore been performed on methods of decreasing the percentage of forcibly terminated calls by giving handoff calls priority. With the aim of simplifying system design, we propose a system for automatically setting the number of circuits reserved for handoff based on the handoff block rate. In this paper, we describe this system and evaluate static traffic characteristics taking into account reattempt calls, the occurrence of which can have a major effect on system performance. We also consider the effects of the proposed system on service quality since giving priority to handoff calls and decreasing the rate of forced terminations results in a tradeoff with the blocking rate of new call attempts. Finally, we evaluate the traffic characteristics associated with the number of control requests, an important element in estimating the processing capacity required by control equipment at the time of system design.

  • An Adaptive Radio Link Protocol for Efficient Packet Transmission in Infostation Systems

    Hua MAO  Gang WU  Michael F. CAGGIANO  James G. EVANS  

     
    PAPER

      Vol:
    E83-B No:8
      Page(s):
    1800-1809

    The Infostation concept has been proposed to provide convenient and cost effective access to high-speed mobile data services. An efficient IP packet transmission protocol is required to compensate for the high error rate inherent to fading radio channels. In this paper, a novel link layer retransmission scheme is proposed. Using the channel state and fading state estimators, the scheme adjusts the retransmission parameters dynamically in order to achieve the optimum performance under time-varying channel conditions. A theoretical analysis is presented for the case of a random error channel. Furthermore, a simulation tool is developed for evaluating the performance of the scheme in a fading channel with various parameters. The analysis and simulation results show that this new retransmission scheme can provide substantial improvement over traditional schemes. It gives a robust performance in both slow and fast fading conditions. In addition, the algorithm's sensitivity to parameter values and channel characteristics, such as Doppler frequency and fading statistics, is investigated. A unique attribute of this algorithm and performance analysis is that throughput is evaluated in IP packets rather than in physical layer packets.

  • A Spatial-Domain RAKE Receiver Using a Super-Resolution Technique

    Yasuhiko TANABE  Kenzaburoh FUJISHIMA  Yasutaka OGAWA  Takeo OHGANE  

     
    PAPER

      Vol:
    E83-B No:8
      Page(s):
    1664-1670

    In high-speed TDMA mobile communications, frequency-selective fading is a serious problem because a delay time difference between multipath signals is large in comparison with symbol duration. We have proposed a spatial-domain RAKE receiver using a multibeam adaptive antenna to reduce frequency-selective fading and to realize path-diversity. The multibeam adaptive antenna resolves multipath signals in the spatial domain, and combines array outputs. In this paper, we propose the application of MUSIC algorithm to estimation of the time delays of multipath signals to make the incident signals coincide with a common reference signal. Because the MUSIC algorithm can estimate the time delays accurately, the BER performance of the proposed scheme is improved. Furthermore, we propose weighting factors which easily realize the maximal-ratio combining.

  • A BSIM3v3 and DFIM Based Ferroelectric Field Effect Transistor Model

    Marc ULLMANN  Holger GOEBEL  Heinz HOENIGSCHMID  Thomas HANEDER  

     
    PAPER-Circuit Applications

      Vol:
    E83-C No:8
      Page(s):
    1324-1330

    A BSIM3v3 based ferroelectric memory field effect transistor (FEMFET) compact model for circuit simulation is presented. Its analytical approach is based on the MOS capacitor equations taking into account the influence of a ferroelectric polarization. The hysteresis behavior of the gate ferroelectric has been modeled by using the distribution function integral method (DFIM). The parameters for the presented simulations were extracted by measurements on MIS and MFIS structures.

  • Analysis of the Sign-Sign Algorithm Based on Gaussian Distributed Tap Weights

    Shin'ichi KOIKE  

     
    PAPER-Adaptive Signal Processing

      Vol:
    E83-A No:8
      Page(s):
    1551-1558

    In this paper, a new set of difference equations is derived for transient analysis of the convergence of adaptive FIR filters using the Sign-Sign Algorithm with Gaussian reference input and additive Gaussian noise. The analysis is based on the assumption that the tap weights are jointly Gaussian distributed. Residual mean squared error after convergence and simpler approximate difference equations are further developed. Results of experiment exhibit good agreement between theoretically calculated convergence and that of simulation for a wide range of parameter values of adaptive filters.

  • Implementation and Performance Evaluation of 384 kbit/s-PHS Experimental System

    Yukiyoshi KAMIO  Fumihide KOJIMA  Masayuki FUJISE  

     
    PAPER

      Vol:
    E83-B No:8
      Page(s):
    1844-1853

    A variety of mobile data communication services based on cellular phones and the PHS (Personal Handyphone System) have recently been developed and used widely. The maximum transmission rate in public mobile data communication services is currently limited to 64 kbit/s, but higher transmission rate will be needed in order to meet the requirements of mobile multimedia applications. We have therefore developed 384 kbit/s-PHS experimental system that uses the 64 kbit/s PHS data communication protocol (PIAFS) and the PPP Multilink protocol. This paper presents the implementation and performance evaluation of the 384 kbit/s-PHS experimental system. Throughtput performance of the system is evaluated using FTP under various radio propagation environments.

  • Tradeoffs between Error Performance and Decoding Complexity in Multilevel 8-PSK Codes with UEP Capabilities and Multistage Decoding

    Motohiko ISAKA  Robert H. MORELOS-ZARAGOZA  Marc P. C. FOSSORIER  Shu LIN  Hideki IMAI  

     
    PAPER-Coding Theory

      Vol:
    E83-A No:8
      Page(s):
    1704-1712

    In this paper, we investigate multilevel coding and multistage decoding for satellite broadcasting with moderate decoding complexity. An unconventional signal set partitioning is used to achieve unequal error protection capabilities. Two possibilities are shown and analyzed for practical systems: (i) linear block component codes with near optimum decoding, (ii) punctured convolutional component codes with a common trellis structure.

  • Higher-Order Cyclostationarity Based Direction Estimation of Coherent Narrow-Band Signals

    Jingmin XIN  Hiroyuki TSUJI  Akira SANO  

     
    PAPER-Applications of Signal Processing

      Vol:
    E83-A No:8
      Page(s):
    1624-1633

    To improve the resolution capability of the directions-of-arrival (DOA) estimation, some subspace-based methods have recently been developed by exploiting the specific signal properties (e.g. non-Gaussian property and cyclostationarity) of communication signals. However, these methods perform poorly as the ordinary subspace-based methods in multipath propagation situations, which are often encountered in mobile communication systems because of various reflections. In this paper, we investigate the direction estimation of coherent signals by jointly utilizing the merits of higher-order statistics and cyclostationarity to enhance the performance of DOA estimation and to effectively reject interference and noise. For estimating the DOA of narrow-band coherent signals impinging on a uniform linear array, a new higher-order cyclostationarity based approach is proposed by incorporating a subarray scheme into a linear prediction technique. This method can improve the resolution capability and alleviate the difficulty of choosing the optimal lag parameter. It is shown numerically that the proposed method is superior to the conventional ones.

  • IFS Coding of Non-Homogeneous Fractal Images Using Grobner Basis Techniques

    Toshimizu ABIKO  Masayuki KAWAMATA  

     
    PAPER-Image/Visual Signal Processing

      Vol:
    E83-A No:8
      Page(s):
    1575-1581

    This paper proposes a moment based encoding algorithm for iterated function system (IFS) coding of non-homogeneous fractal images with unequal probabilities. Moment based encoding algorithms for IFS coding of non-homogeneous fractal images require a solution of simultaneous algebraic equations that are difficult to handle with numerical root-finding methods. The proposed algorithm employs a variable elimination method using Grobner bases with floating-point coefficients in order to derive a numerically solvable equation with a single unknown. The algorithm also employs a varying associated-probabilities method for the purpose of decreasing the computational complexity of calculating Grobner bases. Experimental results show that the average computation time for encoding a non-homogeneous fractal image of 256256 pixels and 256 gray levels is about 200 seconds on a PC with a 400 MHz AMD K6-III processor.

  • An Architectural Study of an MPEG-2 422P@HL Encoder Chip Set

    Ayako HARADA  Shin-ichi HATTORI  Tadashi KASEZAWA  Hidenori SATO  Tetsuya MATSUMURA  Satoshi KUMAKI  Kazuya ISHIHARA  Hiroshi SEGAWA  Atsuo HANAMI  Yoshinori MATSUURA  Ken-ichi ASANO  Toyohiko YOSHIDA  Masahiko YOSHIMOTO  Tokumichi MURAKAMI  

     
    PAPER-Implementations of Signal Processing Systems

      Vol:
    E83-A No:8
      Page(s):
    1614-1623

    An MPEG-2 422P@HL encoder chip set composed of a preprocessing LSI, an encoding LSI, and a motion estimation LSI is described. This chip set realizes a two-type scalability of picture resolution and quality, and executes a hierarchical coding control in the overall encoder system. Due to its scalable architecture, the chip set realizes a 422P@HL video encoder with multi-chip configuration. This single encoding LSI achieves 422P@ML video, audio, and system encoding in real time. It employs an advanced hybrid architecture with a 162 MHz media processor and dedicated video processing hardware. It also has dual communication ports for parallel processing with multi-chip configuration. Transferring of reconstructed data and macroblock characteristic data between neighboring encoder modules is executed via these ports. The preprocessing LSI is fabricated using 0.25 micron three-layer metal CMOS technology and integrates 560 K gates in an area of 12.0 mm 12.0 mm . The encoding LSI is fabricated using 0.25 micron four-layer metal CMOS technology and integrates 11 million transistors in an area of 14.2 mm 14.2 mm . The motion estimation LSI is fabricated using 0.35 micron three-layer metal CMOS technology. It integrates 1.9 million transistors in an area of 8.5 mm 8.5 mm . This chip set makes various system configurations possible and allows for a compact and cost-effective video encoder with high picture quality.

  • A Sample Correlation Method for Source Number Detection

    Hsien-Tsai WU  

     
    PAPER-Applications of Signal Processing

      Vol:
    E83-A No:8
      Page(s):
    1634-1640

    In this paper, the effective uses of Gerschgorin radii of the similar transformed covariance matrix for source number estimation are introduced. A heuristic approach is used for developing the detection criteria. The heuristic approach applying the visual Gerschgorin disk method (VGD), developed from the projection concept, overcomes the problems in cases of small data samples, an unknown noise model, and data dependency. Furthermore, Gerschgorin disks can be formed into two distinct, non-overlapping collections; one for signals and the other for noises. The number of sources can be visually determined by counting the number of Gerschgorin disks for signals. The proposed method is based on the sample correlation coefficient to normalize the signal Gerschgorin radii for source number detection. The performance of VGD shows improved detection capabilities over Gerschgorin Disk Estimator (GDE) in Gaussian white noise process and was used successfully in measured experimental data.

  • Modelling Integer Programming with Logic: Language and Implementation

    Qiang LI  Yike GUO  Tetsuo IDA  

     
    PAPER-Numerical Analysis and Optimization

      Vol:
    E83-A No:8
      Page(s):
    1673-1680

    The classical algebraic modelling approach for integer programming (IP) is not suitable for some real world IP problems, since the algebraic formulations allow only for the description of mathematical relations, not logical relations. In this paper, we present a language + for IP, in which we write logical specification of an IP problem. + is a language based on the predicate logic, but is extended with meta predicates such as at_least(m,S), where m is a non-negative integer, meaning that at least m predicates in the set S of formulas hold. The meta predicates facilitate reasoning about a model of an IP problem rigorously and logically. + is executable in the sense that formulas in + are mechanically translated into a set of mathematical formulas, called IP formulas, which most of existing IP solvers accept. We give a systematic method for translating formulas in + to IP formulas. The translation is rigorously defined, verified and implemented in Mathematica 3.0. Our work follows the approach of McKinnon and Williams, and elaborated the language in that (1) it is rigorously defined, (2) transformation to IP formulas is more optimised and verified, and (3) the transformation is completely given in Mathematica 3.0 and is integrated into IP solving environment as a tool for IP.

  • A New FPGA Architecture for High Performance Bit-Serial Pipeline Datapath

    Akihisa OHTA  Tsuyoshi ISSHIKI  Hiroaki KUNIEDA  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E83-A No:8
      Page(s):
    1663-1672

    In this paper, we present our work on the design of a new FPGA architecture targeted for high-performance bit-serial pipeline datapath. Bit-parallel systems require large amount of routing resource which is especially critical in using FPGAs. Their device utilization and operation frequency become low because of large routing penalty. Whereas bit-serial circuits are very efficient in routing, therefore are able to achieve a very high logic utilization. Our proposed FPGA architecture is designed taking into account the structure of bit-serial circuits to optimize the logic and routing architecture. Our FPGA guarantees near 100% logic utilization with a straightforward place and route tool due to high routability of bit-serial circuits and simple routing interconnect architecture. The FPGA chip core which we designed consists of around 200k transistors on 3.5 mm square substrate using 0.5 µm 2-metal CMOS process technology.

24181-24200hit(30728hit)