This letter presents a global feature-based method for evaluating the no reference quality of scanning electron microscopy (SEM) contrast-distorted images. Based on the characteristics of SEM images and the human visual system, the global features of SEM images are extracted as the score for evaluating image quality. In this letter, the texture information of SEM images is first extracted using a low-pass filter with orientation, and the amount of information in the texture part is calculated based on the entropy reflecting the complexity of the texture. The singular values with four scales of the original image are then calculated, and the amount of structural change between different scales is calculated and averaged. Finally, the amounts of texture information and structural change are pooled to generate the final quality score of the SEM image. Experimental results show that the method can effectively evaluate the quality of SEM contrast-distorted images.

In this paper, we study the properties of the sum-of-squares indicator of vectorial Boolean functions. Firstly, we give the upper bound of $sum_{uin mathbb{F}_2^n,vin mathbb{F}_2^m}mathcal{W}_F^3(u,v)$. Secondly, based on the Walsh-Hadamard transform, we give a secondary construction of vectorial bent functions. Further, three kinds of sum-of-squares indicators of vectorial Boolean functions are defined by autocorrelation function and the lower and upper bounds of the sum-of-squares indicators are derived. Finally, we study the sum-of-squares indicators with respect to several equivalence relations, and get the sum-of-squares indicator which have the best cryptographic properties.

At a flash memory, each stored data frame is protected by error correction codes (ECC) such as Bose-Chaudhuri-Hocquenghem (BCH) codes from random errors. Exclusive-OR (XOR) based erasure codes like RAID-5 have also been employed at the flash memory to protect from memory block defects. Conventionally, the ECC and erasure codes are used separately since their target errors are different. Due to recent aggressive technology scaling, additional error correction capability for random errors is required without adding redundancy. We propose an algorithm to improve error correction capability by using XOR parity with a simple counter that counts the number of unreliable bits in the XOR stripe. We also propose to apply Chase decoding to the proposed algorithm. The counter makes it possible to reduce the false correction and execute the efficient Chase decoding. We show that combining the proposed algorithm with Chase decoding can significantly improve the decoding performance.

The design of codes for distributed storage systems that protects from node failures has been studied for years, and locally repairable code (LRC) is such a method that gives a solution for fast recovery of node failures. Linear complementary dual code (LCD code) is useful for preventing malicious attacks, which helps to secure the system. In this paper, we combine LRC and LCD code by integration of enhancing security and repair efficiency, and propose some techniques for constructing LCD codes with their localities determined. On the basis of these methods and inheriting previous achievements of optimal LCD codes, we give optimal or near-optimal [n, k, d;r] LCD codes for k≤6 and n≥k+1 with relatively small locality, mostly r≤3. Since all of our obtained codes are distance-optimal, in addition, we show that the majority of them are r-optimal and the other 63 codes are all near r-optimal, according to CM bound.

Recent years have seen a decline in the art of analog IC design even though analog interface and analog signal processing remain just as essential as ever. While there are many contributing factors, four specific pressures which contribute the most to the loss of creativity and innovation within analog practice are examined: process evolution, risk aversion, digitally assisted analog, and corporate culture. Despite the potency of these forces, none are found to be insurmountable obstacles to reinvigorating the industry. A more creative future is within our reach.

In this paper, we propose a hybrid crystal oscillator which achieves both quick startup and low steady-state power consumption. At startup, a large negative resistance is realized by configuring a Pierce oscillating circuit with a multi-stage inverter amplifier, resulting in high-speed startup. During steady-state oscillation, the oscillator is reconfigured as a class-C complementary Colpitts circuit for low power consumption and low phase noise. Prototype chips were fabricated in 65nm CMOS process technology. With Pierce-type configuration, the measured startup time and startup energy of the oscillator are reduced to 1/11 and 1/5, respectively, compared with the one without Pierce-type configuration. The power consumption during steady oscillation is 30 µW.

This paper presents a divide-by-9 injection-locked frequency divider (ILFD). It can lock onto about 6-GHz input with a locking range of 3.23GHz (58%). The basic concept of the ILFD is based on employing self-gated multiple inputs into the multiple-stage ring oscillator. A wide lock range is also realized by adapting harmonic-control circuits, which can boost specific harmonics generated by mixing. The ILFD was fabricated using a 55-nm deeply depleted channel (DDC) CMOS process. It occupies an area of 0.0210mm2, and consumes a power of 14.4mW.

This paper presents a high-NIR sensitivity SOI-gate lock-in pixel with improved modulation contrast. The proposed pixel has a shallow buried channel and intermediate gates to create both a high lateral electric field and a potential barrier to parasitic light sensitivity. Device simulation results showed that parasitic light sensitivity reduced from 13.7% to 0.13% compared to the previous structure.

Energy harvesting has been widely investigated as a potential solution to supply power for Internet of Things (IoT) devices. Computing devices must operate intermittently rather than continuously, because harvested energy is unstable and some of IoT applications can be periodic. Therefore, processors for IoT devices with intermittent operation must feature a hibernation mode with zero-standby-power in addition to energy-efficient normal mode. In this paper, we describe the layout design and measurement results of a nonvolatile standard cell memory (NV-SCM) and nonvolatile flip-flops (NV-FF) with a nonvolatile memory using Fishbone-in-Cage Capacitor (FiCC) suitable for IoT processors with intermittent operations. They can be fabricated in any conventional CMOS process without any additional mask. NV-SCM and NV-FF are fabricated in a 180nm CMOS process technology. The area overhead by nonvolatility of a bit cell are 74% in NV-SCM and 29% in NV-FF, respectively. We confirmed full functionality of the NV-SCM and NV-FF. The nonvolatile system using proposed NV-SCM and NV-FF can reduce the energy consumption by 24.3% compared to the volatile system when hibernation/normal operation time ratio is 500 as shown in the simulation.

This paper presents on-chip characterization of electrostatic discharge (ESD) impacts applied on the Si-substrate backside of a flip-chip mounted integrated circuit (FC-IC) chip. An FC-IC chip has an open backside and there is a threat of reliability problems and malfunctions caused by the backside ESD. We prepared a test FC-IC chip and measured Si-substrate voltage fluctuations on its frontside by an on-chip monitor (OCM) circuit. The voltage surges as large as 200mV were observed on the frontside when a 200-V ESD gun was irradiated through a 5kΩ contact resistor on the backside of a 350μm thick Si substrate. The distribution of voltage heights was experimentally measured at 20 on-chip locations among thinned Si substrates up to 40μm, and also explained in full-system level simulation of backside ESD impacts with the equivalent models of ESD-gun operation and FC-IC chip assembly.

Reducing on-chip microwave crosstalk is crucial for semiconductor spin qubit integration. Toward crosstalk reduction and qubit integration, we investigate on-chip microwave crosstalk for gate electrode pad designs with (i) etched trenches between contact pads or (ii) contact pads with reduced sizes. We conclude that the design with feature (ii) is advantageous for high-density integration of semiconductor qubits with small crosstalk (below -25 dB at 6 GHz), favoring the introduction of flip-chip bonding.

The transfer distance of the wireless power transfer (WPT) system with relay coil is longer, so this technology have a better practical perspective. But the location of the relay coil has a great impact on the transmission efficiency of the WPT system, and it is not easy to analyze. In order to research the influence law of the relay coil location on the transmission efficiency and obtain the optimal location, the paper firstly proposes the concept of relay coil location factor. And based on the location factor, a novel method for studying the influence of the relay coil location on the transmission efficiency is proposed. First, the mathematical model between the transmission efficiency and the location factor is built. Next, considering the transfer distance, coil radius, coil turns and load resistance, a lot of simulations are carried out to analyze the influence of the location factor on the transmission efficiency, respectively. The influence law and the optimal location factor were obtained with different parameters. Finally, a WPT system with relay coil was built for experiments. And the experiment results verify that the theoretical analysis is correct and the proposed method can simplify the analysis progress of the influence of relay coil location on the transmission efficiency. Moreover, the proposed method and the research conclusions can provide guidance for designing the multiple coils structure WPT system.

Personalized stock recommendations aim to suggest stocks tailored to individual investor needs, significantly aiding the financial decision making of an investor. This study shows the advantages of incorporating context into personalized stock recommendation systems. We embed item contextual information such as technical indicators, fundamental factors, and business activities of individual stocks. Simultaneously, we consider user contextual information such as investors' personality traits, behavioral characteristics, and attributes to create a comprehensive investor profile. Our model incorporating contextual information, validated on novel stock recommendation tasks, demonstrated a notable improvement over baseline models when incorporating these contextual features. Consistent outperformance across various hyperparameters further underscores the robustness and utility of our model in integrating stocks' features and investors' traits into personalized stock recommendations.

A fault-tolerant aggregate signature (FT-AS) scheme is a variant of an aggregate signature scheme with the additional functionality to trace signers that create invalid signatures in case an aggregate signature is invalid. Several FT-AS schemes have been proposed so far, and some of them trace such rogue signers in multi-rounds, i.e., the setting where the signers repeatedly send their individual signatures. However, it has been overlooked that there exists a potential attack on the efficiency of bandwidth consumption in a multi-round FT-AS scheme. Since one of the merits of aggregate signature schemes is the efficiency of bandwidth consumption, such an attack might be critical for multi-round FT-AS schemes. In this paper, we propose a new multi-round FT-AS scheme that is tolerant of such an attack. We implement our scheme and experimentally show that it is more efficient than the existing multi-round FT-AS scheme if rogue signers randomly create invalid signatures with low probability, which for example captures spontaneous failures of devices in IoT systems.

This paper develops a design method and theoretical analysis for piecewise nonlinear oscillators that have desired circular limit cycles. Especially, the mathematical proof on existence, uniqueness, and stability of the limit cycle is shown for the piecewise nonlinear oscillator. In addition, the relationship between parameters in the oscillator and rotational directions and periods of the limit cycle trajectories is investigated. Then, some numerical simulations show that the piecewise nonlinear oscillator has a unique and stable limit cycle and the properties on rotational directions and periods hold.

We developed a self-controllable voltage level (SVL) circuit and applied this circuit to a single-power-supply, six-transistor complementary metal-oxide-semiconductor static random-access memory (SRAM) to not only improve both write and read performances but also to achieve low standby power and data retention (holding) capability. The SVL circuit comprises only three MOSFETs (i.e., pull-up, pull-down and bypass MOSFETs). The SVL circuit is able to adaptively generate both optimal memory cell voltages and word line voltages depending on which mode of operation (i.e., write, read or hold operation) was used. The write margin (VWM) and read margin (VRM) of the developed (dvlp) SRAM at a supply voltage (VDD) of 1V were 0.470 and 0.1923V, respectively. These values were 1.309 and 2.093 times VWM and VRM of the conventional (conv) SRAM, respectively. At a large threshold voltage (Vt) variability (=+6σ), the minimum power supply voltage (VMin) for the write operation of the conv SRAM was 0.37V, whereas it decreased to 0.22V for the dvlp SRAM. VMin for the read operation of the conv SRAM was 1.05V when the Vt variability (=-6σ) was large, but the dvlp SRAM lowered it to 0.41V. These results show that the SVL circuit expands the operating voltage range for both write and read operations to lower voltages. The dvlp SRAM reduces the standby power consumption (PST) while retaining data. The measured PST of the 2k-bit, 90-nm dvlp SRAM was only 0.957µW at VDD=1.0V, which was 9.46% of PST of the conv SRAM (10.12µW). The Si area overhead of the SVL circuits was only 1.383% of the dvlp SRAM.

A fully analog pipelined deep neural network (DNN) accelerator is proposed, which is constructed by using pipeline registers based on master-slave switched capacitors. The idea of the master-slave switched capacitors is an analog equivalent of the delayed flip-flop (D-FF) which has been used as a digital pipeline register. To estimate the performance of the pipeline register, it is applied to a conventional DNN which performs non-pipeline operation. Compared with the conventional DNN, the cycle time is reduced by 61.5% and data rate is increased by 160%. The accuracy reaches 99.6% in MNIST classification test. The energy consumption per classification is reduced by 88.2% to 0.128µJ, achieving an energy efficiency of 1.05TOPS/W and a throughput of 0.538TOPS in 180nm technology node.

A novel displacement sensor was proposed based on a frequency delta-sigma modulator (FDSM) employing a microwave oscillator. To demonstrate basic operation, we fabricated a stylus surface profiler using a cylindrical cavity resonator, where one end of the cavity is replaced by a thin metal diaphragm with a stylus probe tip. Good surface profile was successfully obtained with this device. A 10 nm depth trench was clearly observed together with a 10 µm trench in a single scan without gain control. This result clearly demonstrates an extremely wide dynamic range of the FDSM displacement sensors.

Wireless technology improvements have been continually increasing, resulting in greater needs for system design and implementation to accommodate all newly emerging standards. As a result, developing a system that ensures compatibility with numerous wireless systems has sparked interest. As a result of their flexibility and scalability over alternative wireless design options, software-defined radios (SDRs) are highly motivated for wireless device modelling. This research paper delves into the difficulties of designing a reconfigurable multi modulation baseband modulator for SDR systems that can handle a variety of wireless protocols. This research paper has proposed an area-efficient Reconfigurable Baseband Modulator (RBM) model to accomplish multi modulation scheme and resolve the adaptability and flexibility issues with the wide range of wireless standards. This also presents the feasibility of using a multi modulation baseband modulator to maximize adaptability with the least possible computational complexity overhead in the SDR system for next-generation wireless communication systems and provides parameterization. Finally, the re-configurability is evaluated concerning the appropriate symbols generations and analyzed its performance metrics through hardware synthesize results.

Physical Unclonable Function (PUF) is a promising lightweight hardware security primitive that can extract device fingerprints for encryption or authentication. However, extracting fingerprints from either the chip or the board individually has security flaws and cannot provide hardware system-level security. This paper proposes a new Chip-PCB hybrid PUF(CPR PUF) in which Weak PUF on PCB is combined with Strong PUF inside the chip to generate massive responses under the control of challenges of on-chip Strong PUF. This structure tightly couples the chip and PCB into an inseparable and unclonable unit thus can verify the authenticity of chip as well as the board. To improve the uniformity and reliability of Chip-PCB hybrid PUF, we propose a lightweight key generator based on a reliability self-test and debiasing algorithm to extract massive stable and secure keys from unreliable and biased PUF responses, which eliminates expensive error correction processes. The FPGA-based test results show that the PUF responses after robust extraction and debiasing achieve high uniqueness, reliability, uniformity and anti-counterfeiting features. Moreover, the key generator greatly reduces the execution cost and the bit error rate of the keys is less than 10-9, the overall security of the key is also improved by eliminating the entropy leakage of helper data.